base_dyn_inst.hh (12421:871001341442) base_dyn_inst.hh (12748:ae5ce8e42de7)
1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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888};
889
890template<class Impl>
891Fault
892BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
893 Request::Flags flags)
894{
895 instFlags[ReqMade] = true;
1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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888};
889
890template<class Impl>
891Fault
892BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
893 Request::Flags flags)
894{
895 instFlags[ReqMade] = true;
896 Request *req = NULL;
897 Request *sreqLow = NULL;
898 Request *sreqHigh = NULL;
896 RequestPtr req = NULL;
897 RequestPtr sreqLow = NULL;
898 RequestPtr sreqHigh = NULL;
899
900 if (instFlags[ReqMade] && translationStarted()) {
901 req = savedReq;
902 sreqLow = savedSreqLow;
903 sreqHigh = savedSreqHigh;
904 } else {
905 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
906 thread->contextId());

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944Fault
945BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
946 Request::Flags flags, uint64_t *res)
947{
948 if (traceData)
949 traceData->setMem(addr, size, flags);
950
951 instFlags[ReqMade] = true;
899
900 if (instFlags[ReqMade] && translationStarted()) {
901 req = savedReq;
902 sreqLow = savedSreqLow;
903 sreqHigh = savedSreqHigh;
904 } else {
905 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
906 thread->contextId());

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944Fault
945BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
946 Request::Flags flags, uint64_t *res)
947{
948 if (traceData)
949 traceData->setMem(addr, size, flags);
950
951 instFlags[ReqMade] = true;
952 Request *req = NULL;
953 Request *sreqLow = NULL;
954 Request *sreqHigh = NULL;
952 RequestPtr req = NULL;
953 RequestPtr sreqLow = NULL;
954 RequestPtr sreqHigh = NULL;
955
956 if (instFlags[ReqMade] && translationStarted()) {
957 req = savedReq;
958 sreqLow = savedSreqLow;
959 sreqHigh = savedSreqHigh;
960 } else {
961 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
962 thread->contextId());

--- 136 unchanged lines hidden --- 		955
956 if (instFlags[ReqMade] && translationStarted()) {
957 req = savedReq;
958 sreqLow = savedSreqLow;
959 sreqHigh = savedSreqHigh;
960 } else {
961 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
962 thread->contextId());

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