base_dyn_inst.hh (12106:7784fac1b159) base_dyn_inst.hh (12107:998b4c54ee51)
1/*
1/*
2 * Copyright (c) 2011,2013 ARM Limited
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <list>
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <list>
52#include <string>
53#include <queue>
52#include <queue>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/exec_context.hh"
62#include "cpu/exetrace.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71

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89 // The list of instructions iterator type.
90 typedef typename std::list<DynInstPtr>::iterator ListIt;
91
92 enum {
93 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
94 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
95 };
96
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72

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90 // The list of instructions iterator type.
91 typedef typename std::list<DynInstPtr>::iterator ListIt;
92
93 enum {
94 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
95 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
96 };
97
97 union Result {
98 uint64_t integer;
99 double dbl;
100 void set(uint64_t i) { integer = i; }
101 void set(double d) { dbl = d; }
102 void get(uint64_t& i) { i = integer; }
103 void get(double& d) { d = dbl; }
104 };
105
106 protected:
107 enum Status {
108 IqEntry, /// Instruction is in the IQ
109 RobEntry, /// Instruction is in the ROB
110 LsqEntry, /// Instruction is in the LSQ
111 Completed, /// Instruction has completed
112 ResultReady, /// Instruction has its result
113 CanIssue, /// Instruction can issue and execute

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169
170 /** InstRecord that tracks this instructions. */
171 Trace::InstRecord *traceData;
172
173 protected:
174 /** The result of the instruction; assumes an instruction can have many
175 * destination registers.
176 */
98 protected:
99 enum Status {
100 IqEntry, /// Instruction is in the IQ
101 RobEntry, /// Instruction is in the ROB
102 LsqEntry, /// Instruction is in the LSQ
103 Completed, /// Instruction has completed
104 ResultReady, /// Instruction has its result
105 CanIssue, /// Instruction can issue and execute

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161
162 /** InstRecord that tracks this instructions. */
163 Trace::InstRecord *traceData;
164
165 protected:
166 /** The result of the instruction; assumes an instruction can have many
167 * destination registers.
168 */
177 std::queue instResult;
169 std::queue<InstResult> instResult;
178
179 /** PC state for this instruction. */
180 TheISA::PCState pc;
181
182 /* An amalgamation of a lot of boolean values into one */
183 std::bitset<MaxFlags> instFlags;
184
185 /** The status of this BaseDynInst. Several bits can be set. */

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601 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
602
603 /** Returns the logical register index of the i'th destination register. */
604 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
605
606 /** Returns the logical register index of the i'th source register. */
607 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
608
170
171 /** PC state for this instruction. */
172 TheISA::PCState pc;
173
174 /* An amalgamation of a lot of boolean values into one */
175 std::bitset<MaxFlags> instFlags;
176
177 /** The status of this BaseDynInst. Several bits can be set. */

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593 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
594
595 /** Returns the logical register index of the i'th destination register. */
596 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
597
598 /** Returns the logical register index of the i'th source register. */
599 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
600
609 /** Pops a result off the instResult queue */
610 template <class T>
611 void popResult(T& t)
601 /** Return the size of the instResult queue. */
602 uint8_t resultSize() { return instResult.size(); }
603
604 /** Pops a result off the instResult queue.
605 * If the result stack is empty, return the default value.
606 * */
607 InstResult popResult(InstResult dflt = InstResult())
612 {
613 if (!instResult.empty()) {
608 {
609 if (!instResult.empty()) {
614 instResult.front().get(t);
610 InstResult t = instResult.front();
615 instResult.pop();
611 instResult.pop();
612 return t;
616 }
613 }
614 return dflt;
617 }
618
615 }
616
619 /** Read the most recent result stored by this instruction */
620 template <class T>
621 void readResult(T& t)
617 /** Pushes a result onto the instResult queue. */
618 template<typename T>
619 void setScalarResult(T&& t)
622 {
620 {
623 instResult.back().get(t);
624 }
625
626 /** Pushes a result onto the instResult queue */
627 template <class T>
628 void setResult(T t)
629 {
630 if (instFlags[RecordResult]) {
621 if (instFlags[RecordResult]) {
631 Result instRes;
632 instRes.set(t);
633 instResult.push(instRes);
622 instResult.push(InstResult(std::forward<T>(t),
623 InstResult::ResultType::Scalar));
634 }
635 }
636
637 /** Records an integer register being set to a value. */
638 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
639 {
624 }
625 }
626
627 /** Records an integer register being set to a value. */
628 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
629 {
640 setResult<uint64_t>(val);
630 setScalarResult(val);
641 }
642
643 /** Records a CC register being set to a value. */
644 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
645 {
631 }
632
633 /** Records a CC register being set to a value. */
634 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
635 {
646 setResult<uint64_t>(val);
636 setScalarResult(val);
647 }
648
649 /** Records an fp register being set to a value. */
650 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
651 {
637 }
638
639 /** Records an fp register being set to a value. */
640 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
641 {
652 setResult<double>(val);
642 setScalarResult(val);
653 }
654
655 /** Records an fp register being set to an integer value. */
643 }
644
645 /** Records an fp register being set to an integer value. */
656 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
646 void
647 setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
657 {
648 {
658 setResult<uint64_t>(val);
649 setScalarResult(val);
659 }
660
661 /** Records that one of the source registers is ready. */
662 void markSrcRegReady();
663
664 /** Marks a specific register as ready. */
665 void markSrcRegReady(RegIndex src_idx);
666

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651
652 /** Records that one of the source registers is ready. */
653 void markSrcRegReady();
654
655 /** Marks a specific register as ready. */
656 void markSrcRegReady(RegIndex src_idx);
657

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