base_dyn_inst.hh (11435:0f1b46dde3fa) base_dyn_inst.hh (11608:6319a1125f1c)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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60#include "cpu/o3/comm.hh"
61#include "cpu/exec_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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60#include "cpu/o3/comm.hh"
61#include "cpu/exec_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
68#include "sim/byteswap.hh"
69#include "sim/system.hh"
70
71/**
72 * @file
73 * Defines a dynamic instruction context.
74 */
75

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308 {
309 cpu->demapPage(vaddr, asn);
310 }
311 void demapDataPage(Addr vaddr, uint64_t asn)
312 {
313 cpu->demapPage(vaddr, asn);
314 }
315
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76

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309 {
310 cpu->demapPage(vaddr, asn);
311 }
312 void demapDataPage(Addr vaddr, uint64_t asn)
313 {
314 cpu->demapPage(vaddr, asn);
315 }
316
316 Fault initiateMemRead(Addr addr, unsigned size, unsigned flags);
317 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
317
318
318 Fault writeMem(uint8_t *data, unsigned size,
319 Addr addr, unsigned flags, uint64_t *res);
319 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
320 Request::Flags flags, uint64_t *res);
320
321 /** Splits a request in two if it crosses a dcache block. */
322 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
323 RequestPtr &sreqHigh);
324
325 /** Initiate a DTB address translation. */
326 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
327 RequestPtr sreqHigh, uint64_t *res,

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868 void mwaitAtomic(ThreadContext *tc)
869 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
870 AddressMonitor *getAddrMonitor()
871 { return cpu->getCpuAddrMonitor(threadNumber); }
872};
873
874template<class Impl>
875Fault
321
322 /** Splits a request in two if it crosses a dcache block. */
323 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
324 RequestPtr &sreqHigh);
325
326 /** Initiate a DTB address translation. */
327 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
328 RequestPtr sreqHigh, uint64_t *res,

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869 void mwaitAtomic(ThreadContext *tc)
870 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
871 AddressMonitor *getAddrMonitor()
872 { return cpu->getCpuAddrMonitor(threadNumber); }
873};
874
875template<class Impl>
876Fault
876BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, unsigned flags)
877BaseDynInst::initiateMemRead(Addr addr, unsigned size,
878 Request::Flags flags)
877{
878 instFlags[ReqMade] = true;
879 Request *req = NULL;
880 Request *sreqLow = NULL;
881 Request *sreqHigh = NULL;
882
883 if (instFlags[ReqMade] && translationStarted()) {
884 req = savedReq;

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920 if (traceData)
921 traceData->setMem(addr, size, flags);
922
923 return fault;
924}
925
926template<class Impl>
927Fault
879{
880 instFlags[ReqMade] = true;
881 Request *req = NULL;
882 Request *sreqLow = NULL;
883 Request *sreqHigh = NULL;
884
885 if (instFlags[ReqMade] && translationStarted()) {
886 req = savedReq;

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922 if (traceData)
923 traceData->setMem(addr, size, flags);
924
925 return fault;
926}
927
928template<class Impl>
929Fault
928BaseDynInst::writeMem(uint8_t *data, unsigned size,
929 Addr addr, unsigned flags, uint64_t *res)
930BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
931 Request::Flags flags, uint64_t *res)
930{
931 if (traceData)
932 traceData->setMem(addr, size, flags);
933
934 instFlags[ReqMade] = true;
935 Request *req = NULL;
936 Request *sreqLow = NULL;
937 Request *sreqHigh = NULL;

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933 if (traceData)
934 traceData->setMem(addr, size, flags);
935
936 instFlags[ReqMade] = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;

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