base_dyn_inst.hh (11005:e7f403b6b76f) base_dyn_inst.hh (11097:da477ae38907)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 201 unchanged lines hidden (view full) ---

210 uint8_t readyRegs;
211
212 public:
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
215 Addr effAddr;
216
217 /** The effective physical address. */
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 201 unchanged lines hidden (view full) ---

210 uint8_t readyRegs;
211
212 public:
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
215 Addr effAddr;
216
217 /** The effective physical address. */
218 Addr physEffAddr;
218 Addr physEffAddrLow;
219
219
220 /** The effective physical address
221 * of the second request for a split request
222 */
223 Addr physEffAddrHigh;
224
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
222
223 /** data address space ID, for loads & stores. */
224 short asid;
225
226 /** The size of the request */
227 uint8_t effSize;

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1051inline void
1052BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1053{
1054 fault = state->getFault();
1055
1056 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1057
1058 if (fault == NoFault) {
225 /** The memory request flags (from translation). */
226 unsigned memReqFlags;
227
228 /** data address space ID, for loads & stores. */
229 short asid;
230
231 /** The size of the request */
232 uint8_t effSize;

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1056inline void
1057BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1058{
1059 fault = state->getFault();
1060
1061 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1062
1063 if (fault == NoFault) {
1059 physEffAddr = state->getPaddr();
1064 // save Paddr for a single req
1065 physEffAddrLow = state->getPaddr();
1066
1067 // case for the request that has been split
1068 if (state->isSplit) {
1069 physEffAddrLow = state->sreqLow->getPaddr();
1070 physEffAddrHigh = state->sreqHigh->getPaddr();
1071 }
1072
1060 memReqFlags = state->getFlags();
1061
1062 if (state->mainReq->isCondSwap()) {
1063 assert(state->res);
1064 state->mainReq->setExtraData(*state->res);
1065 }
1066
1067 } else {
1068 state->deleteReqs();
1069 }
1070 delete state;
1071
1072 translationCompleted(true);
1073}
1074
1075#endif // __CPU_BASE_DYN_INST_HH__
1073 memReqFlags = state->getFlags();
1074
1075 if (state->mainReq->isCondSwap()) {
1076 assert(state->res);
1077 state->mainReq->setExtraData(*state->res);
1078 }
1079
1080 } else {
1081 state->deleteReqs();
1082 }
1083 delete state;
1084
1085 translationCompleted(true);
1086}
1087
1088#endif // __CPU_BASE_DYN_INST_HH__