base_dyn_inst.hh (10934:5af8f40d8f2c) base_dyn_inst.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 union Result {
100 uint64_t integer;
101 double dbl;
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 union Result {
100 uint64_t integer;
101 double dbl;
102
103 // I am assuming that vector register type is different from the two
104 // types used above. Else it seems useless to have a separate typedef
105 // for vector registers.
106 VectorReg vector;
107
108 void set(uint64_t i) { integer = i; }
109 void set(double d) { dbl = d; }
102 void set(uint64_t i) { integer = i; }
103 void set(double d) { dbl = d; }
110 void set(const VectorReg &v) { vector = v; }
111
112 void get(uint64_t& i) { i = integer; }
113 void get(double& d) { d = dbl; }
104 void get(uint64_t& i) { i = integer; }
105 void get(double& d) { d = dbl; }
114 void get(VectorReg& v) { v = vector; }
115 };
116
117 protected:
118 enum Status {
119 IqEntry, /// Instruction is in the IQ
120 RobEntry, /// Instruction is in the ROB
121 LsqEntry, /// Instruction is in the LSQ
122 Completed, /// Instruction has completed

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525 bool isLoad() const { return staticInst->isLoad(); }
526 bool isStore() const { return staticInst->isStore(); }
527 bool isStoreConditional() const
528 { return staticInst->isStoreConditional(); }
529 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
530 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
531 bool isInteger() const { return staticInst->isInteger(); }
532 bool isFloating() const { return staticInst->isFloating(); }
106 };
107
108 protected:
109 enum Status {
110 IqEntry, /// Instruction is in the IQ
111 RobEntry, /// Instruction is in the ROB
112 LsqEntry, /// Instruction is in the LSQ
113 Completed, /// Instruction has completed

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516 bool isLoad() const { return staticInst->isLoad(); }
517 bool isStore() const { return staticInst->isStore(); }
518 bool isStoreConditional() const
519 { return staticInst->isStoreConditional(); }
520 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
521 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
522 bool isInteger() const { return staticInst->isInteger(); }
523 bool isFloating() const { return staticInst->isFloating(); }
533 bool isVector() const { return staticInst->isVector(); }
534 bool isCC() const { return staticInst->isCC(); }
535
536 bool isControl() const { return staticInst->isControl(); }
537 bool isCall() const { return staticInst->isCall(); }
538 bool isReturn() const { return staticInst->isReturn(); }
539 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
540 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
541 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
542 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
543 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }

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557 bool isSyscall() const { return staticInst->isSyscall(); }
558 bool isMacroop() const { return staticInst->isMacroop(); }
559 bool isMicroop() const { return staticInst->isMicroop(); }
560 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
561 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
562 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
563 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
564
524 bool isControl() const { return staticInst->isControl(); }
525 bool isCall() const { return staticInst->isCall(); }
526 bool isReturn() const { return staticInst->isReturn(); }
527 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
528 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
529 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
530 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
531 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }

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545 bool isSyscall() const { return staticInst->isSyscall(); }
546 bool isMacroop() const { return staticInst->isMacroop(); }
547 bool isMicroop() const { return staticInst->isMicroop(); }
548 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
549 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
550 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
551 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
552
565 void printFlags(std::ostream &outs, const std::string &separator) const
566 { staticInst->printFlags(outs, separator); }
567
568 std::string getName() const { return staticInst->getName(); }
569
570 /** Temporarily sets this instruction as a serialize before instruction. */
571 void setSerializeBefore() { status.set(SerializeBefore); }
572
573 /** Clears the serializeBefore part of this instruction. */
574 void clearSerializeBefore() { status.reset(SerializeBefore); }
575
576 /** Checks if this serializeBefore is only temporarily set. */
577 bool isTempSerializeBefore() { return status[SerializeBefore]; }

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608 /** Returns the number of destination registers. */
609 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
610
611 // the following are used to track physical register usage
612 // for machines with separate int & FP reg files
613 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
614 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
615 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
553 /** Temporarily sets this instruction as a serialize before instruction. */
554 void setSerializeBefore() { status.set(SerializeBefore); }
555
556 /** Clears the serializeBefore part of this instruction. */
557 void clearSerializeBefore() { status.reset(SerializeBefore); }
558
559 /** Checks if this serializeBefore is only temporarily set. */
560 bool isTempSerializeBefore() { return status[SerializeBefore]; }

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591 /** Returns the number of destination registers. */
592 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
593
594 // the following are used to track physical register usage
595 // for machines with separate int & FP reg files
596 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
597 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
598 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
616 int8_t numVectorDestRegs() const
617 { return staticInst->numVectorDestRegs(); }
618
619 /** Returns the logical register index of the i'th destination register. */
620 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
621
622 /** Returns the logical register index of the i'th source register. */
623 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
624
625 /** Pops a result off the instResult queue */

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669 }
670
671 /** Records an fp register being set to an integer value. */
672 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
673 {
674 setResult<uint64_t>(val);
675 }
676
599
600 /** Returns the logical register index of the i'th destination register. */
601 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
602
603 /** Returns the logical register index of the i'th source register. */
604 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
605
606 /** Pops a result off the instResult queue */

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650 }
651
652 /** Records an fp register being set to an integer value. */
653 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
654 {
655 setResult<uint64_t>(val);
656 }
657
677 /** Records a vector register being set to a value. */
678 void setVectorRegOperand(const StaticInst *si, int idx,
679 const VectorReg &val)
680 {
681 setResult<const VectorReg &>(val);
682 }
683
684 /** Records that one of the source registers is ready. */
685 void markSrcRegReady();
686
687 /** Marks a specific register as ready. */
688 void markSrcRegReady(RegIndex src_idx);
689
690 /** Returns if a source register is ready. */
691 bool isReadySrcRegIdx(int idx) const

--- 410 unchanged lines hidden --- 		658 /** Records that one of the source registers is ready. */
659 void markSrcRegReady();
660
661 /** Marks a specific register as ready. */
662 void markSrcRegReady(RegIndex src_idx);
663
664 /** Returns if a source register is ready. */
665 bool isReadySrcRegIdx(int idx) const

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