base_dyn_inst.hh (10190:fb83d025d1c3) | base_dyn_inst.hh (10319:4207f9bfcceb) |
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1/* 2 * Copyright (c) 2011,2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 42 unchanged lines hidden (view full) --- 51#include <string> 52#include <queue> 53 54#include "arch/utility.hh" 55#include "base/trace.hh" 56#include "config/the_isa.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/o3/comm.hh" | 1/* 2 * Copyright (c) 2011,2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 42 unchanged lines hidden (view full) --- 51#include <string> 52#include <queue> 53 54#include "arch/utility.hh" 55#include "base/trace.hh" 56#include "config/the_isa.hh" 57#include "cpu/checker/cpu.hh" 58#include "cpu/o3/comm.hh" |
59#include "cpu/exec_context.hh" |
|
59#include "cpu/exetrace.hh" 60#include "cpu/inst_seq.hh" 61#include "cpu/op_class.hh" 62#include "cpu/static_inst.hh" 63#include "cpu/translation.hh" 64#include "mem/packet.hh" 65#include "sim/byteswap.hh" 66#include "sim/fault_fwd.hh" 67#include "sim/system.hh" 68#include "sim/tlb.hh" 69 70/** 71 * @file 72 * Defines a dynamic instruction context. 73 */ 74 75template <class Impl> | 60#include "cpu/exetrace.hh" 61#include "cpu/inst_seq.hh" 62#include "cpu/op_class.hh" 63#include "cpu/static_inst.hh" 64#include "cpu/translation.hh" 65#include "mem/packet.hh" 66#include "sim/byteswap.hh" 67#include "sim/fault_fwd.hh" 68#include "sim/system.hh" 69#include "sim/tlb.hh" 70 71/** 72 * @file 73 * Defines a dynamic instruction context. 74 */ 75 76template <class Impl> |
76class BaseDynInst : public RefCounted | 77class BaseDynInst : public ExecContext, public RefCounted |
77{ 78 public: 79 // Typedef for the CPU. 80 typedef typename Impl::CPUType ImplCPU; 81 typedef typename ImplCPU::ImplState ImplState; 82 83 // Logical register index type. 84 typedef TheISA::RegIndex RegIndex; | 78{ 79 public: 80 // Typedef for the CPU. 81 typedef typename Impl::CPUType ImplCPU; 82 typedef typename ImplCPU::ImplState ImplState; 83 84 // Logical register index type. 85 typedef TheISA::RegIndex RegIndex; |
85 // Integer register type. 86 typedef TheISA::IntReg IntReg; 87 // Floating point register type. 88 typedef TheISA::FloatReg FloatReg; | |
89 90 // The DynInstPtr type. 91 typedef typename Impl::DynInstPtr DynInstPtr; 92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 93 94 // The list of instructions iterator type. 95 typedef typename std::list<DynInstPtr>::iterator ListIt; 96 --- 532 unchanged lines hidden (view full) --- 629 if (instFlags[RecordResult]) { 630 Result instRes; 631 instRes.set(t); 632 instResult.push(instRes); 633 } 634 } 635 636 /** Records an integer register being set to a value. */ | 86 87 // The DynInstPtr type. 88 typedef typename Impl::DynInstPtr DynInstPtr; 89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 90 91 // The list of instructions iterator type. 92 typedef typename std::list<DynInstPtr>::iterator ListIt; 93 --- 532 unchanged lines hidden (view full) --- 626 if (instFlags[RecordResult]) { 627 Result instRes; 628 instRes.set(t); 629 instResult.push(instRes); 630 } 631 } 632 633 /** Records an integer register being set to a value. */ |
637 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) | 634 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) |
638 { 639 setResult<uint64_t>(val); 640 } 641 642 /** Records a CC register being set to a value. */ | 635 { 636 setResult<uint64_t>(val); 637 } 638 639 /** Records a CC register being set to a value. */ |
643 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val) | 640 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) |
644 { 645 setResult<uint64_t>(val); 646 } 647 648 /** Records an fp register being set to a value. */ | 641 { 642 setResult<uint64_t>(val); 643 } 644 645 /** Records an fp register being set to a value. */ |
649 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 650 int width) 651 { 652 if (width == 32 || width == 64) { 653 setResult<double>(val); 654 } else { 655 panic("Unsupported width!"); 656 } 657 } 658 659 /** Records an fp register being set to a value. */ | |
660 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 661 { 662 setResult<double>(val); 663 } 664 665 /** Records an fp register being set to an integer value. */ | 646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 647 { 648 setResult<double>(val); 649 } 650 651 /** Records an fp register being set to an integer value. */ |
666 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 667 int width) | 652 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) |
668 { 669 setResult<uint64_t>(val); 670 } 671 | 653 { 654 setResult<uint64_t>(val); 655 } 656 |
672 /** Records an fp register being set to an integer value. */ 673 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 674 { 675 setResult<uint64_t>(val); 676 } 677 | |
678 /** Records that one of the source registers is ready. */ 679 void markSrcRegReady(); 680 681 /** Marks a specific register as ready. */ 682 void markSrcRegReady(RegIndex src_idx); 683 684 /** Returns if a source register is ready. */ 685 bool isReadySrcRegIdx(int idx) const --- 111 unchanged lines hidden (view full) --- 797 798 /** Sets this instruction as squashed in the ROB. */ 799 void setSquashedInROB() { status.set(SquashedInROB); } 800 801 /** Returns whether or not this instruction is squashed in the ROB. */ 802 bool isSquashedInROB() const { return status[SquashedInROB]; } 803 804 /** Read the PC state of this instruction. */ | 657 /** Records that one of the source registers is ready. */ 658 void markSrcRegReady(); 659 660 /** Marks a specific register as ready. */ 661 void markSrcRegReady(RegIndex src_idx); 662 663 /** Returns if a source register is ready. */ 664 bool isReadySrcRegIdx(int idx) const --- 111 unchanged lines hidden (view full) --- 776 777 /** Sets this instruction as squashed in the ROB. */ 778 void setSquashedInROB() { status.set(SquashedInROB); } 779 780 /** Returns whether or not this instruction is squashed in the ROB. */ 781 bool isSquashedInROB() const { return status[SquashedInROB]; } 782 783 /** Read the PC state of this instruction. */ |
805 const TheISA::PCState pcState() const { return pc; } | 784 TheISA::PCState pcState() const { return pc; } |
806 807 /** Set the PC state of this instruction. */ | 785 786 /** Set the PC state of this instruction. */ |
808 const void pcState(const TheISA::PCState &val) { pc = val; } | 787 void pcState(const TheISA::PCState &val) { pc = val; } |
809 810 /** Read the PC of this instruction. */ 811 const Addr instAddr() const { return pc.instAddr(); } 812 813 /** Read the PC of the next instruction. */ 814 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 815 816 /**Read the micro PC of this instruction. */ --- 22 unchanged lines hidden (view full) --- 839 /** Sets the pointer to the thread state. */ 840 void setThreadState(ImplState *state) { thread = state; } 841 842 /** Returns the thread context. */ 843 ThreadContext *tcBase() { return thread->getTC(); } 844 845 public: 846 /** Sets the effective address. */ | 788 789 /** Read the PC of this instruction. */ 790 const Addr instAddr() const { return pc.instAddr(); } 791 792 /** Read the PC of the next instruction. */ 793 const Addr nextInstAddr() const { return pc.nextInstAddr(); } 794 795 /**Read the micro PC of this instruction. */ --- 22 unchanged lines hidden (view full) --- 818 /** Sets the pointer to the thread state. */ 819 void setThreadState(ImplState *state) { thread = state; } 820 821 /** Returns the thread context. */ 822 ThreadContext *tcBase() { return thread->getTC(); } 823 824 public: 825 /** Sets the effective address. */ |
847 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } | 826 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } |
848 849 /** Returns the effective address. */ | 827 828 /** Returns the effective address. */ |
850 const Addr &getEA() const { return instEffAddr; } | 829 Addr getEA() const { return instEffAddr; } |
851 852 /** Returns whether or not the eff. addr. calculation has been completed. */ 853 bool doneEACalc() { return instFlags[EACalcDone]; } 854 855 /** Returns whether or not the eff. addr. source registers are ready. */ 856 bool eaSrcsReady(); 857 858 /** Is this instruction's memory access uncacheable. */ --- 5 unchanged lines hidden (view full) --- 864 /** Returns iterator to this instruction in the list of all insts. */ 865 ListIt &getInstListIt() { return instListIt; } 866 867 /** Sets iterator for this instruction in the list of all insts. */ 868 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 869 870 public: 871 /** Returns the number of consecutive store conditional failures. */ | 830 831 /** Returns whether or not the eff. addr. calculation has been completed. */ 832 bool doneEACalc() { return instFlags[EACalcDone]; } 833 834 /** Returns whether or not the eff. addr. source registers are ready. */ 835 bool eaSrcsReady(); 836 837 /** Is this instruction's memory access uncacheable. */ --- 5 unchanged lines hidden (view full) --- 843 /** Returns iterator to this instruction in the list of all insts. */ 844 ListIt &getInstListIt() { return instListIt; } 845 846 /** Sets iterator for this instruction in the list of all insts. */ 847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 848 849 public: 850 /** Returns the number of consecutive store conditional failures. */ |
872 unsigned readStCondFailures() | 851 unsigned int readStCondFailures() const |
873 { return thread->storeCondFailures; } 874 875 /** Sets the number of consecutive store conditional failures. */ | 852 { return thread->storeCondFailures; } 853 854 /** Sets the number of consecutive store conditional failures. */ |
876 void setStCondFailures(unsigned sc_failures) | 855 void setStCondFailures(unsigned int sc_failures) |
877 { thread->storeCondFailures = sc_failures; } 878}; 879 880template<class Impl> 881Fault 882BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 883 unsigned size, unsigned flags) 884{ --- 205 unchanged lines hidden --- | 856 { thread->storeCondFailures = sc_failures; } 857}; 858 859template<class Impl> 860Fault 861BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, 862 unsigned size, unsigned flags) 863{ --- 205 unchanged lines hidden --- |