1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Timothy M. Jones
31 */
32
33#ifndef __CPU_BASE_DYN_INST_HH__
34#define __CPU_BASE_DYN_INST_HH__
35
36#include <bitset>
37#include <list>
38#include <string>
39
40#include "arch/faults.hh"
41#include "arch/utility.hh"
42#include "base/fast_alloc.hh"
43#include "base/trace.hh"
44#include "config/full_system.hh"
45#include "config/the_isa.hh"
46#include "cpu/o3/comm.hh"
47#include "cpu/exetrace.hh"
48#include "cpu/inst_seq.hh"
49#include "cpu/op_class.hh"
50#include "cpu/static_inst.hh"
51#include "cpu/translation.hh"
52#include "mem/packet.hh"
53#include "sim/byteswap.hh"
54#include "sim/system.hh"
55#include "sim/tlb.hh"
56
57/**
58 * @file
59 * Defines a dynamic instruction context.
60 */
61
62// Forward declaration.
63class StaticInstPtr;
64
65template <class Impl>
66class BaseDynInst : public FastAlloc, public RefCounted
67{
68 public:
69 // Typedef for the CPU.
70 typedef typename Impl::CPUType ImplCPU;
71 typedef typename ImplCPU::ImplState ImplState;
72
73 // Logical register index type.
74 typedef TheISA::RegIndex RegIndex;
75 // Integer register type.
76 typedef TheISA::IntReg IntReg;
77 // Floating point register type.
78 typedef TheISA::FloatReg FloatReg;
79
80 // The DynInstPtr type.
81 typedef typename Impl::DynInstPtr DynInstPtr;
82
83 // The list of instructions iterator type.
84 typedef typename std::list<DynInstPtr>::iterator ListIt;
85
86 enum {
87 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
88 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
89 };
90
91 /** The StaticInst used by this BaseDynInst. */
92 StaticInstPtr staticInst;
93
94 ////////////////////////////////////////////
95 //
96 // INSTRUCTION EXECUTION
97 //
98 ////////////////////////////////////////////
99 /** InstRecord that tracks this instructions. */
100 Trace::InstRecord *traceData;
101
102 void demapPage(Addr vaddr, uint64_t asn)
103 {
104 cpu->demapPage(vaddr, asn);
105 }
106 void demapInstPage(Addr vaddr, uint64_t asn)
107 {
108 cpu->demapPage(vaddr, asn);
109 }
110 void demapDataPage(Addr vaddr, uint64_t asn)
111 {
112 cpu->demapPage(vaddr, asn);
113 }
114
115 /**
116 * Does a read to a given address.
117 * @param addr The address to read.
118 * @param data The read's data is written into this parameter.
119 * @param flags The request's flags.
120 * @return Returns any fault due to the read.
121 */
122 template <class T>
123 Fault read(Addr addr, T &data, unsigned flags);
124
125 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
126
127 /**
128 * Does a write to a given address.
129 * @param data The data to be written.
130 * @param addr The address to write to.
131 * @param flags The request's flags.
132 * @param res The result of the write (for load locked/store conditionals).
133 * @return Returns any fault due to the write.
134 */
135 template <class T>
136 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
137
138 Fault writeBytes(uint8_t *data, unsigned size,
139 Addr addr, unsigned flags, uint64_t *res);
140
141 /** Splits a request in two if it crosses a dcache block. */
142 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
143 RequestPtr &sreqHigh);
144
145 /** Initiate a DTB address translation. */
146 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
147 RequestPtr sreqHigh, uint64_t *res,
148 BaseTLB::Mode mode);
149
150 /** Finish a DTB address translation. */
151 void finishTranslation(WholeTranslationState *state);
152
153 void prefetch(Addr addr, unsigned flags);
154 void writeHint(Addr addr, int size, unsigned flags);
155 Fault copySrcTranslate(Addr src);
156 Fault copy(Addr dest);
157
158 /** @todo: Consider making this private. */
159 public:
160 /** The sequence number of the instruction. */
161 InstSeqNum seqNum;
162
163 enum Status {
164 IqEntry, /// Instruction is in the IQ
165 RobEntry, /// Instruction is in the ROB
166 LsqEntry, /// Instruction is in the LSQ
167 Completed, /// Instruction has completed
168 ResultReady, /// Instruction has its result
169 CanIssue, /// Instruction can issue and execute
170 Issued, /// Instruction has issued
171 Executed, /// Instruction has executed
172 CanCommit, /// Instruction can commit
173 AtCommit, /// Instruction has reached commit
174 Committed, /// Instruction has committed
175 Squashed, /// Instruction is squashed
176 SquashedInIQ, /// Instruction is squashed in the IQ
177 SquashedInLSQ, /// Instruction is squashed in the LSQ
178 SquashedInROB, /// Instruction is squashed in the ROB
179 RecoverInst, /// Is a recover instruction
180 BlockingInst, /// Is a blocking instruction
181 ThreadsyncWait, /// Is a thread synchronization instruction
182 SerializeBefore, /// Needs to serialize on
183 /// instructions ahead of it
184 SerializeAfter, /// Needs to serialize instructions behind it
185 SerializeHandled, /// Serialization has been handled
186 NumStatus
187 };
188
189 /** The status of this BaseDynInst. Several bits can be set. */
190 std::bitset<NumStatus> status;
191
192 /** The thread this instruction is from. */
193 ThreadID threadNumber;
194
195 /** data address space ID, for loads & stores. */
196 short asid;
197
198 /** How many source registers are ready. */
199 unsigned readyRegs;
200
201 /** Pointer to the Impl's CPU object. */
202 ImplCPU *cpu;
203
204 /** Pointer to the thread state. */
205 ImplState *thread;
206
207 /** The kind of fault this instruction has generated. */
208 Fault fault;
209
210 /** Pointer to the data for the memory access. */
211 uint8_t *memData;
212
213 /** The effective virtual address (lds & stores only). */
214 Addr effAddr;
215
216 /** Is the effective virtual address valid. */
217 bool effAddrValid;
218
219 /** The effective physical address. */
220 Addr physEffAddr;
221
222 /** Effective virtual address for a copy source. */
223 Addr copySrcEffAddr;
224
225 /** Effective physical address for a copy source. */
226 Addr copySrcPhysEffAddr;
227
228 /** The memory request flags (from translation). */
229 unsigned memReqFlags;
230
231 union Result {
232 uint64_t integer;
233// float fp;
234 double dbl;
235 };
236
237 /** The result of the instruction; assumes for now that there's only one
238 * destination register.
239 */
240 Result instResult;
241
242 /** Records changes to result? */
243 bool recordResult;
244
244 /** PC of this instruction. */
245 Addr PC;
246
247 /** Micro PC of this instruction. */
248 Addr microPC;
249
245 /** Did this instruction execute, or is it predicated false */
246 bool predicate;
247
248 protected:
254 /** Next non-speculative PC. It is not filled in at fetch, but rather
255 * once the target of the branch is truly known (either decode or
256 * execute).
257 */
258 Addr nextPC;
249 /** PC state for this instruction. */
250 TheISA::PCState pc;
251
260 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
261 Addr nextNPC;
252 /** Predicted PC state after this instruction. */
253 TheISA::PCState predPC;
254
263 /** Next non-speculative micro PC. */
264 Addr nextMicroPC;
265
266 /** Predicted next PC. */
267 Addr predPC;
268
269 /** Predicted next NPC. */
270 Addr predNPC;
271
272 /** Predicted next microPC */
273 Addr predMicroPC;
274
255 /** If this is a branch that was predicted taken */
256 bool predTaken;
257
258 public:
259
260#ifdef DEBUG
261 void dumpSNList();
262#endif
263
264 /** Whether or not the source register is ready.
265 * @todo: Not sure this should be here vs the derived class.
266 */
267 bool _readySrcRegIdx[MaxInstSrcRegs];
268
269 protected:
270 /** Flattened register index of the destination registers of this
271 * instruction.
272 */
273 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
274
275 /** Flattened register index of the source registers of this
276 * instruction.
277 */
278 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
279
280 /** Physical register index of the destination registers of this
281 * instruction.
282 */
283 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
284
285 /** Physical register index of the source registers of this
286 * instruction.
287 */
288 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
289
290 /** Physical register index of the previous producers of the
291 * architected destinations.
292 */
293 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
294
295 public:
296
297 /** Returns the physical register index of the i'th destination
298 * register.
299 */
300 PhysRegIndex renamedDestRegIdx(int idx) const
301 {
302 return _destRegIdx[idx];
303 }
304
305 /** Returns the physical register index of the i'th source register. */
306 PhysRegIndex renamedSrcRegIdx(int idx) const
307 {
308 return _srcRegIdx[idx];
309 }
310
311 /** Returns the flattened register index of the i'th destination
312 * register.
313 */
314 TheISA::RegIndex flattenedDestRegIdx(int idx) const
315 {
316 return _flatDestRegIdx[idx];
317 }
318
319 /** Returns the flattened register index of the i'th source register */
320 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
321 {
322 return _flatSrcRegIdx[idx];
323 }
324
325 /** Returns the physical register index of the previous physical register
326 * that remapped to the same logical register index.
327 */
328 PhysRegIndex prevDestRegIdx(int idx) const
329 {
330 return _prevDestRegIdx[idx];
331 }
332
333 /** Renames a destination register to a physical register. Also records
334 * the previous physical register that the logical register mapped to.
335 */
336 void renameDestReg(int idx,
337 PhysRegIndex renamed_dest,
338 PhysRegIndex previous_rename)
339 {
340 _destRegIdx[idx] = renamed_dest;
341 _prevDestRegIdx[idx] = previous_rename;
342 }
343
344 /** Renames a source logical register to the physical register which
345 * has/will produce that logical register's result.
346 * @todo: add in whether or not the source register is ready.
347 */
348 void renameSrcReg(int idx, PhysRegIndex renamed_src)
349 {
350 _srcRegIdx[idx] = renamed_src;
351 }
352
353 /** Flattens a source architectural register index into a logical index.
354 */
355 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
356 {
357 _flatSrcRegIdx[idx] = flattened_src;
358 }
359
360 /** Flattens a destination architectural register index into a logical
361 * index.
362 */
363 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
364 {
365 _flatDestRegIdx[idx] = flattened_dest;
366 }
367 /** BaseDynInst constructor given a binary instruction.
368 * @param staticInst A StaticInstPtr to the underlying instruction.
389 * @param PC The PC of the instruction.
390 * @param pred_PC The predicted next PC.
391 * @param pred_NPC The predicted next NPC.
369 * @param pc The PC state for the instruction.
370 * @param predPC The predicted next PC state for the instruction.
371 * @param seq_num The sequence number of the instruction.
372 * @param cpu Pointer to the instruction's CPU.
373 */
395 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
396 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
397 InstSeqNum seq_num, ImplCPU *cpu);
374 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
375 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
376
377 /** BaseDynInst constructor given a binary instruction.
378 * @param inst The binary instruction.
401 * @param PC The PC of the instruction.
402 * @param pred_PC The predicted next PC.
403 * @param pred_NPC The predicted next NPC.
379 * @param _pc The PC state for the instruction.
380 * @param _predPC The predicted next PC state for the instruction.
381 * @param seq_num The sequence number of the instruction.
382 * @param cpu Pointer to the instruction's CPU.
383 */
407 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
408 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
409 InstSeqNum seq_num, ImplCPU *cpu);
384 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
385 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
386
387 /** BaseDynInst constructor given a StaticInst pointer.
388 * @param _staticInst The StaticInst for this BaseDynInst.
389 */
390 BaseDynInst(StaticInstPtr &_staticInst);
391
392 /** BaseDynInst destructor. */
393 ~BaseDynInst();
394
395 private:
396 /** Function to initialize variables in the constructors. */
397 void initVars();
398
399 public:
400 /** Dumps out contents of this BaseDynInst. */
401 void dump();
402
403 /** Dumps out contents of this BaseDynInst into given string. */
404 void dump(std::string &outstring);
405
406 /** Read this CPU's ID. */
407 int cpuId() { return cpu->cpuId(); }
408
409 /** Read this context's system-wide ID **/
410 int contextId() { return thread->contextId(); }
411
412 /** Returns the fault type. */
413 Fault getFault() { return fault; }
414
415 /** Checks whether or not this instruction has had its branch target
416 * calculated yet. For now it is not utilized and is hacked to be
417 * always false.
418 * @todo: Actually use this instruction.
419 */
420 bool doneTargCalc() { return false; }
421
446 /** Returns the next PC. This could be the speculative next PC if it is
447 * called prior to the actual branch target being calculated.
448 */
449 Addr readNextPC() { return nextPC; }
450
451 /** Returns the next NPC. This could be the speculative next NPC if it is
452 * called prior to the actual branch target being calculated.
453 */
454 Addr readNextNPC()
455 {
456#if ISA_HAS_DELAY_SLOT
457 return nextNPC;
458#else
459 return nextPC + sizeof(TheISA::MachInst);
460#endif
461 }
462
463 Addr readNextMicroPC()
464 {
465 return nextMicroPC;
466 }
467
422 /** Set the predicted target of this current instruction. */
469 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
470 Addr predicted_MicroPC)
423 void setPredTarg(const TheISA::PCState &_predPC)
424 {
472 predPC = predicted_PC;
473 predNPC = predicted_NPC;
474 predMicroPC = predicted_MicroPC;
425 predPC = _predPC;
426 }
427
428 const TheISA::PCState &readPredTarg() { return predPC; }
429
430 /** Returns the predicted PC immediately after the branch. */
478 Addr readPredPC() { return predPC; }
431 Addr predInstAddr() { return predPC.instAddr(); }
432
433 /** Returns the predicted PC two instructions after the branch */
481 Addr readPredNPC() { return predNPC; }
434 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
435
436 /** Returns the predicted micro PC after the branch */
484 Addr readPredMicroPC() { return predMicroPC; }
437 Addr predMicroPC() { return predPC.microPC(); }
438
439 /** Returns whether the instruction was predicted taken or not. */
440 bool readPredTaken()
441 {
442 return predTaken;
443 }
444
445 void setPredTaken(bool predicted_taken)
446 {
447 predTaken = predicted_taken;
448 }
449
450 /** Returns whether the instruction mispredicted. */
451 bool mispredicted()
452 {
500 return readPredPC() != readNextPC() ||
501 readPredNPC() != readNextNPC() ||
502 readPredMicroPC() != readNextMicroPC();
453 TheISA::PCState tempPC = pc;
454 TheISA::advancePC(tempPC, staticInst);
455 return !(tempPC == predPC);
456 }
457
458 //
459 // Instruction types. Forward checks to StaticInst object.
460 //
461 bool isNop() const { return staticInst->isNop(); }
462 bool isMemRef() const { return staticInst->isMemRef(); }
463 bool isLoad() const { return staticInst->isLoad(); }
464 bool isStore() const { return staticInst->isStore(); }
465 bool isStoreConditional() const
466 { return staticInst->isStoreConditional(); }
467 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
468 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
469 bool isCopy() const { return staticInst->isCopy(); }
470 bool isInteger() const { return staticInst->isInteger(); }
471 bool isFloating() const { return staticInst->isFloating(); }
472 bool isControl() const { return staticInst->isControl(); }
473 bool isCall() const { return staticInst->isCall(); }
474 bool isReturn() const { return staticInst->isReturn(); }
475 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
476 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
477 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
478 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
479 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
480 bool isThreadSync() const { return staticInst->isThreadSync(); }
481 bool isSerializing() const { return staticInst->isSerializing(); }
482 bool isSerializeBefore() const
483 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
484 bool isSerializeAfter() const
485 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
486 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
487 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
488 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
489 bool isQuiesce() const { return staticInst->isQuiesce(); }
490 bool isIprAccess() const { return staticInst->isIprAccess(); }
491 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
492 bool isSyscall() const { return staticInst->isSyscall(); }
493 bool isMacroop() const { return staticInst->isMacroop(); }
494 bool isMicroop() const { return staticInst->isMicroop(); }
495 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
496 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
497 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
498 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
499
500 /** Temporarily sets this instruction as a serialize before instruction. */
501 void setSerializeBefore() { status.set(SerializeBefore); }
502
503 /** Clears the serializeBefore part of this instruction. */
504 void clearSerializeBefore() { status.reset(SerializeBefore); }
505
506 /** Checks if this serializeBefore is only temporarily set. */
507 bool isTempSerializeBefore() { return status[SerializeBefore]; }
508
509 /** Temporarily sets this instruction as a serialize after instruction. */
510 void setSerializeAfter() { status.set(SerializeAfter); }
511
512 /** Clears the serializeAfter part of this instruction.*/
513 void clearSerializeAfter() { status.reset(SerializeAfter); }
514
515 /** Checks if this serializeAfter is only temporarily set. */
516 bool isTempSerializeAfter() { return status[SerializeAfter]; }
517
518 /** Sets the serialization part of this instruction as handled. */
519 void setSerializeHandled() { status.set(SerializeHandled); }
520
521 /** Checks if the serialization part of this instruction has been
522 * handled. This does not apply to the temporary serializing
523 * state; it only applies to this instruction's own permanent
524 * serializing state.
525 */
526 bool isSerializeHandled() { return status[SerializeHandled]; }
527
528 /** Returns the opclass of this instruction. */
529 OpClass opClass() const { return staticInst->opClass(); }
530
531 /** Returns the branch target address. */
579 Addr branchTarget() const { return staticInst->branchTarget(PC); }
532 TheISA::PCState branchTarget() const
533 { return staticInst->branchTarget(pc); }
534
535 /** Returns the number of source registers. */
536 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
537
538 /** Returns the number of destination registers. */
539 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
540
541 // the following are used to track physical register usage
542 // for machines with separate int & FP reg files
543 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
544 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
545
546 /** Returns the logical register index of the i'th destination register. */
547 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
548
549 /** Returns the logical register index of the i'th source register. */
550 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
551
552 /** Returns the result of an integer instruction. */
553 uint64_t readIntResult() { return instResult.integer; }
554
555 /** Returns the result of a floating point instruction. */
556 float readFloatResult() { return (float)instResult.dbl; }
557
558 /** Returns the result of a floating point (double) instruction. */
559 double readDoubleResult() { return instResult.dbl; }
560
561 /** Records an integer register being set to a value. */
562 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
563 {
564 if (recordResult)
565 instResult.integer = val;
566 }
567
568 /** Records an fp register being set to a value. */
569 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
570 int width)
571 {
572 if (recordResult) {
573 if (width == 32)
574 instResult.dbl = (double)val;
575 else if (width == 64)
576 instResult.dbl = val;
577 else
578 panic("Unsupported width!");
579 }
580 }
581
582 /** Records an fp register being set to a value. */
583 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
584 {
585 if (recordResult)
586 instResult.dbl = (double)val;
587 }
588
589 /** Records an fp register being set to an integer value. */
590 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
591 int width)
592 {
593 if (recordResult)
594 instResult.integer = val;
595 }
596
597 /** Records an fp register being set to an integer value. */
598 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
599 {
600 if (recordResult)
601 instResult.integer = val;
602 }
603
604 /** Records that one of the source registers is ready. */
605 void markSrcRegReady();
606
607 /** Marks a specific register as ready. */
608 void markSrcRegReady(RegIndex src_idx);
609
610 /** Returns if a source register is ready. */
611 bool isReadySrcRegIdx(int idx) const
612 {
613 return this->_readySrcRegIdx[idx];
614 }
615
616 /** Sets this instruction as completed. */
617 void setCompleted() { status.set(Completed); }
618
619 /** Returns whether or not this instruction is completed. */
620 bool isCompleted() const { return status[Completed]; }
621
622 /** Marks the result as ready. */
623 void setResultReady() { status.set(ResultReady); }
624
625 /** Returns whether or not the result is ready. */
626 bool isResultReady() const { return status[ResultReady]; }
627
628 /** Sets this instruction as ready to issue. */
629 void setCanIssue() { status.set(CanIssue); }
630
631 /** Returns whether or not this instruction is ready to issue. */
632 bool readyToIssue() const { return status[CanIssue]; }
633
634 /** Clears this instruction being able to issue. */
635 void clearCanIssue() { status.reset(CanIssue); }
636
637 /** Sets this instruction as issued from the IQ. */
638 void setIssued() { status.set(Issued); }
639
640 /** Returns whether or not this instruction has issued. */
641 bool isIssued() const { return status[Issued]; }
642
643 /** Clears this instruction as being issued. */
644 void clearIssued() { status.reset(Issued); }
645
646 /** Sets this instruction as executed. */
647 void setExecuted() { status.set(Executed); }
648
649 /** Returns whether or not this instruction has executed. */
650 bool isExecuted() const { return status[Executed]; }
651
652 /** Sets this instruction as ready to commit. */
653 void setCanCommit() { status.set(CanCommit); }
654
655 /** Clears this instruction as being ready to commit. */
656 void clearCanCommit() { status.reset(CanCommit); }
657
658 /** Returns whether or not this instruction is ready to commit. */
659 bool readyToCommit() const { return status[CanCommit]; }
660
661 void setAtCommit() { status.set(AtCommit); }
662
663 bool isAtCommit() { return status[AtCommit]; }
664
665 /** Sets this instruction as committed. */
666 void setCommitted() { status.set(Committed); }
667
668 /** Returns whether or not this instruction is committed. */
669 bool isCommitted() const { return status[Committed]; }
670
671 /** Sets this instruction as squashed. */
672 void setSquashed() { status.set(Squashed); }
673
674 /** Returns whether or not this instruction is squashed. */
675 bool isSquashed() const { return status[Squashed]; }
676
677 //Instruction Queue Entry
678 //-----------------------
679 /** Sets this instruction as a entry the IQ. */
680 void setInIQ() { status.set(IqEntry); }
681
682 /** Sets this instruction as a entry the IQ. */
683 void clearInIQ() { status.reset(IqEntry); }
684
685 /** Returns whether or not this instruction has issued. */
686 bool isInIQ() const { return status[IqEntry]; }
687
688 /** Sets this instruction as squashed in the IQ. */
689 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
690
691 /** Returns whether or not this instruction is squashed in the IQ. */
692 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
693
694
695 //Load / Store Queue Functions
696 //-----------------------
697 /** Sets this instruction as a entry the LSQ. */
698 void setInLSQ() { status.set(LsqEntry); }
699
700 /** Sets this instruction as a entry the LSQ. */
701 void removeInLSQ() { status.reset(LsqEntry); }
702
703 /** Returns whether or not this instruction is in the LSQ. */
704 bool isInLSQ() const { return status[LsqEntry]; }
705
706 /** Sets this instruction as squashed in the LSQ. */
707 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
708
709 /** Returns whether or not this instruction is squashed in the LSQ. */
710 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
711
712
713 //Reorder Buffer Functions
714 //-----------------------
715 /** Sets this instruction as a entry the ROB. */
716 void setInROB() { status.set(RobEntry); }
717
718 /** Sets this instruction as a entry the ROB. */
719 void clearInROB() { status.reset(RobEntry); }
720
721 /** Returns whether or not this instruction is in the ROB. */
722 bool isInROB() const { return status[RobEntry]; }
723
724 /** Sets this instruction as squashed in the ROB. */
725 void setSquashedInROB() { status.set(SquashedInROB); }
726
727 /** Returns whether or not this instruction is squashed in the ROB. */
728 bool isSquashedInROB() const { return status[SquashedInROB]; }
729
776 /** Read the PC of this instruction. */
777 const Addr readPC() const { return PC; }
730 /** Read the PC state of this instruction. */
731 const TheISA::PCState pcState() const { return pc; }
732
779 /**Read the micro PC of this instruction. */
780 const Addr readMicroPC() const { return microPC; }
733 /** Set the PC state of this instruction. */
734 const void pcState(const TheISA::PCState &val) { pc = val; }
735
782 /** Set the next PC of this instruction (its actual target). */
783 void setNextPC(Addr val)
784 {
785 nextPC = val;
786 }
736 /** Read the PC of this instruction. */
737 const Addr instAddr() const { return pc.instAddr(); }
738
788 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
789 void setNextNPC(Addr val)
790 {
791#if ISA_HAS_DELAY_SLOT
792 nextNPC = val;
793#endif
794 }
739 /** Read the PC of the next instruction. */
740 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
741
796 void setNextMicroPC(Addr val)
797 {
798 nextMicroPC = val;
799 }
742 /**Read the micro PC of this instruction. */
743 const Addr microPC() const { return pc.microPC(); }
744
745 bool readPredicate()
746 {
747 return predicate;
748 }
749
750 void setPredicate(bool val)
751 {
752 predicate = val;
753
754 if (traceData) {
755 traceData->setPredicate(val);
756 }
757 }
758
759 /** Sets the ASID. */
760 void setASID(short addr_space_id) { asid = addr_space_id; }
761
762 /** Sets the thread id. */
763 void setTid(ThreadID tid) { threadNumber = tid; }
764
765 /** Sets the pointer to the thread state. */
766 void setThreadState(ImplState *state) { thread = state; }
767
768 /** Returns the thread context. */
769 ThreadContext *tcBase() { return thread->getTC(); }
770
771 private:
772 /** Instruction effective address.
773 * @todo: Consider if this is necessary or not.
774 */
775 Addr instEffAddr;
776
777 /** Whether or not the effective address calculation is completed.
778 * @todo: Consider if this is necessary or not.
779 */
780 bool eaCalcDone;
781
782 /** Is this instruction's memory access uncacheable. */
783 bool isUncacheable;
784
785 /** Has this instruction generated a memory request. */
786 bool reqMade;
787
788 public:
789 /** Sets the effective address. */
790 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
791
792 /** Returns the effective address. */
793 const Addr &getEA() const { return instEffAddr; }
794
795 /** Returns whether or not the eff. addr. calculation has been completed. */
796 bool doneEACalc() { return eaCalcDone; }
797
798 /** Returns whether or not the eff. addr. source registers are ready. */
799 bool eaSrcsReady();
800
801 /** Whether or not the memory operation is done. */
802 bool memOpDone;
803
804 /** Is this instruction's memory access uncacheable. */
805 bool uncacheable() { return isUncacheable; }
806
807 /** Has this instruction generated a memory request. */
808 bool hasRequest() { return reqMade; }
809
810 public:
811 /** Load queue index. */
812 int16_t lqIdx;
813
814 /** Store queue index. */
815 int16_t sqIdx;
816
817 /** Iterator pointing to this BaseDynInst in the list of all insts. */
818 ListIt instListIt;
819
820 /** Returns iterator to this instruction in the list of all insts. */
821 ListIt &getInstListIt() { return instListIt; }
822
823 /** Sets iterator for this instruction in the list of all insts. */
824 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
825
826 public:
827 /** Returns the number of consecutive store conditional failures. */
828 unsigned readStCondFailures()
829 { return thread->storeCondFailures; }
830
831 /** Sets the number of consecutive store conditional failures. */
832 void setStCondFailures(unsigned sc_failures)
833 { thread->storeCondFailures = sc_failures; }
834};
835
836template<class Impl>
837Fault
838BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
839 unsigned size, unsigned flags)
840{
841 reqMade = true;
898 Request *req = new Request(asid, addr, size, flags, this->PC,
842 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
843 thread->contextId(), threadNumber);
844
845 Request *sreqLow = NULL;
846 Request *sreqHigh = NULL;
847
848 // Only split the request if the ISA supports unaligned accesses.
849 if (TheISA::HasUnalignedMemAcc) {
850 splitRequest(req, sreqLow, sreqHigh);
851 }
852 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
853
854 if (fault == NoFault) {
855 effAddr = req->getVaddr();
856 effAddrValid = true;
857 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
858 } else {
859 // Commit will have to clean up whatever happened. Set this
860 // instruction as executed.
861 this->setExecuted();
862 }
863
864 if (fault != NoFault) {
865 // Return a fixed value to keep simulation deterministic even
866 // along misspeculated paths.
867 bzero(data, size);
868 }
869
870 if (traceData) {
871 traceData->setAddr(addr);
872 }
873
874 return fault;
875}
876
877template<class Impl>
878template<class T>
879inline Fault
880BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
881{
882 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
883
884 data = TheISA::gtoh(data);
885
886 if (traceData) {
887 traceData->setData(data);
888 }
889
890 return fault;
891}
892
893template<class Impl>
894Fault
895BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
896 Addr addr, unsigned flags, uint64_t *res)
897{
898 if (traceData) {
899 traceData->setAddr(addr);
900 }
901
902 reqMade = true;
959 Request *req = new Request(asid, addr, size, flags, this->PC,
903 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
904 thread->contextId(), threadNumber);
905
906 Request *sreqLow = NULL;
907 Request *sreqHigh = NULL;
908
909 // Only split the request if the ISA supports unaligned accesses.
910 if (TheISA::HasUnalignedMemAcc) {
911 splitRequest(req, sreqLow, sreqHigh);
912 }
913 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
914
915 if (fault == NoFault) {
916 effAddr = req->getVaddr();
917 effAddrValid = true;
918 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
919 }
920
921 return fault;
922}
923
924template<class Impl>
925template<class T>
926inline Fault
927BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
928{
929 if (traceData) {
930 traceData->setData(data);
931 }
932 data = TheISA::htog(data);
933 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
934}
935
936template<class Impl>
937inline void
938BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
939 RequestPtr &sreqHigh)
940{
941 // Check to see if the request crosses the next level block boundary.
942 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
943 Addr addr = req->getVaddr();
944 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
945 assert(split_addr <= addr || split_addr - addr < block_size);
946
947 // Spans two blocks.
948 if (split_addr > addr) {
949 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
950 }
951}
952
953template<class Impl>
954inline void
955BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
956 RequestPtr sreqHigh, uint64_t *res,
957 BaseTLB::Mode mode)
958{
959 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
960 WholeTranslationState *state =
961 new WholeTranslationState(req, NULL, res, mode);
962
963 // One translation if the request isn't split.
964 DataTranslation<BaseDynInst<Impl> > *trans =
965 new DataTranslation<BaseDynInst<Impl> >(this, state);
966 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
967 } else {
968 WholeTranslationState *state =
969 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
970
971 // Two translations when the request is split.
972 DataTranslation<BaseDynInst<Impl> > *stransLow =
973 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
974 DataTranslation<BaseDynInst<Impl> > *stransHigh =
975 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
976
977 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
978 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
979 }
980}
981
982template<class Impl>
983inline void
984BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
985{
986 fault = state->getFault();
987
988 if (state->isUncacheable())
989 isUncacheable = true;
990
991 if (fault == NoFault) {
992 physEffAddr = state->getPaddr();
993 memReqFlags = state->getFlags();
994
995 if (state->mainReq->isCondSwap()) {
996 assert(state->res);
997 state->mainReq->setExtraData(*state->res);
998 }
999
1000 } else {
1001 state->deleteReqs();
1002 }
1003 delete state;
1004}
1005
1006#endif // __CPU_BASE_DYN_INST_HH__