1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 * 28 * Authors: Kevin Lim |
29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33
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32#include <list>
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34#include <string>
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35#include <vector> |
36 37#include "base/fast_alloc.hh" 38#include "base/trace.hh" 39#include "config/full_system.hh" 40#include "cpu/exetrace.hh" 41#include "cpu/inst_seq.hh"
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42#include "cpu/o3/comm.hh" |
43#include "cpu/static_inst.hh"
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41#include "encumbered/cpu/full/op_class.hh"
42#include "mem/functional/memory_control.hh"
43#include "sim/system.hh"
44/*
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44#include "encumbered/cpu/full/bpred_update.hh"
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45#include "encumbered/cpu/full/op_class.hh" |
46#include "encumbered/cpu/full/spec_memory.hh" 47#include "encumbered/cpu/full/spec_state.hh" 48#include "encumbered/mem/functional/main.hh"
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49*/
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49 50/** 51 * @file 52 * Defines a dynamic instruction context. 53 */ 54 55// Forward declaration. 56class StaticInstPtr; 57 58template <class Impl> 59class BaseDynInst : public FastAlloc, public RefCounted 60{ 61 public: 62 // Typedef for the CPU. 63 typedef typename Impl::FullCPU FullCPU;
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65 typedef typename FullCPU::ImplState ImplState;
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64
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67 // Binary machine instruction type.
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65 /// Binary machine instruction type. |
66 typedef TheISA::MachInst MachInst;
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69 // Extended machine instruction type
70 typedef TheISA::ExtMachInst ExtMachInst;
71 // Logical register index type.
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67 /// Logical register index type. |
68 typedef TheISA::RegIndex RegIndex;
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73 // Integer register index type.
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69 /// Integer register index type. |
70 typedef TheISA::IntReg IntReg; 71
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76 // The DynInstPtr type.
77 typedef typename Impl::DynInstPtr DynInstPtr;
78
79 // The list of instructions iterator type.
80 typedef typename std::list<DynInstPtr>::iterator ListIt;
81
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72 enum {
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83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
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73 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs 74 MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs |
75 }; 76
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87 /** The StaticInst used by this BaseDynInst. */
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77 /** The static inst used by this dyn inst. */ |
78 StaticInstPtr staticInst; 79 80 //////////////////////////////////////////// 81 // 82 // INSTRUCTION EXECUTION 83 // 84 ////////////////////////////////////////////
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95 /** InstRecord that tracks this instructions. */
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85 Trace::InstRecord *traceData; 86
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98 /**
99 * Does a read to a given address.
100 * @param addr The address to read.
101 * @param data The read's data is written into this parameter.
102 * @param flags The request's flags.
103 * @return Returns any fault due to the read.
104 */
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87 template <class T> 88 Fault read(Addr addr, T &data, unsigned flags); 89
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108 /**
109 * Does a write to a given address.
110 * @param data The data to be written.
111 * @param addr The address to write to.
112 * @param flags The request's flags.
113 * @param res The result of the write (for load locked/store conditionals).
114 * @return Returns any fault due to the write.
115 */
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90 template <class T> 91 Fault write(T data, Addr addr, unsigned flags, 92 uint64_t *res); 93 94 void prefetch(Addr addr, unsigned flags); 95 void writeHint(Addr addr, int size, unsigned flags); 96 Fault copySrcTranslate(Addr src); 97 Fault copy(Addr dest); 98 99 /** @todo: Consider making this private. */ 100 public:
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101 /** Is this instruction valid. */ 102 bool valid; 103 |
104 /** The sequence number of the instruction. */ 105 InstSeqNum seqNum; 106
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130 /** Is the instruction in the IQ */
131 bool iqEntry;
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107 /** How many source registers are ready. */ 108 unsigned readyRegs; |
109
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133 /** Is the instruction in the ROB */
134 bool robEntry;
135
136 /** Is the instruction in the LSQ */
137 bool lsqEntry;
138
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110 /** Is the instruction completed. */ 111 bool completed; 112
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142 /** Is the instruction's result ready. */
143 bool resultReady;
144
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113 /** Can this instruction issue. */ 114 bool canIssue; 115 116 /** Has this instruction issued. */ 117 bool issued; 118 119 /** Has this instruction executed (or made it through execute) yet. */ 120 bool executed; 121 122 /** Can this instruction commit. */ 123 bool canCommit; 124
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157 /** Is this instruction committed. */
158 bool committed;
159
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125 /** Is this instruction squashed. */ 126 bool squashed; 127 128 /** Is this instruction squashed in the instruction queue. */ 129 bool squashedInIQ; 130
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166 /** Is this instruction squashed in the instruction queue. */
167 bool squashedInLSQ;
168
169 /** Is this instruction squashed in the instruction queue. */
170 bool squashedInROB;
171
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131 /** Is this a recover instruction. */ 132 bool recoverInst; 133 134 /** Is this a thread blocking instruction. */ 135 bool blockingInst; /* this inst has called thread_block() */ 136 137 /** Is this a thread syncrhonization instruction. */ 138 bool threadsyncWait; 139 140 /** The thread this instruction is from. */ 141 short threadNumber; 142 143 /** data address space ID, for loads & stores. */ 144 short asid; 145
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187 /** How many source registers are ready. */
188 unsigned readyRegs;
189
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146 /** Pointer to the FullCPU object. */ 147 FullCPU *cpu; 148
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193 /** Pointer to the exec context. */
194 ImplState *thread;
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149 /** Pointer to the exec context. Will not exist in the final version. */ 150 CPUExecContext *cpuXC; |
151 152 /** The kind of fault this instruction has generated. */ 153 Fault fault; 154
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199 /** The memory request. */
200 MemReqPtr req;
201
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155 /** The effective virtual address (lds & stores only). */ 156 Addr effAddr; 157 158 /** The effective physical address. */ 159 Addr physEffAddr; 160 161 /** Effective virtual address for a copy source. */ 162 Addr copySrcEffAddr; 163 164 /** Effective physical address for a copy source. */ 165 Addr copySrcPhysEffAddr; 166 167 /** The memory request flags (from translation). */ 168 unsigned memReqFlags; 169 170 /** The size of the data to be stored. */ 171 int storeSize; 172 173 /** The data to be stored. */ 174 IntReg storeData; 175 176 union Result { 177 uint64_t integer; 178 float fp; 179 double dbl; 180 }; 181 182 /** The result of the instruction; assumes for now that there's only one 183 * destination register. 184 */ 185 Result instResult; 186 187 /** PC of this instruction. */ 188 Addr PC; 189 190 /** Next non-speculative PC. It is not filled in at fetch, but rather 191 * once the target of the branch is truly known (either decode or 192 * execute). 193 */ 194 Addr nextPC; 195 196 /** Predicted next PC. */ 197 Addr predPC; 198 199 /** Count of total number of dynamic instructions. */ 200 static int instcount; 201
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249#ifdef DEBUG
250 void dumpSNList();
251#endif
252
253 /** Whether or not the source register is ready.
254 * @todo: Not sure this should be here vs the derived class.
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202 /** Whether or not the source register is ready. Not sure this should be 203 * here vs. the derived class. |
204 */ 205 bool _readySrcRegIdx[MaxInstSrcRegs]; 206 207 public:
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259 /** BaseDynInst constructor given a binary instruction.
260 * @param inst The binary instruction.
261 * @param PC The PC of the instruction.
262 * @param pred_PC The predicted next PC.
263 * @param seq_num The sequence number of the instruction.
264 * @param cpu Pointer to the instruction's CPU.
265 */
266 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
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208 /** BaseDynInst constructor given a binary instruction. */ 209 BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, |
210 FullCPU *cpu); 211
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269 /** BaseDynInst constructor given a StaticInst pointer.
270 * @param _staticInst The StaticInst for this BaseDynInst.
271 */
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212 /** BaseDynInst constructor given a static inst pointer. */ |
213 BaseDynInst(StaticInstPtr &_staticInst); 214 215 /** BaseDynInst destructor. */ 216 ~BaseDynInst(); 217 218 private: 219 /** Function to initialize variables in the constructors. */ 220 void initVars(); 221 222 public:
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282 /**
283 * @todo: Make this function work; currently it is a dummy function.
284 * @param fault Last fault.
285 * @param cmd Last command.
286 * @param addr Virtual address of access.
287 * @param p Memory accessed.
288 * @param nbytes Access size.
289 */
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223 void
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291 trace_mem(Fault fault,
292 MemCmd cmd,
293 Addr addr,
294 void *p,
295 int nbytes);
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224 trace_mem(Fault fault, // last fault 225 MemCmd cmd, // last command 226 Addr addr, // virtual address of access 227 void *p, // memory accessed 228 int nbytes); // access size |
229 230 /** Dumps out contents of this BaseDynInst. */ 231 void dump(); 232 233 /** Dumps out contents of this BaseDynInst into given string. */ 234 void dump(std::string &outstring); 235 236 /** Returns the fault type. */ 237 Fault getFault() { return fault; } 238 239 /** Checks whether or not this instruction has had its branch target 240 * calculated yet. For now it is not utilized and is hacked to be 241 * always false.
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309 * @todo: Actually use this instruction.
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242 */ 243 bool doneTargCalc() { return false; } 244 245 /** Returns the next PC. This could be the speculative next PC if it is 246 * called prior to the actual branch target being calculated. 247 */ 248 Addr readNextPC() { return nextPC; } 249 250 /** Set the predicted target of this current instruction. */ 251 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; } 252 253 /** Returns the predicted target of the branch. */ 254 Addr readPredTarg() { return predPC; } 255 256 /** Returns whether the instruction was predicted taken or not. */
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325 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
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257 bool predTaken() { 258 return( predPC != (PC + sizeof(MachInst) ) ); 259 } |
260 261 /** Returns whether the instruction mispredicted. */
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328 bool mispredicted() { return predPC != nextPC; }
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262 bool mispredicted() { return (predPC != nextPC); } |
263 264 // 265 // Instruction types. Forward checks to StaticInst object. 266 // 267 bool isNop() const { return staticInst->isNop(); } 268 bool isMemRef() const { return staticInst->isMemRef(); } 269 bool isLoad() const { return staticInst->isLoad(); } 270 bool isStore() const { return staticInst->isStore(); }
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337 bool isStoreConditional() const
338 { return staticInst->isStoreConditional(); }
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271 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 272 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 273 bool isCopy() const { return staticInst->isCopy(); } 274 bool isInteger() const { return staticInst->isInteger(); } 275 bool isFloating() const { return staticInst->isFloating(); } 276 bool isControl() const { return staticInst->isControl(); } 277 bool isCall() const { return staticInst->isCall(); } 278 bool isReturn() const { return staticInst->isReturn(); } 279 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 280 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 281 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 282 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 283 bool isThreadSync() const { return staticInst->isThreadSync(); } 284 bool isSerializing() const { return staticInst->isSerializing(); }
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353 bool isSerializeBefore() const
354 { return staticInst->isSerializeBefore() || serializeBefore; }
355 bool isSerializeAfter() const
356 { return staticInst->isSerializeAfter() || serializeAfter; }
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285 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 286 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 287 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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360 bool isQuiesce() const { return staticInst->isQuiesce(); }
361 bool isIprAccess() const { return staticInst->isIprAccess(); }
362 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
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288
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364 /** Temporarily sets this instruction as a serialize before instruction. */
365 void setSerializeBefore() { serializeBefore = true; }
366
367 /** Clears the serializeBefore part of this instruction. */
368 void clearSerializeBefore() { serializeBefore = false; }
369
370 /** Checks if this serializeBefore is only temporarily set. */
371 bool isTempSerializeBefore() { return serializeBefore; }
372
373 /** Tracks if instruction has been externally set as serializeBefore. */
374 bool serializeBefore;
375
376 /** Temporarily sets this instruction as a serialize after instruction. */
377 void setSerializeAfter() { serializeAfter = true; }
378
379 /** Clears the serializeAfter part of this instruction.*/
380 void clearSerializeAfter() { serializeAfter = false; }
381
382 /** Checks if this serializeAfter is only temporarily set. */
383 bool isTempSerializeAfter() { return serializeAfter; }
384
385 /** Tracks if instruction has been externally set as serializeAfter. */
386 bool serializeAfter;
387
388 /** Checks if the serialization part of this instruction has been
389 * handled. This does not apply to the temporary serializing
390 * state; it only applies to this instruction's own permanent
391 * serializing state.
392 */
393 bool isSerializeHandled() { return serializeHandled; }
394
395 /** Sets the serialization part of this instruction as handled. */
396 void setSerializeHandled() { serializeHandled = true; }
397
398 /** Whether or not the serialization of this instruction has been handled. */
399 bool serializeHandled;
400
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289 /** Returns the opclass of this instruction. */ 290 OpClass opClass() const { return staticInst->opClass(); } 291 292 /** Returns the branch target address. */ 293 Addr branchTarget() const { return staticInst->branchTarget(PC); } 294
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407 /** Returns the number of source registers. */
408 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
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295 /** Number of source registers. */ 296 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } |
297
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410 /** Returns the number of destination registers. */
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298 /** Number of destination registers. */ |
299 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 300 301 // the following are used to track physical register usage 302 // for machines with separate int & FP reg files 303 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 304 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 305 306 /** Returns the logical register index of the i'th destination register. */
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419 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
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307 RegIndex destRegIdx(int i) const 308 { 309 return staticInst->destRegIdx(i); 310 } |
311 312 /** Returns the logical register index of the i'th source register. */
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422 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
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313 RegIndex srcRegIdx(int i) const 314 { 315 return staticInst->srcRegIdx(i); 316 } |
317 318 /** Returns the result of an integer instruction. */ 319 uint64_t readIntResult() { return instResult.integer; } 320 321 /** Returns the result of a floating point instruction. */ 322 float readFloatResult() { return instResult.fp; } 323 324 /** Returns the result of a floating point (double) instruction. */ 325 double readDoubleResult() { return instResult.dbl; } 326
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433 void setIntReg(const StaticInst *si, int idx, uint64_t val)
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327 //Push to .cc file. 328 /** Records that one of the source registers is ready. */ 329 void markSrcRegReady() |
330 {
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435 instResult.integer = val;
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331 ++readyRegs; 332 if(readyRegs == numSrcRegs()) { 333 canIssue = true; 334 } |
335 } 336
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438 void setFloatRegSingle(const StaticInst *si, int idx, float val)
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337 /** Marks a specific register as ready. 338 * @todo: Move this to .cc file. 339 */ 340 void markSrcRegReady(RegIndex src_idx) |
341 {
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440 instResult.fp = val;
441 }
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342 ++readyRegs; |
343
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443 void setFloatRegDouble(const StaticInst *si, int idx, double val)
444 {
445 instResult.dbl = val;
446 }
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344 _readySrcRegIdx[src_idx] = 1; |
345
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448 void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
449 {
450 instResult.integer = val;
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346 if(readyRegs == numSrcRegs()) { 347 canIssue = true; 348 } |
349 } 350
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453 /** Records that one of the source registers is ready. */
454 void markSrcRegReady();
455
456 /** Marks a specific register as ready. */
457 void markSrcRegReady(RegIndex src_idx);
458
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351 /** Returns if a source register is ready. */ 352 bool isReadySrcRegIdx(int idx) const 353 { 354 return this->_readySrcRegIdx[idx]; 355 } 356 357 /** Sets this instruction as completed. */ 358 void setCompleted() { completed = true; } 359
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468 /** Returns whether or not this instruction is completed. */
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360 /** Returns whethe or not this instruction is completed. */ |
361 bool isCompleted() const { return completed; } 362
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471 void setResultReady() { resultReady = true; }
472
473 bool isResultReady() const { return resultReady; }
474
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363 /** Sets this instruction as ready to issue. */ 364 void setCanIssue() { canIssue = true; } 365 366 /** Returns whether or not this instruction is ready to issue. */ 367 bool readyToIssue() const { return canIssue; } 368 369 /** Sets this instruction as issued from the IQ. */ 370 void setIssued() { issued = true; } 371 372 /** Returns whether or not this instruction has issued. */ 373 bool isIssued() const { return issued; } 374 375 /** Sets this instruction as executed. */ 376 void setExecuted() { executed = true; } 377 378 /** Returns whether or not this instruction has executed. */ 379 bool isExecuted() const { return executed; } 380 381 /** Sets this instruction as ready to commit. */ 382 void setCanCommit() { canCommit = true; } 383 384 /** Clears this instruction as being ready to commit. */ 385 void clearCanCommit() { canCommit = false; } 386 387 /** Returns whether or not this instruction is ready to commit. */ 388 bool readyToCommit() const { return canCommit; } 389
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502 /** Sets this instruction as committed. */
503 void setCommitted() { committed = true; }
504
505 /** Returns whether or not this instruction is committed. */
506 bool isCommitted() const { return committed; }
507
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390 /** Sets this instruction as squashed. */ 391 void setSquashed() { squashed = true; } 392 393 /** Returns whether or not this instruction is squashed. */ 394 bool isSquashed() const { return squashed; } 395
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514 //Instruction Queue Entry
515 //-----------------------
516 /** Sets this instruction as a entry the IQ. */
517 void setInIQ() { iqEntry = true; }
518
519 /** Sets this instruction as a entry the IQ. */
520 void removeInIQ() { iqEntry = false; }
521
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396 /** Sets this instruction as squashed in the IQ. */
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523 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
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397 void setSquashedInIQ() { squashedInIQ = true; } |
398 399 /** Returns whether or not this instruction is squashed in the IQ. */ 400 bool isSquashedInIQ() const { return squashedInIQ; } 401
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528 /** Returns whether or not this instruction has issued. */
529 bool isInIQ() const { return iqEntry; }
530
531
532 //Load / Store Queue Functions
533 //-----------------------
534 /** Sets this instruction as a entry the LSQ. */
535 void setInLSQ() { lsqEntry = true; }
536
537 /** Sets this instruction as a entry the LSQ. */
538 void removeInLSQ() { lsqEntry = false; }
539
540 /** Sets this instruction as squashed in the LSQ. */
541 void setSquashedInLSQ() { squashedInLSQ = true;}
542
543 /** Returns whether or not this instruction is squashed in the LSQ. */
544 bool isSquashedInLSQ() const { return squashedInLSQ; }
545
546 /** Returns whether or not this instruction is in the LSQ. */
547 bool isInLSQ() const { return lsqEntry; }
548
549
550 //Reorder Buffer Functions
551 //-----------------------
552 /** Sets this instruction as a entry the ROB. */
553 void setInROB() { robEntry = true; }
554
555 /** Sets this instruction as a entry the ROB. */
556 void removeInROB() { robEntry = false; }
557
558 /** Sets this instruction as squashed in the ROB. */
559 void setSquashedInROB() { squashedInROB = true; }
560
561 /** Returns whether or not this instruction is squashed in the ROB. */
562 bool isSquashedInROB() const { return squashedInROB; }
563
564 /** Returns whether or not this instruction is in the ROB. */
565 bool isInROB() const { return robEntry; }
566
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402 /** Read the PC of this instruction. */ 403 const Addr readPC() const { return PC; } 404 405 /** Set the next PC of this instruction (its actual target). */
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571 void setNextPC(uint64_t val)
572 {
573 nextPC = val;
574// instResult.integer = val;
575 }
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406 void setNextPC(uint64_t val) { nextPC = val; } |
407
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577 void setASID(short addr_space_id) { asid = addr_space_id; }
578
579 void setThread(unsigned tid) { threadNumber = tid; }
580
581 void setState(ImplState *state) { thread = state; }
582
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408 /** Returns the exec context. 409 * @todo: Remove this once the ExecContext is no longer used. 410 */
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586 ExecContext *xcBase() { return thread->getXCProxy(); }
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411 ExecContext *xcBase() { return cpuXC->getProxy(); } |
412 413 private: 414 /** Instruction effective address. 415 * @todo: Consider if this is necessary or not. 416 */ 417 Addr instEffAddr;
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593
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418 /** Whether or not the effective address calculation is completed. 419 * @todo: Consider if this is necessary or not. 420 */ 421 bool eaCalcDone; 422 423 public: 424 /** Sets the effective address. */ 425 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 426 427 /** Returns the effective address. */
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604 const Addr &getEA() const { return req->vaddr; }
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428 const Addr &getEA() const { return instEffAddr; } |
429 430 /** Returns whether or not the eff. addr. calculation has been completed. */ 431 bool doneEACalc() { return eaCalcDone; } 432 433 /** Returns whether or not the eff. addr. source registers are ready. */ 434 bool eaSrcsReady(); 435
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612 /** Whether or not the memory operation is done. */
613 bool memOpDone;
614
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436 public: 437 /** Load queue index. */ 438 int16_t lqIdx; 439 440 /** Store queue index. */ 441 int16_t sqIdx;
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621
622 bool reachedCommit;
623
624 /** Iterator pointing to this BaseDynInst in the list of all insts. */
625 ListIt instListIt;
626
627 /** Returns iterator to this instruction in the list of all insts. */
628 ListIt &getInstListIt() { return instListIt; }
629
630 /** Sets iterator for this instruction in the list of all insts. */
631 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
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442}; 443 444template<class Impl> 445template<class T> 446inline Fault 447BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 448{
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639 if (executed) {
640 fault = cpu->read(req, data, lqIdx);
641 return fault;
642 }
643
644 req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
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449 MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags); |
450 req->asid = asid;
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646 req->thread_num = threadNumber;
647 req->pc = this->PC;
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451
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649 if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
650 TheISA::VMPageSize) {
651 return TheISA::genAlignmentFault();
652 }
653
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452 fault = cpu->translateDataReadReq(req); 453
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454 // Record key MemReq parameters so we can generate another one 455 // just like it for the timing access without calling translate() 456 // again (which might mess up the TLB). 457 // Do I ever really need this? -KTL 3/05 |
458 effAddr = req->vaddr; 459 physEffAddr = req->paddr; 460 memReqFlags = req->flags; 461
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462 /** 463 * @todo 464 * Replace the disjoint functional memory with a unified one and remove 465 * this hack. 466 */ 467#if !FULL_SYSTEM 468 req->paddr = req->vaddr; 469#endif 470 |
471 if (fault == NoFault) {
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661#if FULL_SYSTEM
662 if (cpu->system->memctrl->badaddr(physEffAddr)) {
663 fault = TheISA::genMachineCheckFault();
664 data = (T)-1;
665 this->setExecuted();
666 } else {
667 fault = cpu->read(req, data, lqIdx);
668 }
669#else
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472 fault = cpu->read(req, data, lqIdx);
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671#endif
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473 } else { 474 // Return a fixed value to keep simulation deterministic even 475 // along misspeculated paths. 476 data = (T)-1;
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676
677 // Commit will have to clean up whatever happened. Set this
678 // instruction as executed.
679 this->setExecuted();
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477 } 478 479 if (traceData) { 480 traceData->setAddr(addr); 481 traceData->setData(data); 482 } 483 484 return fault; 485} 486 487template<class Impl> 488template<class T> 489inline Fault 490BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 491{ 492 if (traceData) { 493 traceData->setAddr(addr); 494 traceData->setData(data); 495 } 496
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700 req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
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497 MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags); |
498 499 req->asid = asid;
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703 req->thread_num = threadNumber;
704 req->pc = this->PC;
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500
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706 if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
707 TheISA::VMPageSize) {
708 return TheISA::genAlignmentFault();
709 }
710
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501 fault = cpu->translateDataWriteReq(req); 502
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503 // Record key MemReq parameters so we can generate another one 504 // just like it for the timing access without calling translate() 505 // again (which might mess up the TLB). |
506 effAddr = req->vaddr; 507 physEffAddr = req->paddr; 508 memReqFlags = req->flags; 509
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510 /** 511 * @todo 512 * Replace the disjoint functional memory with a unified one and remove 513 * this hack. 514 */ 515#if !FULL_SYSTEM 516 req->paddr = req->vaddr; 517#endif 518 |
519 if (fault == NoFault) {
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718#if FULL_SYSTEM
719 if (cpu->system->memctrl->badaddr(physEffAddr)) {
720 fault = TheISA::genMachineCheckFault();
721 } else {
722 fault = cpu->write(req, data, sqIdx);
723 }
724#else
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520 fault = cpu->write(req, data, sqIdx);
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726#endif
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521 } 522 523 if (res) { 524 // always return some result to keep misspeculated paths 525 // (which will ignore faults) deterministic 526 *res = (fault == NoFault) ? req->result : 0; 527 } 528 529 return fault; 530} 531 532#endif // __CPU_BASE_DYN_INST_HH__
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