1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 410 unchanged lines hidden (view full) --- 419 void dump(); 420 421 /** Dumps out contents of this BaseDynInst into given string. */ 422 void dump(std::string &outstring); 423 424 /** Read this CPU's ID. */ 425 int cpuId() { return cpu->cpuId(); } 426 |
427 /** Read this CPU's data requestor ID */ 428 MasterID masterId() { return cpu->dataMasterId(); } 429 |
430 /** Read this context's system-wide ID **/ 431 int contextId() { return thread->contextId(); } 432 433 /** Returns the fault type. */ 434 Fault getFault() { return fault; } 435 436 /** Checks whether or not this instruction has had its branch target 437 * calculated yet. For now it is not utilized and is hacked to be --- 438 unchanged lines hidden (view full) --- 876 Request *sreqLow = NULL; 877 Request *sreqHigh = NULL; 878 879 if (reqMade && translationStarted) { 880 req = savedReq; 881 sreqLow = savedSreqLow; 882 sreqHigh = savedSreqHigh; 883 } else { |
884 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), |
885 thread->contextId(), threadNumber); 886 887 // Only split the request if the ISA supports unaligned accesses. 888 if (TheISA::HasUnalignedMemAcc) { 889 splitRequest(req, sreqLow, sreqHigh); 890 } 891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 892 } --- 45 unchanged lines hidden (view full) --- 938 Request *sreqLow = NULL; 939 Request *sreqHigh = NULL; 940 941 if (reqMade && translationStarted) { 942 req = savedReq; 943 sreqLow = savedSreqLow; 944 sreqHigh = savedSreqHigh; 945 } else { |
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), |
947 thread->contextId(), threadNumber); 948 949 // Only split the request if the ISA supports unaligned accesses. 950 if (TheISA::HasUnalignedMemAcc) { 951 splitRequest(req, sreqLow, sreqHigh); 952 } 953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 954 } --- 104 unchanged lines hidden --- |