1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 24 unchanged lines hidden (view full) --- 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" |
41#include "arch/utility.hh" |
42#include "base/fast_alloc.hh" 43#include "base/trace.hh" 44#include "config/full_system.hh" 45#include "config/the_isa.hh" 46#include "cpu/o3/comm.hh" 47#include "cpu/exetrace.hh" 48#include "cpu/inst_seq.hh" 49#include "cpu/op_class.hh" --- 187 unchanged lines hidden (view full) --- 237 /** The result of the instruction; assumes for now that there's only one 238 * destination register. 239 */ 240 Result instResult; 241 242 /** Records changes to result? */ 243 bool recordResult; 244 |
245 /** Did this instruction execute, or is it predicated false */ 246 bool predicate; 247 248 protected: |
249 /** PC state for this instruction. */ 250 TheISA::PCState pc; |
251 |
252 /** Predicted PC state after this instruction. */ 253 TheISA::PCState predPC; |
254 |
255 /** If this is a branch that was predicted taken */ 256 bool predTaken; 257 258 public: 259 260#ifdef DEBUG 261 void dumpSNList(); 262#endif --- 98 unchanged lines hidden (view full) --- 361 * index. 362 */ 363 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 364 { 365 _flatDestRegIdx[idx] = flattened_dest; 366 } 367 /** BaseDynInst constructor given a binary instruction. 368 * @param staticInst A StaticInstPtr to the underlying instruction. |
369 * @param pc The PC state for the instruction. 370 * @param predPC The predicted next PC state for the instruction. |
371 * @param seq_num The sequence number of the instruction. 372 * @param cpu Pointer to the instruction's CPU. 373 */ |
374 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc, 375 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); |
376 377 /** BaseDynInst constructor given a binary instruction. 378 * @param inst The binary instruction. |
379 * @param _pc The PC state for the instruction. 380 * @param _predPC The predicted next PC state for the instruction. |
381 * @param seq_num The sequence number of the instruction. 382 * @param cpu Pointer to the instruction's CPU. 383 */ |
384 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc, 385 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu); |
386 387 /** BaseDynInst constructor given a StaticInst pointer. 388 * @param _staticInst The StaticInst for this BaseDynInst. 389 */ 390 BaseDynInst(StaticInstPtr &_staticInst); 391 392 /** BaseDynInst destructor. */ 393 ~BaseDynInst(); --- 20 unchanged lines hidden (view full) --- 414 415 /** Checks whether or not this instruction has had its branch target 416 * calculated yet. For now it is not utilized and is hacked to be 417 * always false. 418 * @todo: Actually use this instruction. 419 */ 420 bool doneTargCalc() { return false; } 421 |
422 /** Set the predicted target of this current instruction. */ |
423 void setPredTarg(const TheISA::PCState &_predPC) |
424 { |
425 predPC = _predPC; |
426 } 427 |
428 const TheISA::PCState &readPredTarg() { return predPC; } 429 |
430 /** Returns the predicted PC immediately after the branch. */ |
431 Addr predInstAddr() { return predPC.instAddr(); } |
432 433 /** Returns the predicted PC two instructions after the branch */ |
434 Addr predNextInstAddr() { return predPC.nextInstAddr(); } |
435 436 /** Returns the predicted micro PC after the branch */ |
437 Addr predMicroPC() { return predPC.microPC(); } |
438 439 /** Returns whether the instruction was predicted taken or not. */ 440 bool readPredTaken() 441 { 442 return predTaken; 443 } 444 445 void setPredTaken(bool predicted_taken) 446 { 447 predTaken = predicted_taken; 448 } 449 450 /** Returns whether the instruction mispredicted. */ 451 bool mispredicted() 452 { |
453 TheISA::PCState tempPC = pc; 454 TheISA::advancePC(tempPC, staticInst); 455 return !(tempPC == predPC); |
456 } 457 458 // 459 // Instruction types. Forward checks to StaticInst object. 460 // 461 bool isNop() const { return staticInst->isNop(); } 462 bool isMemRef() const { return staticInst->isMemRef(); } 463 bool isLoad() const { return staticInst->isLoad(); } --- 60 unchanged lines hidden (view full) --- 524 * serializing state. 525 */ 526 bool isSerializeHandled() { return status[SerializeHandled]; } 527 528 /** Returns the opclass of this instruction. */ 529 OpClass opClass() const { return staticInst->opClass(); } 530 531 /** Returns the branch target address. */ |
532 TheISA::PCState branchTarget() const 533 { return staticInst->branchTarget(pc); } |
534 535 /** Returns the number of source registers. */ 536 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 537 538 /** Returns the number of destination registers. */ 539 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 540 541 // the following are used to track physical register usage --- 180 unchanged lines hidden (view full) --- 722 bool isInROB() const { return status[RobEntry]; } 723 724 /** Sets this instruction as squashed in the ROB. */ 725 void setSquashedInROB() { status.set(SquashedInROB); } 726 727 /** Returns whether or not this instruction is squashed in the ROB. */ 728 bool isSquashedInROB() const { return status[SquashedInROB]; } 729 |
730 /** Read the PC state of this instruction. */ 731 const TheISA::PCState pcState() const { return pc; } |
732 |
733 /** Set the PC state of this instruction. */ 734 const void pcState(const TheISA::PCState &val) { pc = val; } |
735 |
736 /** Read the PC of this instruction. */ 737 const Addr instAddr() const { return pc.instAddr(); } |
738 |
739 /** Read the PC of the next instruction. */ 740 const Addr nextInstAddr() const { return pc.nextInstAddr(); } |
741 |
742 /**Read the micro PC of this instruction. */ 743 const Addr microPC() const { return pc.microPC(); } |
744 745 bool readPredicate() 746 { 747 return predicate; 748 } 749 750 void setPredicate(bool val) 751 { --- 82 unchanged lines hidden (view full) --- 834}; 835 836template<class Impl> 837Fault 838BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 839 unsigned size, unsigned flags) 840{ 841 reqMade = true; |
842 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), |
843 thread->contextId(), threadNumber); 844 845 Request *sreqLow = NULL; 846 Request *sreqHigh = NULL; 847 848 // Only split the request if the ISA supports unaligned accesses. 849 if (TheISA::HasUnalignedMemAcc) { 850 splitRequest(req, sreqLow, sreqHigh); --- 44 unchanged lines hidden (view full) --- 895BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 896 Addr addr, unsigned flags, uint64_t *res) 897{ 898 if (traceData) { 899 traceData->setAddr(addr); 900 } 901 902 reqMade = true; |
903 Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(), |
904 thread->contextId(), threadNumber); 905 906 Request *sreqLow = NULL; 907 Request *sreqHigh = NULL; 908 909 // Only split the request if the ISA supports unaligned accesses. 910 if (TheISA::HasUnalignedMemAcc) { 911 splitRequest(req, sreqLow, sreqHigh); --- 95 unchanged lines hidden --- |