1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 232 unchanged lines hidden (view full) --- 241 bool recordResult; 242 243 /** PC of this instruction. */ 244 Addr PC; 245 246 /** Micro PC of this instruction. */ 247 Addr microPC; 248 |
249 /** Did this instruction execute, or is it predicated false */ 250 bool predicate; 251 |
252 protected: 253 /** Next non-speculative PC. It is not filled in at fetch, but rather 254 * once the target of the branch is truly known (either decode or 255 * execute). 256 */ 257 Addr nextPC; 258 259 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ --- 532 unchanged lines hidden (view full) --- 792#endif 793 } 794 795 void setNextMicroPC(Addr val) 796 { 797 nextMicroPC = val; 798 } 799 |
800 bool readPredicate() 801 { 802 return predicate; 803 } 804 805 void setPredicate(bool val) 806 { 807 predicate = val; 808 } 809 |
810 /** Sets the ASID. */ 811 void setASID(short addr_space_id) { asid = addr_space_id; } 812 813 /** Sets the thread id. */ 814 void setTid(ThreadID tid) { threadNumber = tid; } 815 816 /** Sets the pointer to the thread state. */ 817 void setThreadState(ImplState *state) { thread = state; } --- 240 unchanged lines hidden --- |