1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 101 unchanged lines hidden (view full) --- 110 * @param addr The address to read. 111 * @param data The read's data is written into this parameter. 112 * @param flags The request's flags. 113 * @return Returns any fault due to the read. 114 */ 115 template <class T> 116 Fault read(Addr addr, T &data, unsigned flags); 117 |
118 /** 119 * Does a write to a given address. 120 * @param data The data to be written. 121 * @param addr The address to write to. 122 * @param flags The request's flags. 123 * @param res The result of the write (for load locked/store conditionals). 124 * @return Returns any fault due to the write. 125 */ 126 template <class T> 127 Fault write(T data, Addr addr, unsigned flags, 128 uint64_t *res); 129 |
130 void prefetch(Addr addr, unsigned flags); 131 void writeHint(Addr addr, int size, unsigned flags); 132 Fault copySrcTranslate(Addr src); 133 Fault copy(Addr dest); 134 135 /** @todo: Consider making this private. */ 136 public: 137 /** The sequence number of the instruction. */ --- 708 unchanged lines hidden (view full) --- 846 { return thread->storeCondFailures; } 847 848 /** Sets the number of consecutive store conditional failures. */ 849 void setStCondFailures(unsigned sc_failures) 850 { thread->storeCondFailures = sc_failures; } 851}; 852 853template<class Impl> |
854template<class T> 855inline Fault 856BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 857{ 858 reqMade = true; 859 Request *req = new Request(); 860 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 861 req->setThreadContext(thread->contextId(), threadNumber); 862 |
863 fault = cpu->dtb->translate(req, thread->getTC(), false); |
864 865 if (req->isUncacheable()) 866 isUncacheable = true; 867 868 if (fault == NoFault) { 869 effAddr = req->getVaddr(); 870 effAddrValid = true; 871 physEffAddr = req->getPaddr(); --- 25 unchanged lines hidden (view full) --- 897 traceData->setAddr(addr); 898 traceData->setData(data); 899 } 900 901 return fault; 902} 903 904template<class Impl> |
905template<class T> 906inline Fault 907BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 908{ 909 if (traceData) { 910 traceData->setAddr(addr); 911 traceData->setData(data); 912 } 913 914 reqMade = true; 915 Request *req = new Request(); 916 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 917 req->setThreadContext(thread->contextId(), threadNumber); 918 |
919 fault = cpu->dtb->translate(req, thread->getTC(), true); |
920 921 if (req->isUncacheable()) 922 isUncacheable = true; 923 924 if (fault == NoFault) { 925 effAddr = req->getVaddr(); 926 effAddrValid = true; 927 physEffAddr = req->getPaddr(); --- 23 unchanged lines hidden --- |