1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 88 unchanged lines hidden (view full) --- 97 * @param addr The address to read. 98 * @param data The read's data is written into this parameter. 99 * @param flags The request's flags. 100 * @return Returns any fault due to the read. 101 */ 102 template <class T> 103 Fault read(Addr addr, T &data, unsigned flags); 104 |
105 Fault translateDataReadAddr(Addr vaddr, Addr &paddr, 106 int size, unsigned flags); 107 |
108 /** 109 * Does a write to a given address. 110 * @param data The data to be written. 111 * @param addr The address to write to. 112 * @param flags The request's flags. 113 * @param res The result of the write (for load locked/store conditionals). 114 * @return Returns any fault due to the write. 115 */ 116 template <class T> 117 Fault write(T data, Addr addr, unsigned flags, 118 uint64_t *res); 119 |
120 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, 121 int size, unsigned flags); 122 |
123 void prefetch(Addr addr, unsigned flags); 124 void writeHint(Addr addr, int size, unsigned flags); 125 Fault copySrcTranslate(Addr src); 126 Fault copy(Addr dest); 127 128 /** @todo: Consider making this private. */ 129 public: 130 /** The sequence number of the instruction. */ --- 708 unchanged lines hidden (view full) --- 839 { return thread->storeCondFailures; } 840 841 /** Sets the number of consecutive store conditional failures. */ 842 void setStCondFailures(unsigned sc_failures) 843 { thread->storeCondFailures = sc_failures; } 844}; 845 846template<class Impl> |
847Fault 848BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr, 849 int size, unsigned flags) 850{ 851 if (traceData) { 852 traceData->setAddr(vaddr); 853 } 854 855 reqMade = true; 856 Request *req = new Request(); 857 req->setVirt(asid, vaddr, size, flags, PC); 858 req->setThreadContext(thread->readCpuId(), threadNumber); 859 860 fault = cpu->translateDataReadReq(req, thread); 861 862 if (fault == NoFault) 863 paddr = req->getPaddr(); 864 865 delete req; 866 return fault; 867} 868 869template<class Impl> |
870template<class T> 871inline Fault 872BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 873{ 874 reqMade = true; 875 Request *req = new Request(); 876 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 877 req->setThreadContext(thread->readCpuId(), threadNumber); --- 35 unchanged lines hidden (view full) --- 913 traceData->setAddr(addr); 914 traceData->setData(data); 915 } 916 917 return fault; 918} 919 920template<class Impl> |
921Fault 922BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr, 923 int size, unsigned flags) 924{ 925 if (traceData) { 926 traceData->setAddr(vaddr); 927 } 928 929 reqMade = true; 930 Request *req = new Request(); 931 req->setVirt(asid, vaddr, size, flags, PC); 932 req->setThreadContext(thread->readCpuId(), threadNumber); 933 934 fault = cpu->translateDataWriteReq(req, thread); 935 936 if (fault == NoFault) 937 paddr = req->getPaddr(); 938 939 delete req; 940 return fault; 941} 942 943template<class Impl> |
944template<class T> 945inline Fault 946BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 947{ 948 if (traceData) { 949 traceData->setAddr(addr); 950 traceData->setData(data); 951 } --- 38 unchanged lines hidden --- |