1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_BASE_DYN_INST_HH__ 32#define __CPU_BASE_DYN_INST_HH__ 33 |
34#include <bitset> |
35#include <list> 36#include <string> 37 38#include "arch/faults.hh" 39#include "base/fast_alloc.hh" 40#include "base/trace.hh" 41#include "config/full_system.hh" 42#include "cpu/exetrace.hh" --- 79 unchanged lines hidden (view full) --- 122 Fault copySrcTranslate(Addr src); 123 Fault copy(Addr dest); 124 125 /** @todo: Consider making this private. */ 126 public: 127 /** The sequence number of the instruction. */ 128 InstSeqNum seqNum; 129 |
130 enum Status { 131 IqEntry, /// Instruction is in the IQ 132 RobEntry, /// Instruction is in the ROB 133 LsqEntry, /// Instruction is in the LSQ 134 Completed, /// Instruction has completed 135 ResultReady, /// Instruction has its result 136 CanIssue, /// Instruction can issue and execute 137 Issued, /// Instruction has issued 138 Executed, /// Instruction has executed 139 CanCommit, /// Instruction can commit 140 AtCommit, /// Instruction has reached commit 141 Committed, /// Instruction has committed 142 Squashed, /// Instruction is squashed 143 SquashedInIQ, /// Instruction is squashed in the IQ 144 SquashedInLSQ, /// Instruction is squashed in the LSQ 145 SquashedInROB, /// Instruction is squashed in the ROB 146 RecoverInst, /// Is a recover instruction 147 BlockingInst, /// Is a blocking instruction 148 ThreadsyncWait, /// Is a thread synchronization instruction 149 SerializeBefore, /// Needs to serialize on 150 /// instructions ahead of it 151 SerializeAfter, /// Needs to serialize instructions behind it 152 SerializeHandled, /// Serialization has been handled 153 NumStatus 154 }; |
155 |
156 /** The status of this BaseDynInst. Several bits can be set. */ 157 std::bitset<NumStatus> status; |
158 |
159 /** The thread this instruction is from. */ 160 short threadNumber; 161 162 /** data address space ID, for loads & stores. */ 163 short asid; 164 165 /** How many source registers are ready. */ 166 unsigned readyRegs; --- 23 unchanged lines hidden (view full) --- 190 Addr copySrcEffAddr; 191 192 /** Effective physical address for a copy source. */ 193 Addr copySrcPhysEffAddr; 194 195 /** The memory request flags (from translation). */ 196 unsigned memReqFlags; 197 |
198 union Result { 199 uint64_t integer; 200 float fp; 201 double dbl; 202 }; 203 204 /** The result of the instruction; assumes for now that there's only one 205 * destination register. --- 100 unchanged lines hidden (view full) --- 306 bool isReturn() const { return staticInst->isReturn(); } 307 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 308 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 309 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 310 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 311 bool isThreadSync() const { return staticInst->isThreadSync(); } 312 bool isSerializing() const { return staticInst->isSerializing(); } 313 bool isSerializeBefore() const |
314 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } |
315 bool isSerializeAfter() const |
316 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } |
317 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 318 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 319 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 320 bool isQuiesce() const { return staticInst->isQuiesce(); } 321 bool isIprAccess() const { return staticInst->isIprAccess(); } 322 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 323 324 /** Temporarily sets this instruction as a serialize before instruction. */ |
325 void setSerializeBefore() { status.set(SerializeBefore); } |
326 327 /** Clears the serializeBefore part of this instruction. */ |
328 void clearSerializeBefore() { status.reset(SerializeBefore); } |
329 330 /** Checks if this serializeBefore is only temporarily set. */ |
331 bool isTempSerializeBefore() { return status[SerializeBefore]; } |
332 |
333 /** Temporarily sets this instruction as a serialize after instruction. */ |
334 void setSerializeAfter() { status.set(SerializeAfter); } |
335 336 /** Clears the serializeAfter part of this instruction.*/ |
337 void clearSerializeAfter() { status.reset(SerializeAfter); } |
338 339 /** Checks if this serializeAfter is only temporarily set. */ |
340 bool isTempSerializeAfter() { return status[SerializeAfter]; } |
341 |
342 /** Sets the serialization part of this instruction as handled. */ 343 void setSerializeHandled() { status.set(SerializeHandled); } |
344 345 /** Checks if the serialization part of this instruction has been 346 * handled. This does not apply to the temporary serializing 347 * state; it only applies to this instruction's own permanent 348 * serializing state. 349 */ |
350 bool isSerializeHandled() { return status[SerializeHandled]; } |
351 |
352 /** Returns the opclass of this instruction. */ 353 OpClass opClass() const { return staticInst->opClass(); } 354 355 /** Returns the branch target address. */ 356 Addr branchTarget() const { return staticInst->branchTarget(PC); } 357 358 /** Returns the number of source registers. */ 359 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } --- 64 unchanged lines hidden (view full) --- 424 425 /** Returns if a source register is ready. */ 426 bool isReadySrcRegIdx(int idx) const 427 { 428 return this->_readySrcRegIdx[idx]; 429 } 430 431 /** Sets this instruction as completed. */ |
432 void setCompleted() { status.set(Completed); } |
433 434 /** Returns whether or not this instruction is completed. */ |
435 bool isCompleted() const { return status[Completed]; } |
436 |
437 /** Marks the result as ready. */ 438 void setResultReady() { status.set(ResultReady); } |
439 |
440 /** Returns whether or not the result is ready. */ 441 bool isResultReady() const { return status[ResultReady]; } |
442 443 /** Sets this instruction as ready to issue. */ |
444 void setCanIssue() { status.set(CanIssue); } |
445 446 /** Returns whether or not this instruction is ready to issue. */ |
447 bool readyToIssue() const { return status[CanIssue]; } |
448 449 /** Sets this instruction as issued from the IQ. */ |
450 void setIssued() { status.set(Issued); } |
451 452 /** Returns whether or not this instruction has issued. */ |
453 bool isIssued() const { return status[Issued]; } |
454 455 /** Sets this instruction as executed. */ |
456 void setExecuted() { status.set(Executed); } |
457 458 /** Returns whether or not this instruction has executed. */ |
459 bool isExecuted() const { return status[Executed]; } |
460 461 /** Sets this instruction as ready to commit. */ |
462 void setCanCommit() { status.set(CanCommit); } |
463 464 /** Clears this instruction as being ready to commit. */ |
465 void clearCanCommit() { status.reset(CanCommit); } |
466 467 /** Returns whether or not this instruction is ready to commit. */ |
468 bool readyToCommit() const { return status[CanCommit]; } |
469 |
470 void setAtCommit() { status.set(AtCommit); } 471 472 bool isAtCommit() { return status[AtCommit]; } 473 |
474 /** Sets this instruction as committed. */ |
475 void setCommitted() { status.set(Committed); } |
476 477 /** Returns whether or not this instruction is committed. */ |
478 bool isCommitted() const { return status[Committed]; } |
479 480 /** Sets this instruction as squashed. */ |
481 void setSquashed() { status.set(Squashed); } |
482 483 /** Returns whether or not this instruction is squashed. */ |
484 bool isSquashed() const { return status[Squashed]; } |
485 486 //Instruction Queue Entry 487 //----------------------- 488 /** Sets this instruction as a entry the IQ. */ |
489 void setInIQ() { status.set(IqEntry); } |
490 491 /** Sets this instruction as a entry the IQ. */ |
492 void clearInIQ() { status.reset(IqEntry); } |
493 |
494 /** Returns whether or not this instruction has issued. */ 495 bool isInIQ() const { return status[IqEntry]; } 496 |
497 /** Sets this instruction as squashed in the IQ. */ |
498 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} |
499 500 /** Returns whether or not this instruction is squashed in the IQ. */ |
501 bool isSquashedInIQ() const { return status[SquashedInIQ]; } |
502 |
503 |
504 //Load / Store Queue Functions 505 //----------------------- 506 /** Sets this instruction as a entry the LSQ. */ |
507 void setInLSQ() { status.set(LsqEntry); } |
508 509 /** Sets this instruction as a entry the LSQ. */ |
510 void removeInLSQ() { status.reset(LsqEntry); } |
511 |
512 /** Returns whether or not this instruction is in the LSQ. */ 513 bool isInLSQ() const { return status[LsqEntry]; } 514 |
515 /** Sets this instruction as squashed in the LSQ. */ |
516 void setSquashedInLSQ() { status.set(SquashedInLSQ);} |
517 518 /** Returns whether or not this instruction is squashed in the LSQ. */ |
519 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } |
520 |
521 |
522 //Reorder Buffer Functions 523 //----------------------- 524 /** Sets this instruction as a entry the ROB. */ |
525 void setInROB() { status.set(RobEntry); } |
526 527 /** Sets this instruction as a entry the ROB. */ |
528 void clearInROB() { status.reset(RobEntry); } |
529 |
530 /** Returns whether or not this instruction is in the ROB. */ 531 bool isInROB() const { return status[RobEntry]; } 532 |
533 /** Sets this instruction as squashed in the ROB. */ |
534 void setSquashedInROB() { status.set(SquashedInROB); } |
535 536 /** Returns whether or not this instruction is squashed in the ROB. */ |
537 bool isSquashedInROB() const { return status[SquashedInROB]; } |
538 |
539 /** Read the PC of this instruction. */ 540 const Addr readPC() const { return PC; } 541 542 /** Set the next PC of this instruction (its actual target). */ 543 void setNextPC(uint64_t val) 544 { 545 nextPC = val; 546 } 547 548 /** Sets the ASID. */ 549 void setASID(short addr_space_id) { asid = addr_space_id; } 550 551 /** Sets the thread id. */ 552 void setTid(unsigned tid) { threadNumber = tid; } 553 |
554 /** Sets the pointer to the thread state. */ |
555 void setThreadState(ImplState *state) { thread = state; } 556 |
557 /** Returns the thread context. */ |
558 ThreadContext *tcBase() { return thread->getTC(); } 559 560 private: 561 /** Instruction effective address. 562 * @todo: Consider if this is necessary or not. 563 */ 564 Addr instEffAddr; 565 --- 20 unchanged lines hidden (view full) --- 586 587 public: 588 /** Load queue index. */ 589 int16_t lqIdx; 590 591 /** Store queue index. */ 592 int16_t sqIdx; 593 |
594 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 595 ListIt instListIt; 596 597 /** Returns iterator to this instruction in the list of all insts. */ 598 ListIt &getInstListIt() { return instListIt; } 599 600 /** Sets iterator for this instruction in the list of all insts. */ 601 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } --- 106 unchanged lines hidden --- |