1/* |
2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited |
3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 68 unchanged lines hidden (view full) --- 79class BaseDynInst : public ExecContext, public RefCounted 80{ 81 public: 82 // Typedef for the CPU. 83 typedef typename Impl::CPUType ImplCPU; 84 typedef typename ImplCPU::ImplState ImplState; 85 using VecRegContainer = TheISA::VecRegContainer; 86 |
87 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*; 88 using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator; 89 using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator; 90 |
91 // The DynInstPtr type. 92 typedef typename Impl::DynInstPtr DynInstPtr; 93 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr; 94 95 // The list of instructions iterator type. 96 typedef typename std::list<DynInstPtr>::iterator ListIt; 97 98 enum { --- 103 unchanged lines hidden (view full) --- 202 uint8_t readyRegs; 203 204 public: 205 /////////////////////// Load Store Data ////////////////////// 206 /** The effective virtual address (lds & stores only). */ 207 Addr effAddr; 208 209 /** The effective physical address. */ |
210 Addr physEffAddr; |
211 |
212 /** The memory request flags (from translation). */ 213 unsigned memReqFlags; 214 215 /** data address space ID, for loads & stores. */ 216 short asid; 217 218 /** The size of the request */ 219 uint8_t effSize; 220 221 /** Pointer to the data for the memory access. */ 222 uint8_t *memData; 223 224 /** Load queue index. */ 225 int16_t lqIdx; |
226 LQIterator lqIt; |
227 228 /** Store queue index. */ 229 int16_t sqIdx; |
230 SQIterator sqIt; |
231 232 233 /////////////////////// TLB Miss ////////////////////// 234 /** |
235 * Saved memory request (needed when the DTB address translation is |
236 * delayed due to a hw page table walk). 237 */ |
238 LSQRequestPtr savedReq; |
239 240 /////////////////////// Checker ////////////////////// 241 // Need a copy of main request pointer to verify on writes. 242 RequestPtr reqToVerify; 243 244 protected: 245 /** Flattened register index of the destination registers of this 246 * instruction. --- 17 unchanged lines hidden (view full) --- 264 265 266 public: 267 /** Records changes to result? */ 268 void recordResult(bool f) { instFlags[RecordResult] = f; } 269 270 /** Is the effective virtual address valid. */ 271 bool effAddrValid() const { return instFlags[EffAddrValid]; } |
272 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; } |
273 274 /** Whether or not the memory operation is done. */ 275 bool memOpDone() const { return instFlags[MemOpDone]; } 276 void memOpDone(bool f) { instFlags[MemOpDone] = f; } 277 278 bool notAnInst() const { return instFlags[NotAnInst]; } 279 void setNotAnInst() { instFlags[NotAnInst] = true; } 280 --- 17 unchanged lines hidden (view full) --- 298 cpu->demapPage(vaddr, asn); 299 } 300 301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags); 302 303 Fault writeMem(uint8_t *data, unsigned size, Addr addr, 304 Request::Flags flags, uint64_t *res); 305 |
306 /** True if the DTB address translation has started. */ 307 bool translationStarted() const { return instFlags[TranslationStarted]; } 308 void translationStarted(bool f) { instFlags[TranslationStarted] = f; } 309 310 /** True if the DTB address translation has completed. */ 311 bool translationCompleted() const { return instFlags[TranslationCompleted]; } 312 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; } 313 --- 123 unchanged lines hidden (view full) --- 437 /** Read this CPU's data requestor ID */ 438 MasterID masterId() const { return cpu->dataMasterId(); } 439 440 /** Read this context's system-wide ID **/ 441 ContextID contextId() const { return thread->contextId(); } 442 443 /** Returns the fault type. */ 444 Fault getFault() const { return fault; } |
445 /** TODO: This I added for the LSQRequest side to be able to modify the 446 * fault. There should be a better mechanism in place. */ 447 Fault& getFault() { return fault; } |
448 449 /** Checks whether or not this instruction has had its branch target 450 * calculated yet. For now it is not utilized and is hacked to be 451 * always false. 452 * @todo: Actually use this instruction. 453 */ 454 bool doneTargCalc() { return false; } 455 --- 119 unchanged lines hidden (view full) --- 575 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 576 577 // the following are used to track physical register usage 578 // for machines with separate int & FP reg files 579 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 580 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 581 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } 582 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } |
583 int8_t numVecElemDestRegs() const 584 { |
585 return staticInst->numVecElemDestRegs(); 586 } 587 588 /** Returns the logical register index of the i'th destination register. */ 589 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); } 590 591 /** Returns the logical register index of the i'th source register. */ 592 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } --- 231 unchanged lines hidden (view full) --- 824 825 if (traceData) { 826 traceData->setPredicate(val); 827 } 828 } 829 830 /** Sets the ASID. */ 831 void setASID(short addr_space_id) { asid = addr_space_id; } |
832 short getASID() { return asid; } |
833 834 /** Sets the thread id. */ 835 void setTid(ThreadID tid) { threadNumber = tid; } 836 837 /** Sets the pointer to the thread state. */ 838 void setThreadState(ImplState *state) { thread = state; } 839 840 /** Returns the thread context. */ 841 ThreadContext *tcBase() { return thread->getTC(); } 842 843 public: 844 /** Returns whether or not the eff. addr. source registers are ready. */ 845 bool eaSrcsReady() const; 846 847 /** Is this instruction's memory access strictly ordered? */ 848 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } |
849 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; } |
850 851 /** Has this instruction generated a memory request. */ 852 bool hasRequest() const { return instFlags[ReqMade]; } |
853 /** Assert this instruction has generated a memory request. */ 854 void setRequest() { instFlags[ReqMade] = true; } |
855 856 /** Returns iterator to this instruction in the list of all insts. */ 857 ListIt &getInstListIt() { return instListIt; } 858 859 /** Sets iterator for this instruction in the list of all insts. */ 860 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 861 862 public: --- 15 unchanged lines hidden (view full) --- 878 { return cpu->getCpuAddrMonitor(threadNumber); } 879}; 880 881template<class Impl> 882Fault 883BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size, 884 Request::Flags flags) 885{ |
886 return cpu->pushRequest( 887 dynamic_cast<typename DynInstPtr::PtrType>(this), 888 /* ld */ true, nullptr, size, addr, flags, nullptr); |
889} 890 891template<class Impl> 892Fault 893BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, 894 Request::Flags flags, uint64_t *res) 895{ |
896 return cpu->pushRequest( 897 dynamic_cast<typename DynInstPtr::PtrType>(this), 898 /* st */ false, data, size, addr, flags, res); |
899} 900 |
901#endif // __CPU_BASE_DYN_INST_HH__ |