1/* 2 * Copyright (c) 2011,2013 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 903 unchanged lines hidden (view full) --- 912 if (fault != NoFault) { 913 // Return a fixed value to keep simulation deterministic even 914 // along misspeculated paths. 915 if (data) 916 bzero(data, size); 917 } 918 } 919 |
920 if (traceData) 921 traceData->setMem(addr, size, flags); |
922 923 return fault; 924} 925 926template<class Impl> 927Fault 928BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, 929 Addr addr, unsigned flags, uint64_t *res) 930{ |
931 if (traceData) 932 traceData->setMem(addr, size, flags); |
933 934 instFlags[ReqMade] = true; 935 Request *req = NULL; 936 Request *sreqLow = NULL; 937 Request *sreqHigh = NULL; 938 939 if (instFlags[ReqMade] && translationStarted()) { 940 req = savedReq; --- 133 unchanged lines hidden --- |