101,103c101,108
< /** The StaticInst used by this BaseDynInst. */
< StaticInstPtr staticInst;
< StaticInstPtr macroop;
---
> union Result {
> uint64_t integer;
> double dbl;
> void set(uint64_t i) { integer = i; }
> void set(double d) { dbl = d; }
> void get(uint64_t& i) { i = integer; }
> void get(double& d) { d = dbl; }
> };
105,186c110
< ////////////////////////////////////////////
< //
< // INSTRUCTION EXECUTION
< //
< ////////////////////////////////////////////
< /** InstRecord that tracks this instructions. */
< Trace::InstRecord *traceData;
<
< void demapPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
< void demapInstPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
< void demapDataPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
<
< Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
<
< Fault writeMem(uint8_t *data, unsigned size,
< Addr addr, unsigned flags, uint64_t *res);
<
< /** Splits a request in two if it crosses a dcache block. */
< void splitRequest(RequestPtr req, RequestPtr &sreqLow,
< RequestPtr &sreqHigh);
<
< /** Initiate a DTB address translation. */
< void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
< RequestPtr sreqHigh, uint64_t *res,
< BaseTLB::Mode mode);
<
< /** Finish a DTB address translation. */
< void finishTranslation(WholeTranslationState *state);
<
< /** True if the DTB address translation has started. */
< bool translationStarted;
<
< /** True if the DTB address translation has completed. */
< bool translationCompleted;
<
< /** True if this address was found to match a previous load and they issued
< * out of order. If that happend, then it's only a problem if an incoming
< * snoop invalidate modifies the line, in which case we need to squash.
< * If nothing modified the line the order doesn't matter.
< */
< bool possibleLoadViolation;
<
< /** True if the address hit a external snoop while sitting in the LSQ.
< * If this is true and a older instruction sees it, this instruction must
< * reexecute
< */
< bool hitExternalSnoop;
<
< /**
< * Returns true if the DTB address translation is being delayed due to a hw
< * page table walk.
< */
< bool isTranslationDelayed() const
< {
< return (translationStarted && !translationCompleted);
< }
<
< /**
< * Saved memory requests (needed when the DTB address translation is
< * delayed due to a hw page table walk).
< */
< RequestPtr savedReq;
< RequestPtr savedSreqLow;
< RequestPtr savedSreqHigh;
<
< // Need a copy of main request pointer to verify on writes.
< RequestPtr reqToVerify;
<
< /** @todo: Consider making this private. */
< public:
< /** The sequence number of the instruction. */
< InstSeqNum seqNum;
<
---
> protected:
213,214c137,154
< /** The status of this BaseDynInst. Several bits can be set. */
< std::bitset<NumStatus> status;
---
> enum Flags {
> TranslationStarted,
> TranslationCompleted,
> PossibleLoadViolation,
> HitExternalSnoop,
> EffAddrValid,
> RecordResult,
> Predicate,
> PredTaken,
> /** Whether or not the effective address calculation is completed.
> * @todo: Consider if this is necessary or not.
> */
> EACalcDone,
> IsUncacheable,
> ReqMade,
> MemOpDone,
> MaxFlags
> };
216,217c156,158
< /** The thread this instruction is from. */
< ThreadID threadNumber;
---
> public:
> /** The sequence number of the instruction. */
> InstSeqNum seqNum;
219,220c160,161
< /** data address space ID, for loads & stores. */
< short asid;
---
> /** The StaticInst used by this BaseDynInst. */
> StaticInstPtr staticInst;
222,224d162
< /** How many source registers are ready. */
< unsigned readyRegs;
<
234,235c172,173
< /** Pointer to the data for the memory access. */
< uint8_t *memData;
---
> /** InstRecord that tracks this instructions. */
> Trace::InstRecord *traceData;
237,238c175,179
< /** The effective virtual address (lds & stores only). */
< Addr effAddr;
---
> protected:
> /** The result of the instruction; assumes an instruction can have many
> * destination registers.
> */
> std::queue<Result> instResult;
240,241c181,182
< /** The size of the request */
< Addr effSize;
---
> /** PC state for this instruction. */
> TheISA::PCState pc;
243,244c184,185
< /** Is the effective virtual address valid. */
< bool effAddrValid;
---
> /* An amalgamation of a lot of boolean values into one */
> std::bitset<MaxFlags> instFlags;
245a187,216
> /** The status of this BaseDynInst. Several bits can be set. */
> std::bitset<NumStatus> status;
>
> /** Whether or not the source register is ready.
> * @todo: Not sure this should be here vs the derived class.
> */
> std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
>
> public:
> /** The thread this instruction is from. */
> ThreadID threadNumber;
>
> /** Iterator pointing to this BaseDynInst in the list of all insts. */
> ListIt instListIt;
>
> ////////////////////// Branch Data ///////////////
> /** Predicted PC state after this instruction. */
> TheISA::PCState predPC;
>
> /** The Macroop if one exists */
> StaticInstPtr macroop;
>
> /** How many source registers are ready. */
> uint8_t readyRegs;
>
> public:
> /////////////////////// Load Store Data //////////////////////
> /** The effective virtual address (lds & stores only). */
> Addr effAddr;
>
252,259c223,224
< union Result {
< uint64_t integer;
< double dbl;
< void set(uint64_t i) { integer = i; }
< void set(double d) { dbl = d; }
< void get(uint64_t& i) { i = integer; }
< void get(double& d) { d = dbl; }
< };
---
> /** data address space ID, for loads & stores. */
> short asid;
261,264c226,227
< /** The result of the instruction; assumes an instruction can have many
< * destination registers.
< */
< std::queue<Result> instResult;
---
> /** The size of the request */
> uint8_t effSize;
266,267c229,230
< /** Records changes to result? */
< bool recordResult;
---
> /** Pointer to the data for the memory access. */
> uint8_t *memData;
269,270c232,233
< /** Did this instruction execute, or is it predicated false */
< bool predicate;
---
> /** Load queue index. */
> int16_t lqIdx;
272,274c235,236
< protected:
< /** PC state for this instruction. */
< TheISA::PCState pc;
---
> /** Store queue index. */
> int16_t sqIdx;
276,277d237
< /** Predicted PC state after this instruction. */
< TheISA::PCState predPC;
279,280c239,246
< /** If this is a branch that was predicted taken */
< bool predTaken;
---
> /////////////////////// TLB Miss //////////////////////
> /**
> * Saved memory requests (needed when the DTB address translation is
> * delayed due to a hw page table walk).
> */
> RequestPtr savedReq;
> RequestPtr savedSreqLow;
> RequestPtr savedSreqHigh;
282c248,250
< public:
---
> /////////////////////// Checker //////////////////////
> // Need a copy of main request pointer to verify on writes.
> RequestPtr reqToVerify;
284,289c252,254
< #ifdef DEBUG
< void dumpSNList();
< #endif
<
< /** Whether or not the source register is ready.
< * @todo: Not sure this should be here vs the derived class.
---
> private:
> /** Instruction effective address.
> * @todo: Consider if this is necessary or not.
291c256
< bool _readySrcRegIdx[MaxInstSrcRegs];
---
> Addr instEffAddr;
299,303d263
< /** Flattened register index of the source registers of this
< * instruction.
< */
< TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
<
318a279
>
319a281,282
> /** Records changes to result? */
> void recordResult(bool f) { instFlags[RecordResult] = f; }
320a284,364
> /** Is the effective virtual address valid. */
> bool effAddrValid() const { return instFlags[EffAddrValid]; }
>
> /** Whether or not the memory operation is done. */
> bool memOpDone() const { return instFlags[MemOpDone]; }
> void memOpDone(bool f) { instFlags[MemOpDone] = f; }
>
>
> ////////////////////////////////////////////
> //
> // INSTRUCTION EXECUTION
> //
> ////////////////////////////////////////////
>
> void demapPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
> void demapInstPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
> void demapDataPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
>
> Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
>
> Fault writeMem(uint8_t *data, unsigned size,
> Addr addr, unsigned flags, uint64_t *res);
>
> /** Splits a request in two if it crosses a dcache block. */
> void splitRequest(RequestPtr req, RequestPtr &sreqLow,
> RequestPtr &sreqHigh);
>
> /** Initiate a DTB address translation. */
> void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
> RequestPtr sreqHigh, uint64_t *res,
> BaseTLB::Mode mode);
>
> /** Finish a DTB address translation. */
> void finishTranslation(WholeTranslationState *state);
>
> /** True if the DTB address translation has started. */
> bool translationStarted() const { return instFlags[TranslationStarted]; }
> void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
>
> /** True if the DTB address translation has completed. */
> bool translationCompleted() const { return instFlags[TranslationCompleted]; }
> void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
>
> /** True if this address was found to match a previous load and they issued
> * out of order. If that happend, then it's only a problem if an incoming
> * snoop invalidate modifies the line, in which case we need to squash.
> * If nothing modified the line the order doesn't matter.
> */
> bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
> void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
>
> /** True if the address hit a external snoop while sitting in the LSQ.
> * If this is true and a older instruction sees it, this instruction must
> * reexecute
> */
> bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
> void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
>
> /**
> * Returns true if the DTB address translation is being delayed due to a hw
> * page table walk.
> */
> bool isTranslationDelayed() const
> {
> return (translationStarted() && !translationCompleted());
> }
>
> public:
> #ifdef DEBUG
> void dumpSNList();
> #endif
>
331a376
> assert(TheISA::MaxInstSrcRegs > idx);
343,348d387
< /** Returns the flattened register index of the i'th source register */
< TheISA::RegIndex flattenedSrcRegIdx(int idx) const
< {
< return _flatSrcRegIdx[idx];
< }
<
377,383d415
< /** Flattens a source architectural register index into a logical index.
< */
< void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
< {
< _flatSrcRegIdx[idx] = flattened_src;
< }
<
460c492
< return predTaken;
---
> return instFlags[PredTaken];
465c497
< predTaken = predicted_taken;
---
> instFlags[PredTaken] = predicted_taken;
591c623
< if (recordResult) {
---
> if (instFlags[RecordResult]) {
777c809
< return predicate;
---
> return instFlags[Predicate];
782c814
< predicate = val;
---
> instFlags[Predicate] = val;
801,817d832
< private:
< /** Instruction effective address.
< * @todo: Consider if this is necessary or not.
< */
< Addr instEffAddr;
<
< /** Whether or not the effective address calculation is completed.
< * @todo: Consider if this is necessary or not.
< */
< bool eaCalcDone;
<
< /** Is this instruction's memory access uncacheable. */
< bool isUncacheable;
<
< /** Has this instruction generated a memory request. */
< bool reqMade;
<
820c835
< void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
---
> void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
826c841
< bool doneEACalc() { return eaCalcDone; }
---
> bool doneEACalc() { return instFlags[EACalcDone]; }
831,833d845
< /** Whether or not the memory operation is done. */
< bool memOpDone;
<
835c847
< bool uncacheable() { return isUncacheable; }
---
> bool uncacheable() { return instFlags[IsUncacheable]; }
838c850
< bool hasRequest() { return reqMade; }
---
> bool hasRequest() { return instFlags[ReqMade]; }
840,849d851
< public:
< /** Load queue index. */
< int16_t lqIdx;
<
< /** Store queue index. */
< int16_t sqIdx;
<
< /** Iterator pointing to this BaseDynInst in the list of all insts. */
< ListIt instListIt;
<
871c873
< reqMade = true;
---
> instFlags[ReqMade] = true;
876c878
< if (reqMade && translationStarted) {
---
> if (instFlags[ReqMade] && translationStarted()) {
891c893
< if (translationCompleted) {
---
> if (translationCompleted()) {
895c897
< effAddrValid = true;
---
> instFlags[EffAddrValid] = true;
934c936
< reqMade = true;
---
> instFlags[ReqMade] = true;
939c941
< if (reqMade && translationStarted) {
---
> if (instFlags[ReqMade] && translationStarted()) {
954c956
< if (fault == NoFault && translationCompleted) {
---
> if (fault == NoFault && translationCompleted()) {
957c959
< effAddrValid = true;
---
> instFlags[EffAddrValid] = true;
994c996
< translationStarted = true;
---
> translationStarted(true);
1004c1006
< if (!translationCompleted) {
---
> if (!translationCompleted()) {
1022c1024
< if (!translationCompleted) {
---
> if (!translationCompleted()) {
1037,1038c1039
< if (state->isUncacheable())
< isUncacheable = true;
---
> instFlags[IsUncacheable] = state->isUncacheable();
1054c1055
< translationCompleted = true;
---
> translationCompleted(true);
< /** The StaticInst used by this BaseDynInst. */
< StaticInstPtr staticInst;
< StaticInstPtr macroop;
---
> union Result {
> uint64_t integer;
> double dbl;
> void set(uint64_t i) { integer = i; }
> void set(double d) { dbl = d; }
> void get(uint64_t& i) { i = integer; }
> void get(double& d) { d = dbl; }
> };
105,186c110
< ////////////////////////////////////////////
< //
< // INSTRUCTION EXECUTION
< //
< ////////////////////////////////////////////
< /** InstRecord that tracks this instructions. */
< Trace::InstRecord *traceData;
<
< void demapPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
< void demapInstPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
< void demapDataPage(Addr vaddr, uint64_t asn)
< {
< cpu->demapPage(vaddr, asn);
< }
<
< Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
<
< Fault writeMem(uint8_t *data, unsigned size,
< Addr addr, unsigned flags, uint64_t *res);
<
< /** Splits a request in two if it crosses a dcache block. */
< void splitRequest(RequestPtr req, RequestPtr &sreqLow,
< RequestPtr &sreqHigh);
<
< /** Initiate a DTB address translation. */
< void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
< RequestPtr sreqHigh, uint64_t *res,
< BaseTLB::Mode mode);
<
< /** Finish a DTB address translation. */
< void finishTranslation(WholeTranslationState *state);
<
< /** True if the DTB address translation has started. */
< bool translationStarted;
<
< /** True if the DTB address translation has completed. */
< bool translationCompleted;
<
< /** True if this address was found to match a previous load and they issued
< * out of order. If that happend, then it's only a problem if an incoming
< * snoop invalidate modifies the line, in which case we need to squash.
< * If nothing modified the line the order doesn't matter.
< */
< bool possibleLoadViolation;
<
< /** True if the address hit a external snoop while sitting in the LSQ.
< * If this is true and a older instruction sees it, this instruction must
< * reexecute
< */
< bool hitExternalSnoop;
<
< /**
< * Returns true if the DTB address translation is being delayed due to a hw
< * page table walk.
< */
< bool isTranslationDelayed() const
< {
< return (translationStarted && !translationCompleted);
< }
<
< /**
< * Saved memory requests (needed when the DTB address translation is
< * delayed due to a hw page table walk).
< */
< RequestPtr savedReq;
< RequestPtr savedSreqLow;
< RequestPtr savedSreqHigh;
<
< // Need a copy of main request pointer to verify on writes.
< RequestPtr reqToVerify;
<
< /** @todo: Consider making this private. */
< public:
< /** The sequence number of the instruction. */
< InstSeqNum seqNum;
<
---
> protected:
213,214c137,154
< /** The status of this BaseDynInst. Several bits can be set. */
< std::bitset<NumStatus> status;
---
> enum Flags {
> TranslationStarted,
> TranslationCompleted,
> PossibleLoadViolation,
> HitExternalSnoop,
> EffAddrValid,
> RecordResult,
> Predicate,
> PredTaken,
> /** Whether or not the effective address calculation is completed.
> * @todo: Consider if this is necessary or not.
> */
> EACalcDone,
> IsUncacheable,
> ReqMade,
> MemOpDone,
> MaxFlags
> };
216,217c156,158
< /** The thread this instruction is from. */
< ThreadID threadNumber;
---
> public:
> /** The sequence number of the instruction. */
> InstSeqNum seqNum;
219,220c160,161
< /** data address space ID, for loads & stores. */
< short asid;
---
> /** The StaticInst used by this BaseDynInst. */
> StaticInstPtr staticInst;
222,224d162
< /** How many source registers are ready. */
< unsigned readyRegs;
<
234,235c172,173
< /** Pointer to the data for the memory access. */
< uint8_t *memData;
---
> /** InstRecord that tracks this instructions. */
> Trace::InstRecord *traceData;
237,238c175,179
< /** The effective virtual address (lds & stores only). */
< Addr effAddr;
---
> protected:
> /** The result of the instruction; assumes an instruction can have many
> * destination registers.
> */
> std::queue<Result> instResult;
240,241c181,182
< /** The size of the request */
< Addr effSize;
---
> /** PC state for this instruction. */
> TheISA::PCState pc;
243,244c184,185
< /** Is the effective virtual address valid. */
< bool effAddrValid;
---
> /* An amalgamation of a lot of boolean values into one */
> std::bitset<MaxFlags> instFlags;
245a187,216
> /** The status of this BaseDynInst. Several bits can be set. */
> std::bitset<NumStatus> status;
>
> /** Whether or not the source register is ready.
> * @todo: Not sure this should be here vs the derived class.
> */
> std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
>
> public:
> /** The thread this instruction is from. */
> ThreadID threadNumber;
>
> /** Iterator pointing to this BaseDynInst in the list of all insts. */
> ListIt instListIt;
>
> ////////////////////// Branch Data ///////////////
> /** Predicted PC state after this instruction. */
> TheISA::PCState predPC;
>
> /** The Macroop if one exists */
> StaticInstPtr macroop;
>
> /** How many source registers are ready. */
> uint8_t readyRegs;
>
> public:
> /////////////////////// Load Store Data //////////////////////
> /** The effective virtual address (lds & stores only). */
> Addr effAddr;
>
252,259c223,224
< union Result {
< uint64_t integer;
< double dbl;
< void set(uint64_t i) { integer = i; }
< void set(double d) { dbl = d; }
< void get(uint64_t& i) { i = integer; }
< void get(double& d) { d = dbl; }
< };
---
> /** data address space ID, for loads & stores. */
> short asid;
261,264c226,227
< /** The result of the instruction; assumes an instruction can have many
< * destination registers.
< */
< std::queue<Result> instResult;
---
> /** The size of the request */
> uint8_t effSize;
266,267c229,230
< /** Records changes to result? */
< bool recordResult;
---
> /** Pointer to the data for the memory access. */
> uint8_t *memData;
269,270c232,233
< /** Did this instruction execute, or is it predicated false */
< bool predicate;
---
> /** Load queue index. */
> int16_t lqIdx;
272,274c235,236
< protected:
< /** PC state for this instruction. */
< TheISA::PCState pc;
---
> /** Store queue index. */
> int16_t sqIdx;
276,277d237
< /** Predicted PC state after this instruction. */
< TheISA::PCState predPC;
279,280c239,246
< /** If this is a branch that was predicted taken */
< bool predTaken;
---
> /////////////////////// TLB Miss //////////////////////
> /**
> * Saved memory requests (needed when the DTB address translation is
> * delayed due to a hw page table walk).
> */
> RequestPtr savedReq;
> RequestPtr savedSreqLow;
> RequestPtr savedSreqHigh;
282c248,250
< public:
---
> /////////////////////// Checker //////////////////////
> // Need a copy of main request pointer to verify on writes.
> RequestPtr reqToVerify;
284,289c252,254
< #ifdef DEBUG
< void dumpSNList();
< #endif
<
< /** Whether or not the source register is ready.
< * @todo: Not sure this should be here vs the derived class.
---
> private:
> /** Instruction effective address.
> * @todo: Consider if this is necessary or not.
291c256
< bool _readySrcRegIdx[MaxInstSrcRegs];
---
> Addr instEffAddr;
299,303d263
< /** Flattened register index of the source registers of this
< * instruction.
< */
< TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
<
318a279
>
319a281,282
> /** Records changes to result? */
> void recordResult(bool f) { instFlags[RecordResult] = f; }
320a284,364
> /** Is the effective virtual address valid. */
> bool effAddrValid() const { return instFlags[EffAddrValid]; }
>
> /** Whether or not the memory operation is done. */
> bool memOpDone() const { return instFlags[MemOpDone]; }
> void memOpDone(bool f) { instFlags[MemOpDone] = f; }
>
>
> ////////////////////////////////////////////
> //
> // INSTRUCTION EXECUTION
> //
> ////////////////////////////////////////////
>
> void demapPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
> void demapInstPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
> void demapDataPage(Addr vaddr, uint64_t asn)
> {
> cpu->demapPage(vaddr, asn);
> }
>
> Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
>
> Fault writeMem(uint8_t *data, unsigned size,
> Addr addr, unsigned flags, uint64_t *res);
>
> /** Splits a request in two if it crosses a dcache block. */
> void splitRequest(RequestPtr req, RequestPtr &sreqLow,
> RequestPtr &sreqHigh);
>
> /** Initiate a DTB address translation. */
> void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
> RequestPtr sreqHigh, uint64_t *res,
> BaseTLB::Mode mode);
>
> /** Finish a DTB address translation. */
> void finishTranslation(WholeTranslationState *state);
>
> /** True if the DTB address translation has started. */
> bool translationStarted() const { return instFlags[TranslationStarted]; }
> void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
>
> /** True if the DTB address translation has completed. */
> bool translationCompleted() const { return instFlags[TranslationCompleted]; }
> void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
>
> /** True if this address was found to match a previous load and they issued
> * out of order. If that happend, then it's only a problem if an incoming
> * snoop invalidate modifies the line, in which case we need to squash.
> * If nothing modified the line the order doesn't matter.
> */
> bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
> void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
>
> /** True if the address hit a external snoop while sitting in the LSQ.
> * If this is true and a older instruction sees it, this instruction must
> * reexecute
> */
> bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
> void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
>
> /**
> * Returns true if the DTB address translation is being delayed due to a hw
> * page table walk.
> */
> bool isTranslationDelayed() const
> {
> return (translationStarted() && !translationCompleted());
> }
>
> public:
> #ifdef DEBUG
> void dumpSNList();
> #endif
>
331a376
> assert(TheISA::MaxInstSrcRegs > idx);
343,348d387
< /** Returns the flattened register index of the i'th source register */
< TheISA::RegIndex flattenedSrcRegIdx(int idx) const
< {
< return _flatSrcRegIdx[idx];
< }
<
377,383d415
< /** Flattens a source architectural register index into a logical index.
< */
< void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
< {
< _flatSrcRegIdx[idx] = flattened_src;
< }
<
460c492
< return predTaken;
---
> return instFlags[PredTaken];
465c497
< predTaken = predicted_taken;
---
> instFlags[PredTaken] = predicted_taken;
591c623
< if (recordResult) {
---
> if (instFlags[RecordResult]) {
777c809
< return predicate;
---
> return instFlags[Predicate];
782c814
< predicate = val;
---
> instFlags[Predicate] = val;
801,817d832
< private:
< /** Instruction effective address.
< * @todo: Consider if this is necessary or not.
< */
< Addr instEffAddr;
<
< /** Whether or not the effective address calculation is completed.
< * @todo: Consider if this is necessary or not.
< */
< bool eaCalcDone;
<
< /** Is this instruction's memory access uncacheable. */
< bool isUncacheable;
<
< /** Has this instruction generated a memory request. */
< bool reqMade;
<
820c835
< void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
---
> void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
826c841
< bool doneEACalc() { return eaCalcDone; }
---
> bool doneEACalc() { return instFlags[EACalcDone]; }
831,833d845
< /** Whether or not the memory operation is done. */
< bool memOpDone;
<
835c847
< bool uncacheable() { return isUncacheable; }
---
> bool uncacheable() { return instFlags[IsUncacheable]; }
838c850
< bool hasRequest() { return reqMade; }
---
> bool hasRequest() { return instFlags[ReqMade]; }
840,849d851
< public:
< /** Load queue index. */
< int16_t lqIdx;
<
< /** Store queue index. */
< int16_t sqIdx;
<
< /** Iterator pointing to this BaseDynInst in the list of all insts. */
< ListIt instListIt;
<
871c873
< reqMade = true;
---
> instFlags[ReqMade] = true;
876c878
< if (reqMade && translationStarted) {
---
> if (instFlags[ReqMade] && translationStarted()) {
891c893
< if (translationCompleted) {
---
> if (translationCompleted()) {
895c897
< effAddrValid = true;
---
> instFlags[EffAddrValid] = true;
934c936
< reqMade = true;
---
> instFlags[ReqMade] = true;
939c941
< if (reqMade && translationStarted) {
---
> if (instFlags[ReqMade] && translationStarted()) {
954c956
< if (fault == NoFault && translationCompleted) {
---
> if (fault == NoFault && translationCompleted()) {
957c959
< effAddrValid = true;
---
> instFlags[EffAddrValid] = true;
994c996
< translationStarted = true;
---
> translationStarted(true);
1004c1006
< if (!translationCompleted) {
---
> if (!translationCompleted()) {
1022c1024
< if (!translationCompleted) {
---
> if (!translationCompleted()) {
1037,1038c1039
< if (state->isUncacheable())
< isUncacheable = true;
---
> instFlags[IsUncacheable] = state->isUncacheable();
1054c1055
< translationCompleted = true;
---
> translationCompleted(true);