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> #include "arch/utility.hh"
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< /** PC of this instruction. */
< Addr PC;
<
< /** Micro PC of this instruction. */
< Addr microPC;
<
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< /** Next non-speculative PC. It is not filled in at fetch, but rather
< * once the target of the branch is truly known (either decode or
< * execute).
< */
< Addr nextPC;
---
> /** PC state for this instruction. */
> TheISA::PCState pc;
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< /** Next non-speculative NPC. Target PC for Mips or Sparc. */
< Addr nextNPC;
---
> /** Predicted PC state after this instruction. */
> TheISA::PCState predPC;
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< /** Next non-speculative micro PC. */
< Addr nextMicroPC;
<
< /** Predicted next PC. */
< Addr predPC;
<
< /** Predicted next NPC. */
< Addr predNPC;
<
< /** Predicted next microPC */
< Addr predMicroPC;
<
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< * @param PC The PC of the instruction.
< * @param pred_PC The predicted next PC.
< * @param pred_NPC The predicted next NPC.
---
> * @param pc The PC state for the instruction.
> * @param predPC The predicted next PC state for the instruction.
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< BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
< Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
< InstSeqNum seq_num, ImplCPU *cpu);
---
> BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
> TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
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< * @param PC The PC of the instruction.
< * @param pred_PC The predicted next PC.
< * @param pred_NPC The predicted next NPC.
---
> * @param _pc The PC state for the instruction.
> * @param _predPC The predicted next PC state for the instruction.
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< BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
< Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
< InstSeqNum seq_num, ImplCPU *cpu);
---
> BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
> TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
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< /** Returns the next PC. This could be the speculative next PC if it is
< * called prior to the actual branch target being calculated.
< */
< Addr readNextPC() { return nextPC; }
<
< /** Returns the next NPC. This could be the speculative next NPC if it is
< * called prior to the actual branch target being calculated.
< */
< Addr readNextNPC()
< {
< #if ISA_HAS_DELAY_SLOT
< return nextNPC;
< #else
< return nextPC + sizeof(TheISA::MachInst);
< #endif
< }
<
< Addr readNextMicroPC()
< {
< return nextMicroPC;
< }
<
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< void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
< Addr predicted_MicroPC)
---
> void setPredTarg(const TheISA::PCState &_predPC)
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< predPC = predicted_PC;
< predNPC = predicted_NPC;
< predMicroPC = predicted_MicroPC;
---
> predPC = _predPC;
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> const TheISA::PCState &readPredTarg() { return predPC; }
>
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< Addr readPredPC() { return predPC; }
---
> Addr predInstAddr() { return predPC.instAddr(); }
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< Addr readPredNPC() { return predNPC; }
---
> Addr predNextInstAddr() { return predPC.nextInstAddr(); }
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< Addr readPredMicroPC() { return predMicroPC; }
---
> Addr predMicroPC() { return predPC.microPC(); }
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< return readPredPC() != readNextPC() ||
< readPredNPC() != readNextNPC() ||
< readPredMicroPC() != readNextMicroPC();
---
> TheISA::PCState tempPC = pc;
> TheISA::advancePC(tempPC, staticInst);
> return !(tempPC == predPC);
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< Addr branchTarget() const { return staticInst->branchTarget(PC); }
---
> TheISA::PCState branchTarget() const
> { return staticInst->branchTarget(pc); }
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< /** Read the PC of this instruction. */
< const Addr readPC() const { return PC; }
---
> /** Read the PC state of this instruction. */
> const TheISA::PCState pcState() const { return pc; }
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< /**Read the micro PC of this instruction. */
< const Addr readMicroPC() const { return microPC; }
---
> /** Set the PC state of this instruction. */
> const void pcState(const TheISA::PCState &val) { pc = val; }
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< /** Set the next PC of this instruction (its actual target). */
< void setNextPC(Addr val)
< {
< nextPC = val;
< }
---
> /** Read the PC of this instruction. */
> const Addr instAddr() const { return pc.instAddr(); }
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< /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
< void setNextNPC(Addr val)
< {
< #if ISA_HAS_DELAY_SLOT
< nextNPC = val;
< #endif
< }
---
> /** Read the PC of the next instruction. */
> const Addr nextInstAddr() const { return pc.nextInstAddr(); }
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< void setNextMicroPC(Addr val)
< {
< nextMicroPC = val;
< }
---
> /**Read the micro PC of this instruction. */
> const Addr microPC() const { return pc.microPC(); }
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< Request *req = new Request(asid, addr, size, flags, this->PC,
---
> Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),
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< Request *req = new Request(asid, addr, size, flags, this->PC,
---
> Request *req = new Request(asid, addr, size, flags, this->pc.instAddr(),