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> #include "cpu/o3/comm.hh"
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< // Binary machine instruction type.
< typedef TheISA::MachInst MachInst;
< // Extended machine instruction type
< typedef TheISA::ExtMachInst ExtMachInst;
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> protected:
> /** Flattened register index of the destination registers of this
> * instruction.
> */
> TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
>
> /** Flattened register index of the source registers of this
> * instruction.
> */
> TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
>
> /** Physical register index of the destination registers of this
> * instruction.
> */
> PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
>
> /** Physical register index of the source registers of this
> * instruction.
> */
> PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
>
> /** Physical register index of the previous producers of the
> * architected destinations.
> */
> PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
>
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>
> /** Returns the physical register index of the i'th destination
> * register.
> */
> PhysRegIndex renamedDestRegIdx(int idx) const
> {
> return _destRegIdx[idx];
> }
>
> /** Returns the physical register index of the i'th source register. */
> PhysRegIndex renamedSrcRegIdx(int idx) const
> {
> return _srcRegIdx[idx];
> }
>
> /** Returns the flattened register index of the i'th destination
> * register.
> */
> TheISA::RegIndex flattenedDestRegIdx(int idx) const
> {
> return _flatDestRegIdx[idx];
> }
>
> /** Returns the flattened register index of the i'th source register */
> TheISA::RegIndex flattenedSrcRegIdx(int idx) const
> {
> return _flatSrcRegIdx[idx];
> }
>
> /** Returns the physical register index of the previous physical register
> * that remapped to the same logical register index.
> */
> PhysRegIndex prevDestRegIdx(int idx) const
> {
> return _prevDestRegIdx[idx];
> }
>
> /** Renames a destination register to a physical register. Also records
> * the previous physical register that the logical register mapped to.
> */
> void renameDestReg(int idx,
> PhysRegIndex renamed_dest,
> PhysRegIndex previous_rename)
> {
> _destRegIdx[idx] = renamed_dest;
> _prevDestRegIdx[idx] = previous_rename;
> }
>
> /** Renames a source logical register to the physical register which
> * has/will produce that logical register's result.
> * @todo: add in whether or not the source register is ready.
> */
> void renameSrcReg(int idx, PhysRegIndex renamed_src)
> {
> _srcRegIdx[idx] = renamed_src;
> }
>
> /** Flattens a source architectural register index into a logical index.
> */
> void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
> {
> _flatSrcRegIdx[idx] = flattened_src;
> }
>
> /** Flattens a destination architectural register index into a logical
> * index.
> */
> void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
> {
> _flatDestRegIdx[idx] = flattened_dest;
> }
>
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< BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
< ImplCPU *cpu);
---
> BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC,
> InstSeqNum seq_num, ImplCPU *cpu);
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< { return predPC != (nextPC + sizeof(MachInst)); }
---
> { return predPC != (nextPC + sizeof(TheISA::MachInst)); }
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< { return predPC != (PC + sizeof(MachInst)); }
---
> { return predPC != (PC + sizeof(TheISA::MachInst)); }
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< void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
---
> void setIntReg(const StaticInst *si, int idx, uint64_t val)
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< void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
< int width)
---
> void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
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< void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
---
> void setFloatReg(const StaticInst *si, int idx, FloatReg val)
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< void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
< int width)
---
> void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
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< void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
---
> void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)