26a27,28
> *
> * Authors: Kevin Lim
32d33
< #include <list>
33a35
> #include <vector>
39a42
> #include "cpu/o3/comm.hh"
41,44d43
< #include "encumbered/cpu/full/op_class.hh"
< #include "mem/functional/memory_control.hh"
< #include "sim/system.hh"
< /*
45a45
> #include "encumbered/cpu/full/op_class.hh"
49d48
< */
65d63
< typedef typename FullCPU::ImplState ImplState;
67c65
< // Binary machine instruction type.
---
> /// Binary machine instruction type.
69,71c67
< // Extended machine instruction type
< typedef TheISA::ExtMachInst ExtMachInst;
< // Logical register index type.
---
> /// Logical register index type.
73c69
< // Integer register index type.
---
> /// Integer register index type.
76,81d71
< // The DynInstPtr type.
< typedef typename Impl::DynInstPtr DynInstPtr;
<
< // The list of instructions iterator type.
< typedef typename std::list<DynInstPtr>::iterator ListIt;
<
83,84c73,74
< MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
< MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
---
> MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
> MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
87c77
< /** The StaticInst used by this BaseDynInst. */
---
> /** The static inst used by this dyn inst. */
95d84
< /** InstRecord that tracks this instructions. */
98,104d86
< /**
< * Does a read to a given address.
< * @param addr The address to read.
< * @param data The read's data is written into this parameter.
< * @param flags The request's flags.
< * @return Returns any fault due to the read.
< */
108,115d89
< /**
< * Does a write to a given address.
< * @param data The data to be written.
< * @param addr The address to write to.
< * @param flags The request's flags.
< * @param res The result of the write (for load locked/store conditionals).
< * @return Returns any fault due to the write.
< */
126a101,103
> /** Is this instruction valid. */
> bool valid;
>
130,131c107,108
< /** Is the instruction in the IQ */
< bool iqEntry;
---
> /** How many source registers are ready. */
> unsigned readyRegs;
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< /** Is the instruction in the ROB */
< bool robEntry;
<
< /** Is the instruction in the LSQ */
< bool lsqEntry;
<
142,144d112
< /** Is the instruction's result ready. */
< bool resultReady;
<
157,159d124
< /** Is this instruction committed. */
< bool committed;
<
166,171d130
< /** Is this instruction squashed in the instruction queue. */
< bool squashedInLSQ;
<
< /** Is this instruction squashed in the instruction queue. */
< bool squashedInROB;
<
187,189d145
< /** How many source registers are ready. */
< unsigned readyRegs;
<
193,194c149,150
< /** Pointer to the exec context. */
< ImplState *thread;
---
> /** Pointer to the exec context. Will not exist in the final version. */
> CPUExecContext *cpuXC;
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< /** The memory request. */
< MemReqPtr req;
<
249,254c202,203
< #ifdef DEBUG
< void dumpSNList();
< #endif
<
< /** Whether or not the source register is ready.
< * @todo: Not sure this should be here vs the derived class.
---
> /** Whether or not the source register is ready. Not sure this should be
> * here vs. the derived class.
259,266c208,209
< /** BaseDynInst constructor given a binary instruction.
< * @param inst The binary instruction.
< * @param PC The PC of the instruction.
< * @param pred_PC The predicted next PC.
< * @param seq_num The sequence number of the instruction.
< * @param cpu Pointer to the instruction's CPU.
< */
< BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
---
> /** BaseDynInst constructor given a binary instruction. */
> BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
269,271c212
< /** BaseDynInst constructor given a StaticInst pointer.
< * @param _staticInst The StaticInst for this BaseDynInst.
< */
---
> /** BaseDynInst constructor given a static inst pointer. */
282,289d222
< /**
< * @todo: Make this function work; currently it is a dummy function.
< * @param fault Last fault.
< * @param cmd Last command.
< * @param addr Virtual address of access.
< * @param p Memory accessed.
< * @param nbytes Access size.
< */
291,295c224,228
< trace_mem(Fault fault,
< MemCmd cmd,
< Addr addr,
< void *p,
< int nbytes);
---
> trace_mem(Fault fault, // last fault
> MemCmd cmd, // last command
> Addr addr, // virtual address of access
> void *p, // memory accessed
> int nbytes); // access size
309d241
< * @todo: Actually use this instruction.
325c257,259
< bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
---
> bool predTaken() {
> return( predPC != (PC + sizeof(MachInst) ) );
> }
328c262
< bool mispredicted() { return predPC != nextPC; }
---
> bool mispredicted() { return (predPC != nextPC); }
337,338d270
< bool isStoreConditional() const
< { return staticInst->isStoreConditional(); }
353,356d284
< bool isSerializeBefore() const
< { return staticInst->isSerializeBefore() || serializeBefore; }
< bool isSerializeAfter() const
< { return staticInst->isSerializeAfter() || serializeAfter; }
360,362d287
< bool isQuiesce() const { return staticInst->isQuiesce(); }
< bool isIprAccess() const { return staticInst->isIprAccess(); }
< bool isUnverifiable() const { return staticInst->isUnverifiable(); }
364,400d288
< /** Temporarily sets this instruction as a serialize before instruction. */
< void setSerializeBefore() { serializeBefore = true; }
<
< /** Clears the serializeBefore part of this instruction. */
< void clearSerializeBefore() { serializeBefore = false; }
<
< /** Checks if this serializeBefore is only temporarily set. */
< bool isTempSerializeBefore() { return serializeBefore; }
<
< /** Tracks if instruction has been externally set as serializeBefore. */
< bool serializeBefore;
<
< /** Temporarily sets this instruction as a serialize after instruction. */
< void setSerializeAfter() { serializeAfter = true; }
<
< /** Clears the serializeAfter part of this instruction.*/
< void clearSerializeAfter() { serializeAfter = false; }
<
< /** Checks if this serializeAfter is only temporarily set. */
< bool isTempSerializeAfter() { return serializeAfter; }
<
< /** Tracks if instruction has been externally set as serializeAfter. */
< bool serializeAfter;
<
< /** Checks if the serialization part of this instruction has been
< * handled. This does not apply to the temporary serializing
< * state; it only applies to this instruction's own permanent
< * serializing state.
< */
< bool isSerializeHandled() { return serializeHandled; }
<
< /** Sets the serialization part of this instruction as handled. */
< void setSerializeHandled() { serializeHandled = true; }
<
< /** Whether or not the serialization of this instruction has been handled. */
< bool serializeHandled;
<
407,408c295,296
< /** Returns the number of source registers. */
< int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
---
> /** Number of source registers. */
> int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
410c298
< /** Returns the number of destination registers. */
---
> /** Number of destination registers. */
419c307,310
< RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
---
> RegIndex destRegIdx(int i) const
> {
> return staticInst->destRegIdx(i);
> }
422c313,316
< RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
---
> RegIndex srcRegIdx(int i) const
> {
> return staticInst->srcRegIdx(i);
> }
433c327,329
< void setIntReg(const StaticInst *si, int idx, uint64_t val)
---
> //Push to .cc file.
> /** Records that one of the source registers is ready. */
> void markSrcRegReady()
435c331,334
< instResult.integer = val;
---
> ++readyRegs;
> if(readyRegs == numSrcRegs()) {
> canIssue = true;
> }
438c337,340
< void setFloatRegSingle(const StaticInst *si, int idx, float val)
---
> /** Marks a specific register as ready.
> * @todo: Move this to .cc file.
> */
> void markSrcRegReady(RegIndex src_idx)
440,441c342
< instResult.fp = val;
< }
---
> ++readyRegs;
443,446c344
< void setFloatRegDouble(const StaticInst *si, int idx, double val)
< {
< instResult.dbl = val;
< }
---
> _readySrcRegIdx[src_idx] = 1;
448,450c346,348
< void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
< {
< instResult.integer = val;
---
> if(readyRegs == numSrcRegs()) {
> canIssue = true;
> }
453,458d350
< /** Records that one of the source registers is ready. */
< void markSrcRegReady();
<
< /** Marks a specific register as ready. */
< void markSrcRegReady(RegIndex src_idx);
<
468c360
< /** Returns whether or not this instruction is completed. */
---
> /** Returns whethe or not this instruction is completed. */
471,474d362
< void setResultReady() { resultReady = true; }
<
< bool isResultReady() const { return resultReady; }
<
502,507d389
< /** Sets this instruction as committed. */
< void setCommitted() { committed = true; }
<
< /** Returns whether or not this instruction is committed. */
< bool isCommitted() const { return committed; }
<
514,521d395
< //Instruction Queue Entry
< //-----------------------
< /** Sets this instruction as a entry the IQ. */
< void setInIQ() { iqEntry = true; }
<
< /** Sets this instruction as a entry the IQ. */
< void removeInIQ() { iqEntry = false; }
<
523c397
< void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
---
> void setSquashedInIQ() { squashedInIQ = true; }
528,566d401
< /** Returns whether or not this instruction has issued. */
< bool isInIQ() const { return iqEntry; }
<
<
< //Load / Store Queue Functions
< //-----------------------
< /** Sets this instruction as a entry the LSQ. */
< void setInLSQ() { lsqEntry = true; }
<
< /** Sets this instruction as a entry the LSQ. */
< void removeInLSQ() { lsqEntry = false; }
<
< /** Sets this instruction as squashed in the LSQ. */
< void setSquashedInLSQ() { squashedInLSQ = true;}
<
< /** Returns whether or not this instruction is squashed in the LSQ. */
< bool isSquashedInLSQ() const { return squashedInLSQ; }
<
< /** Returns whether or not this instruction is in the LSQ. */
< bool isInLSQ() const { return lsqEntry; }
<
<
< //Reorder Buffer Functions
< //-----------------------
< /** Sets this instruction as a entry the ROB. */
< void setInROB() { robEntry = true; }
<
< /** Sets this instruction as a entry the ROB. */
< void removeInROB() { robEntry = false; }
<
< /** Sets this instruction as squashed in the ROB. */
< void setSquashedInROB() { squashedInROB = true; }
<
< /** Returns whether or not this instruction is squashed in the ROB. */
< bool isSquashedInROB() const { return squashedInROB; }
<
< /** Returns whether or not this instruction is in the ROB. */
< bool isInROB() const { return robEntry; }
<
571,575c406
< void setNextPC(uint64_t val)
< {
< nextPC = val;
< // instResult.integer = val;
< }
---
> void setNextPC(uint64_t val) { nextPC = val; }
577,582d407
< void setASID(short addr_space_id) { asid = addr_space_id; }
<
< void setThread(unsigned tid) { threadNumber = tid; }
<
< void setState(ImplState *state) { thread = state; }
<
586c411
< ExecContext *xcBase() { return thread->getXCProxy(); }
---
> ExecContext *xcBase() { return cpuXC->getProxy(); }
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<
604c428
< const Addr &getEA() const { return req->vaddr; }
---
> const Addr &getEA() const { return instEffAddr; }
612,614d435
< /** Whether or not the memory operation is done. */
< bool memOpDone;
<
621,631d441
<
< bool reachedCommit;
<
< /** Iterator pointing to this BaseDynInst in the list of all insts. */
< ListIt instListIt;
<
< /** Returns iterator to this instruction in the list of all insts. */
< ListIt &getInstListIt() { return instListIt; }
<
< /** Sets iterator for this instruction in the list of all insts. */
< void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
639,644c449
< if (executed) {
< fault = cpu->read(req, data, lqIdx);
< return fault;
< }
<
< req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
---
> MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
646,647d450
< req->thread_num = threadNumber;
< req->pc = this->PC;
649,653d451
< if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
< TheISA::VMPageSize) {
< return TheISA::genAlignmentFault();
< }
<
655a454,457
> // Record key MemReq parameters so we can generate another one
> // just like it for the timing access without calling translate()
> // again (which might mess up the TLB).
> // Do I ever really need this? -KTL 3/05
659a462,470
> /**
> * @todo
> * Replace the disjoint functional memory with a unified one and remove
> * this hack.
> */
> #if !FULL_SYSTEM
> req->paddr = req->vaddr;
> #endif
>
661,669d471
< #if FULL_SYSTEM
< if (cpu->system->memctrl->badaddr(physEffAddr)) {
< fault = TheISA::genMachineCheckFault();
< data = (T)-1;
< this->setExecuted();
< } else {
< fault = cpu->read(req, data, lqIdx);
< }
< #else
671d472
< #endif
676,679d476
<
< // Commit will have to clean up whatever happened. Set this
< // instruction as executed.
< this->setExecuted();
700c497
< req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
---
> MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
703,704d499
< req->thread_num = threadNumber;
< req->pc = this->PC;
706,710d500
< if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
< TheISA::VMPageSize) {
< return TheISA::genAlignmentFault();
< }
<
712a503,505
> // Record key MemReq parameters so we can generate another one
> // just like it for the timing access without calling translate()
> // again (which might mess up the TLB).
716a510,518
> /**
> * @todo
> * Replace the disjoint functional memory with a unified one and remove
> * this hack.
> */
> #if !FULL_SYSTEM
> req->paddr = req->vaddr;
> #endif
>
718,724d519
< #if FULL_SYSTEM
< if (cpu->system->memctrl->badaddr(physEffAddr)) {
< fault = TheISA::genMachineCheckFault();
< } else {
< fault = cpu->write(req, data, sqIdx);
< }
< #else
726d520
< #endif
> *
> * Authors: Kevin Lim
32d33
< #include <list>
33a35
> #include <vector>
39a42
> #include "cpu/o3/comm.hh"
41,44d43
< #include "encumbered/cpu/full/op_class.hh"
< #include "mem/functional/memory_control.hh"
< #include "sim/system.hh"
< /*
45a45
> #include "encumbered/cpu/full/op_class.hh"
49d48
< */
65d63
< typedef typename FullCPU::ImplState ImplState;
67c65
< // Binary machine instruction type.
---
> /// Binary machine instruction type.
69,71c67
< // Extended machine instruction type
< typedef TheISA::ExtMachInst ExtMachInst;
< // Logical register index type.
---
> /// Logical register index type.
73c69
< // Integer register index type.
---
> /// Integer register index type.
76,81d71
< // The DynInstPtr type.
< typedef typename Impl::DynInstPtr DynInstPtr;
<
< // The list of instructions iterator type.
< typedef typename std::list<DynInstPtr>::iterator ListIt;
<
83,84c73,74
< MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
< MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
---
> MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
> MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
87c77
< /** The StaticInst used by this BaseDynInst. */
---
> /** The static inst used by this dyn inst. */
95d84
< /** InstRecord that tracks this instructions. */
98,104d86
< /**
< * Does a read to a given address.
< * @param addr The address to read.
< * @param data The read's data is written into this parameter.
< * @param flags The request's flags.
< * @return Returns any fault due to the read.
< */
108,115d89
< /**
< * Does a write to a given address.
< * @param data The data to be written.
< * @param addr The address to write to.
< * @param flags The request's flags.
< * @param res The result of the write (for load locked/store conditionals).
< * @return Returns any fault due to the write.
< */
126a101,103
> /** Is this instruction valid. */
> bool valid;
>
130,131c107,108
< /** Is the instruction in the IQ */
< bool iqEntry;
---
> /** How many source registers are ready. */
> unsigned readyRegs;
133,138d109
< /** Is the instruction in the ROB */
< bool robEntry;
<
< /** Is the instruction in the LSQ */
< bool lsqEntry;
<
142,144d112
< /** Is the instruction's result ready. */
< bool resultReady;
<
157,159d124
< /** Is this instruction committed. */
< bool committed;
<
166,171d130
< /** Is this instruction squashed in the instruction queue. */
< bool squashedInLSQ;
<
< /** Is this instruction squashed in the instruction queue. */
< bool squashedInROB;
<
187,189d145
< /** How many source registers are ready. */
< unsigned readyRegs;
<
193,194c149,150
< /** Pointer to the exec context. */
< ImplState *thread;
---
> /** Pointer to the exec context. Will not exist in the final version. */
> CPUExecContext *cpuXC;
199,201d154
< /** The memory request. */
< MemReqPtr req;
<
249,254c202,203
< #ifdef DEBUG
< void dumpSNList();
< #endif
<
< /** Whether or not the source register is ready.
< * @todo: Not sure this should be here vs the derived class.
---
> /** Whether or not the source register is ready. Not sure this should be
> * here vs. the derived class.
259,266c208,209
< /** BaseDynInst constructor given a binary instruction.
< * @param inst The binary instruction.
< * @param PC The PC of the instruction.
< * @param pred_PC The predicted next PC.
< * @param seq_num The sequence number of the instruction.
< * @param cpu Pointer to the instruction's CPU.
< */
< BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
---
> /** BaseDynInst constructor given a binary instruction. */
> BaseDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
269,271c212
< /** BaseDynInst constructor given a StaticInst pointer.
< * @param _staticInst The StaticInst for this BaseDynInst.
< */
---
> /** BaseDynInst constructor given a static inst pointer. */
282,289d222
< /**
< * @todo: Make this function work; currently it is a dummy function.
< * @param fault Last fault.
< * @param cmd Last command.
< * @param addr Virtual address of access.
< * @param p Memory accessed.
< * @param nbytes Access size.
< */
291,295c224,228
< trace_mem(Fault fault,
< MemCmd cmd,
< Addr addr,
< void *p,
< int nbytes);
---
> trace_mem(Fault fault, // last fault
> MemCmd cmd, // last command
> Addr addr, // virtual address of access
> void *p, // memory accessed
> int nbytes); // access size
309d241
< * @todo: Actually use this instruction.
325c257,259
< bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
---
> bool predTaken() {
> return( predPC != (PC + sizeof(MachInst) ) );
> }
328c262
< bool mispredicted() { return predPC != nextPC; }
---
> bool mispredicted() { return (predPC != nextPC); }
337,338d270
< bool isStoreConditional() const
< { return staticInst->isStoreConditional(); }
353,356d284
< bool isSerializeBefore() const
< { return staticInst->isSerializeBefore() || serializeBefore; }
< bool isSerializeAfter() const
< { return staticInst->isSerializeAfter() || serializeAfter; }
360,362d287
< bool isQuiesce() const { return staticInst->isQuiesce(); }
< bool isIprAccess() const { return staticInst->isIprAccess(); }
< bool isUnverifiable() const { return staticInst->isUnverifiable(); }
364,400d288
< /** Temporarily sets this instruction as a serialize before instruction. */
< void setSerializeBefore() { serializeBefore = true; }
<
< /** Clears the serializeBefore part of this instruction. */
< void clearSerializeBefore() { serializeBefore = false; }
<
< /** Checks if this serializeBefore is only temporarily set. */
< bool isTempSerializeBefore() { return serializeBefore; }
<
< /** Tracks if instruction has been externally set as serializeBefore. */
< bool serializeBefore;
<
< /** Temporarily sets this instruction as a serialize after instruction. */
< void setSerializeAfter() { serializeAfter = true; }
<
< /** Clears the serializeAfter part of this instruction.*/
< void clearSerializeAfter() { serializeAfter = false; }
<
< /** Checks if this serializeAfter is only temporarily set. */
< bool isTempSerializeAfter() { return serializeAfter; }
<
< /** Tracks if instruction has been externally set as serializeAfter. */
< bool serializeAfter;
<
< /** Checks if the serialization part of this instruction has been
< * handled. This does not apply to the temporary serializing
< * state; it only applies to this instruction's own permanent
< * serializing state.
< */
< bool isSerializeHandled() { return serializeHandled; }
<
< /** Sets the serialization part of this instruction as handled. */
< void setSerializeHandled() { serializeHandled = true; }
<
< /** Whether or not the serialization of this instruction has been handled. */
< bool serializeHandled;
<
407,408c295,296
< /** Returns the number of source registers. */
< int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
---
> /** Number of source registers. */
> int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
410c298
< /** Returns the number of destination registers. */
---
> /** Number of destination registers. */
419c307,310
< RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
---
> RegIndex destRegIdx(int i) const
> {
> return staticInst->destRegIdx(i);
> }
422c313,316
< RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
---
> RegIndex srcRegIdx(int i) const
> {
> return staticInst->srcRegIdx(i);
> }
433c327,329
< void setIntReg(const StaticInst *si, int idx, uint64_t val)
---
> //Push to .cc file.
> /** Records that one of the source registers is ready. */
> void markSrcRegReady()
435c331,334
< instResult.integer = val;
---
> ++readyRegs;
> if(readyRegs == numSrcRegs()) {
> canIssue = true;
> }
438c337,340
< void setFloatRegSingle(const StaticInst *si, int idx, float val)
---
> /** Marks a specific register as ready.
> * @todo: Move this to .cc file.
> */
> void markSrcRegReady(RegIndex src_idx)
440,441c342
< instResult.fp = val;
< }
---
> ++readyRegs;
443,446c344
< void setFloatRegDouble(const StaticInst *si, int idx, double val)
< {
< instResult.dbl = val;
< }
---
> _readySrcRegIdx[src_idx] = 1;
448,450c346,348
< void setFloatRegInt(const StaticInst *si, int idx, uint64_t val)
< {
< instResult.integer = val;
---
> if(readyRegs == numSrcRegs()) {
> canIssue = true;
> }
453,458d350
< /** Records that one of the source registers is ready. */
< void markSrcRegReady();
<
< /** Marks a specific register as ready. */
< void markSrcRegReady(RegIndex src_idx);
<
468c360
< /** Returns whether or not this instruction is completed. */
---
> /** Returns whethe or not this instruction is completed. */
471,474d362
< void setResultReady() { resultReady = true; }
<
< bool isResultReady() const { return resultReady; }
<
502,507d389
< /** Sets this instruction as committed. */
< void setCommitted() { committed = true; }
<
< /** Returns whether or not this instruction is committed. */
< bool isCommitted() const { return committed; }
<
514,521d395
< //Instruction Queue Entry
< //-----------------------
< /** Sets this instruction as a entry the IQ. */
< void setInIQ() { iqEntry = true; }
<
< /** Sets this instruction as a entry the IQ. */
< void removeInIQ() { iqEntry = false; }
<
523c397
< void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
---
> void setSquashedInIQ() { squashedInIQ = true; }
528,566d401
< /** Returns whether or not this instruction has issued. */
< bool isInIQ() const { return iqEntry; }
<
<
< //Load / Store Queue Functions
< //-----------------------
< /** Sets this instruction as a entry the LSQ. */
< void setInLSQ() { lsqEntry = true; }
<
< /** Sets this instruction as a entry the LSQ. */
< void removeInLSQ() { lsqEntry = false; }
<
< /** Sets this instruction as squashed in the LSQ. */
< void setSquashedInLSQ() { squashedInLSQ = true;}
<
< /** Returns whether or not this instruction is squashed in the LSQ. */
< bool isSquashedInLSQ() const { return squashedInLSQ; }
<
< /** Returns whether or not this instruction is in the LSQ. */
< bool isInLSQ() const { return lsqEntry; }
<
<
< //Reorder Buffer Functions
< //-----------------------
< /** Sets this instruction as a entry the ROB. */
< void setInROB() { robEntry = true; }
<
< /** Sets this instruction as a entry the ROB. */
< void removeInROB() { robEntry = false; }
<
< /** Sets this instruction as squashed in the ROB. */
< void setSquashedInROB() { squashedInROB = true; }
<
< /** Returns whether or not this instruction is squashed in the ROB. */
< bool isSquashedInROB() const { return squashedInROB; }
<
< /** Returns whether or not this instruction is in the ROB. */
< bool isInROB() const { return robEntry; }
<
571,575c406
< void setNextPC(uint64_t val)
< {
< nextPC = val;
< // instResult.integer = val;
< }
---
> void setNextPC(uint64_t val) { nextPC = val; }
577,582d407
< void setASID(short addr_space_id) { asid = addr_space_id; }
<
< void setThread(unsigned tid) { threadNumber = tid; }
<
< void setState(ImplState *state) { thread = state; }
<
586c411
< ExecContext *xcBase() { return thread->getXCProxy(); }
---
> ExecContext *xcBase() { return cpuXC->getProxy(); }
593d417
<
604c428
< const Addr &getEA() const { return req->vaddr; }
---
> const Addr &getEA() const { return instEffAddr; }
612,614d435
< /** Whether or not the memory operation is done. */
< bool memOpDone;
<
621,631d441
<
< bool reachedCommit;
<
< /** Iterator pointing to this BaseDynInst in the list of all insts. */
< ListIt instListIt;
<
< /** Returns iterator to this instruction in the list of all insts. */
< ListIt &getInstListIt() { return instListIt; }
<
< /** Sets iterator for this instruction in the list of all insts. */
< void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
639,644c449
< if (executed) {
< fault = cpu->read(req, data, lqIdx);
< return fault;
< }
<
< req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
---
> MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
646,647d450
< req->thread_num = threadNumber;
< req->pc = this->PC;
649,653d451
< if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
< TheISA::VMPageSize) {
< return TheISA::genAlignmentFault();
< }
<
655a454,457
> // Record key MemReq parameters so we can generate another one
> // just like it for the timing access without calling translate()
> // again (which might mess up the TLB).
> // Do I ever really need this? -KTL 3/05
659a462,470
> /**
> * @todo
> * Replace the disjoint functional memory with a unified one and remove
> * this hack.
> */
> #if !FULL_SYSTEM
> req->paddr = req->vaddr;
> #endif
>
661,669d471
< #if FULL_SYSTEM
< if (cpu->system->memctrl->badaddr(physEffAddr)) {
< fault = TheISA::genMachineCheckFault();
< data = (T)-1;
< this->setExecuted();
< } else {
< fault = cpu->read(req, data, lqIdx);
< }
< #else
671d472
< #endif
676,679d476
<
< // Commit will have to clean up whatever happened. Set this
< // instruction as executed.
< this->setExecuted();
700c497
< req = new MemReq(addr, thread->getXCProxy(), sizeof(T), flags);
---
> MemReqPtr req = new MemReq(addr, cpuXC->getProxy(), sizeof(T), flags);
703,704d499
< req->thread_num = threadNumber;
< req->pc = this->PC;
706,710d500
< if ((req->vaddr & (TheISA::VMPageSize - 1)) + req->size >
< TheISA::VMPageSize) {
< return TheISA::genAlignmentFault();
< }
<
712a503,505
> // Record key MemReq parameters so we can generate another one
> // just like it for the timing access without calling translate()
> // again (which might mess up the TLB).
716a510,518
> /**
> * @todo
> * Replace the disjoint functional memory with a unified one and remove
> * this hack.
> */
> #if !FULL_SYSTEM
> req->paddr = req->vaddr;
> #endif
>
718,724d519
< #if FULL_SYSTEM
< if (cpu->system->memctrl->badaddr(physEffAddr)) {
< fault = TheISA::genMachineCheckFault();
< } else {
< fault = cpu->write(req, data, sqIdx);
< }
< #else
726d520
< #endif