3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Timothy M. Jones
43 */
44
45#ifndef __CPU_BASE_DYN_INST_HH__
46#define __CPU_BASE_DYN_INST_HH__
47
48#include <bitset>
49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/trace.hh"
55#include "config/the_isa.hh"
56#include "cpu/checker/cpu.hh"
57#include "cpu/o3/comm.hh"
58#include "cpu/exetrace.hh"
59#include "cpu/inst_seq.hh"
60#include "cpu/op_class.hh"
61#include "cpu/static_inst.hh"
62#include "cpu/translation.hh"
63#include "mem/packet.hh"
64#include "sim/byteswap.hh"
65#include "sim/fault_fwd.hh"
66#include "sim/system.hh"
67#include "sim/tlb.hh"
68
69/**
70 * @file
71 * Defines a dynamic instruction context.
72 */
73
74template <class Impl>
75class BaseDynInst : public RefCounted
76{
77 public:
78 // Typedef for the CPU.
79 typedef typename Impl::CPUType ImplCPU;
80 typedef typename ImplCPU::ImplState ImplState;
81
82 // Logical register index type.
83 typedef TheISA::RegIndex RegIndex;
84 // Integer register type.
85 typedef TheISA::IntReg IntReg;
86 // Floating point register type.
87 typedef TheISA::FloatReg FloatReg;
88
89 // The DynInstPtr type.
90 typedef typename Impl::DynInstPtr DynInstPtr;
91 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
92
93 // The list of instructions iterator type.
94 typedef typename std::list<DynInstPtr>::iterator ListIt;
95
96 enum {
97 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
98 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
99 };
100
101 union Result {
102 uint64_t integer;
103 double dbl;
104 void set(uint64_t i) { integer = i; }
105 void set(double d) { dbl = d; }
106 void get(uint64_t& i) { i = integer; }
107 void get(double& d) { d = dbl; }
108 };
109
110 protected:
111 enum Status {
112 IqEntry, /// Instruction is in the IQ
113 RobEntry, /// Instruction is in the ROB
114 LsqEntry, /// Instruction is in the LSQ
115 Completed, /// Instruction has completed
116 ResultReady, /// Instruction has its result
117 CanIssue, /// Instruction can issue and execute
118 Issued, /// Instruction has issued
119 Executed, /// Instruction has executed
120 CanCommit, /// Instruction can commit
121 AtCommit, /// Instruction has reached commit
122 Committed, /// Instruction has committed
123 Squashed, /// Instruction is squashed
124 SquashedInIQ, /// Instruction is squashed in the IQ
125 SquashedInLSQ, /// Instruction is squashed in the LSQ
126 SquashedInROB, /// Instruction is squashed in the ROB
127 RecoverInst, /// Is a recover instruction
128 BlockingInst, /// Is a blocking instruction
129 ThreadsyncWait, /// Is a thread synchronization instruction
130 SerializeBefore, /// Needs to serialize on
131 /// instructions ahead of it
132 SerializeAfter, /// Needs to serialize instructions behind it
133 SerializeHandled, /// Serialization has been handled
134 NumStatus
135 };
136
137 enum Flags {
138 TranslationStarted,
139 TranslationCompleted,
140 PossibleLoadViolation,
141 HitExternalSnoop,
142 EffAddrValid,
143 RecordResult,
144 Predicate,
145 PredTaken,
146 /** Whether or not the effective address calculation is completed.
147 * @todo: Consider if this is necessary or not.
148 */
149 EACalcDone,
150 IsUncacheable,
151 ReqMade,
152 MemOpDone,
153 MaxFlags
154 };
155
156 public:
157 /** The sequence number of the instruction. */
158 InstSeqNum seqNum;
159
160 /** The StaticInst used by this BaseDynInst. */
161 StaticInstPtr staticInst;
162
163 /** Pointer to the Impl's CPU object. */
164 ImplCPU *cpu;
165
166 /** Pointer to the thread state. */
167 ImplState *thread;
168
169 /** The kind of fault this instruction has generated. */
170 Fault fault;
171
172 /** InstRecord that tracks this instructions. */
173 Trace::InstRecord *traceData;
174
175 protected:
176 /** The result of the instruction; assumes an instruction can have many
177 * destination registers.
178 */
179 std::queue<Result> instResult;
180
181 /** PC state for this instruction. */
182 TheISA::PCState pc;
183
184 /* An amalgamation of a lot of boolean values into one */
185 std::bitset<MaxFlags> instFlags;
186
187 /** The status of this BaseDynInst. Several bits can be set. */
188 std::bitset<NumStatus> status;
189
190 /** Whether or not the source register is ready.
191 * @todo: Not sure this should be here vs the derived class.
192 */
193 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
194
195 public:
196 /** The thread this instruction is from. */
197 ThreadID threadNumber;
198
199 /** Iterator pointing to this BaseDynInst in the list of all insts. */
200 ListIt instListIt;
201
202 ////////////////////// Branch Data ///////////////
203 /** Predicted PC state after this instruction. */
204 TheISA::PCState predPC;
205
206 /** The Macroop if one exists */
207 StaticInstPtr macroop;
208
209 /** How many source registers are ready. */
210 uint8_t readyRegs;
211
212 public:
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
215 Addr effAddr;
216
217 /** The effective physical address. */
218 Addr physEffAddr;
219
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
222
223 /** data address space ID, for loads & stores. */
224 short asid;
225
226 /** The size of the request */
227 uint8_t effSize;
228
229 /** Pointer to the data for the memory access. */
230 uint8_t *memData;
231
232 /** Load queue index. */
233 int16_t lqIdx;
234
235 /** Store queue index. */
236 int16_t sqIdx;
237
238
239 /////////////////////// TLB Miss //////////////////////
240 /**
241 * Saved memory requests (needed when the DTB address translation is
242 * delayed due to a hw page table walk).
243 */
244 RequestPtr savedReq;
245 RequestPtr savedSreqLow;
246 RequestPtr savedSreqHigh;
247
248 /////////////////////// Checker //////////////////////
249 // Need a copy of main request pointer to verify on writes.
250 RequestPtr reqToVerify;
251
252 private:
253 /** Instruction effective address.
254 * @todo: Consider if this is necessary or not.
255 */
256 Addr instEffAddr;
257
258 protected:
259 /** Flattened register index of the destination registers of this
260 * instruction.
261 */
262 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
263
264 /** Physical register index of the destination registers of this
265 * instruction.
266 */
267 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
268
269 /** Physical register index of the source registers of this
270 * instruction.
271 */
272 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
273
274 /** Physical register index of the previous producers of the
275 * architected destinations.
276 */
277 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
278
279
280 public:
281 /** Records changes to result? */
282 void recordResult(bool f) { instFlags[RecordResult] = f; }
283
284 /** Is the effective virtual address valid. */
285 bool effAddrValid() const { return instFlags[EffAddrValid]; }
286
287 /** Whether or not the memory operation is done. */
288 bool memOpDone() const { return instFlags[MemOpDone]; }
289 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
290
291
292 ////////////////////////////////////////////
293 //
294 // INSTRUCTION EXECUTION
295 //
296 ////////////////////////////////////////////
297
298 void demapPage(Addr vaddr, uint64_t asn)
299 {
300 cpu->demapPage(vaddr, asn);
301 }
302 void demapInstPage(Addr vaddr, uint64_t asn)
303 {
304 cpu->demapPage(vaddr, asn);
305 }
306 void demapDataPage(Addr vaddr, uint64_t asn)
307 {
308 cpu->demapPage(vaddr, asn);
309 }
310
311 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
312
313 Fault writeMem(uint8_t *data, unsigned size,
314 Addr addr, unsigned flags, uint64_t *res);
315
316 /** Splits a request in two if it crosses a dcache block. */
317 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
318 RequestPtr &sreqHigh);
319
320 /** Initiate a DTB address translation. */
321 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
322 RequestPtr sreqHigh, uint64_t *res,
323 BaseTLB::Mode mode);
324
325 /** Finish a DTB address translation. */
326 void finishTranslation(WholeTranslationState *state);
327
328 /** True if the DTB address translation has started. */
329 bool translationStarted() const { return instFlags[TranslationStarted]; }
330 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
331
332 /** True if the DTB address translation has completed. */
333 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
334 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
335
336 /** True if this address was found to match a previous load and they issued
337 * out of order. If that happend, then it's only a problem if an incoming
338 * snoop invalidate modifies the line, in which case we need to squash.
339 * If nothing modified the line the order doesn't matter.
340 */
341 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
342 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
343
344 /** True if the address hit a external snoop while sitting in the LSQ.
345 * If this is true and a older instruction sees it, this instruction must
346 * reexecute
347 */
348 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
349 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
350
351 /**
352 * Returns true if the DTB address translation is being delayed due to a hw
353 * page table walk.
354 */
355 bool isTranslationDelayed() const
356 {
357 return (translationStarted() && !translationCompleted());
358 }
359
360 public:
361#ifdef DEBUG
362 void dumpSNList();
363#endif
364
365 /** Returns the physical register index of the i'th destination
366 * register.
367 */
368 PhysRegIndex renamedDestRegIdx(int idx) const
369 {
370 return _destRegIdx[idx];
371 }
372
373 /** Returns the physical register index of the i'th source register. */
374 PhysRegIndex renamedSrcRegIdx(int idx) const
375 {
376 assert(TheISA::MaxInstSrcRegs > idx);
377 return _srcRegIdx[idx];
378 }
379
380 /** Returns the flattened register index of the i'th destination
381 * register.
382 */
383 TheISA::RegIndex flattenedDestRegIdx(int idx) const
384 {
385 return _flatDestRegIdx[idx];
386 }
387
388 /** Returns the physical register index of the previous physical register
389 * that remapped to the same logical register index.
390 */
391 PhysRegIndex prevDestRegIdx(int idx) const
392 {
393 return _prevDestRegIdx[idx];
394 }
395
396 /** Renames a destination register to a physical register. Also records
397 * the previous physical register that the logical register mapped to.
398 */
399 void renameDestReg(int idx,
400 PhysRegIndex renamed_dest,
401 PhysRegIndex previous_rename)
402 {
403 _destRegIdx[idx] = renamed_dest;
404 _prevDestRegIdx[idx] = previous_rename;
405 }
406
407 /** Renames a source logical register to the physical register which
408 * has/will produce that logical register's result.
409 * @todo: add in whether or not the source register is ready.
410 */
411 void renameSrcReg(int idx, PhysRegIndex renamed_src)
412 {
413 _srcRegIdx[idx] = renamed_src;
414 }
415
416 /** Flattens a destination architectural register index into a logical
417 * index.
418 */
419 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
420 {
421 _flatDestRegIdx[idx] = flattened_dest;
422 }
423 /** BaseDynInst constructor given a binary instruction.
424 * @param staticInst A StaticInstPtr to the underlying instruction.
425 * @param pc The PC state for the instruction.
426 * @param predPC The predicted next PC state for the instruction.
427 * @param seq_num The sequence number of the instruction.
428 * @param cpu Pointer to the instruction's CPU.
429 */
430 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
431 TheISA::PCState pc, TheISA::PCState predPC,
432 InstSeqNum seq_num, ImplCPU *cpu);
433
434 /** BaseDynInst constructor given a StaticInst pointer.
435 * @param _staticInst The StaticInst for this BaseDynInst.
436 */
437 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
438
439 /** BaseDynInst destructor. */
440 ~BaseDynInst();
441
442 private:
443 /** Function to initialize variables in the constructors. */
444 void initVars();
445
446 public:
447 /** Dumps out contents of this BaseDynInst. */
448 void dump();
449
450 /** Dumps out contents of this BaseDynInst into given string. */
451 void dump(std::string &outstring);
452
453 /** Read this CPU's ID. */
454 int cpuId() { return cpu->cpuId(); }
455
456 /** Read this CPU's data requestor ID */
457 MasterID masterId() { return cpu->dataMasterId(); }
458
459 /** Read this context's system-wide ID **/
460 int contextId() { return thread->contextId(); }
461
462 /** Returns the fault type. */
463 Fault getFault() { return fault; }
464
465 /** Checks whether or not this instruction has had its branch target
466 * calculated yet. For now it is not utilized and is hacked to be
467 * always false.
468 * @todo: Actually use this instruction.
469 */
470 bool doneTargCalc() { return false; }
471
472 /** Set the predicted target of this current instruction. */
473 void setPredTarg(const TheISA::PCState &_predPC)
474 {
475 predPC = _predPC;
476 }
477
478 const TheISA::PCState &readPredTarg() { return predPC; }
479
480 /** Returns the predicted PC immediately after the branch. */
481 Addr predInstAddr() { return predPC.instAddr(); }
482
483 /** Returns the predicted PC two instructions after the branch */
484 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
485
486 /** Returns the predicted micro PC after the branch */
487 Addr predMicroPC() { return predPC.microPC(); }
488
489 /** Returns whether the instruction was predicted taken or not. */
490 bool readPredTaken()
491 {
492 return instFlags[PredTaken];
493 }
494
495 void setPredTaken(bool predicted_taken)
496 {
497 instFlags[PredTaken] = predicted_taken;
498 }
499
500 /** Returns whether the instruction mispredicted. */
501 bool mispredicted()
502 {
503 TheISA::PCState tempPC = pc;
504 TheISA::advancePC(tempPC, staticInst);
505 return !(tempPC == predPC);
506 }
507
508 //
509 // Instruction types. Forward checks to StaticInst object.
510 //
511 bool isNop() const { return staticInst->isNop(); }
512 bool isMemRef() const { return staticInst->isMemRef(); }
513 bool isLoad() const { return staticInst->isLoad(); }
514 bool isStore() const { return staticInst->isStore(); }
515 bool isStoreConditional() const
516 { return staticInst->isStoreConditional(); }
517 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
518 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
519 bool isInteger() const { return staticInst->isInteger(); }
520 bool isFloating() const { return staticInst->isFloating(); }
521 bool isControl() const { return staticInst->isControl(); }
522 bool isCall() const { return staticInst->isCall(); }
523 bool isReturn() const { return staticInst->isReturn(); }
524 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
525 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
526 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
527 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
528 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
529 bool isThreadSync() const { return staticInst->isThreadSync(); }
530 bool isSerializing() const { return staticInst->isSerializing(); }
531 bool isSerializeBefore() const
532 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
533 bool isSerializeAfter() const
534 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
535 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
536 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
537 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
538 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
539 bool isQuiesce() const { return staticInst->isQuiesce(); }
540 bool isIprAccess() const { return staticInst->isIprAccess(); }
541 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
542 bool isSyscall() const { return staticInst->isSyscall(); }
543 bool isMacroop() const { return staticInst->isMacroop(); }
544 bool isMicroop() const { return staticInst->isMicroop(); }
545 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
546 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
547 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
548 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
549
550 /** Temporarily sets this instruction as a serialize before instruction. */
551 void setSerializeBefore() { status.set(SerializeBefore); }
552
553 /** Clears the serializeBefore part of this instruction. */
554 void clearSerializeBefore() { status.reset(SerializeBefore); }
555
556 /** Checks if this serializeBefore is only temporarily set. */
557 bool isTempSerializeBefore() { return status[SerializeBefore]; }
558
559 /** Temporarily sets this instruction as a serialize after instruction. */
560 void setSerializeAfter() { status.set(SerializeAfter); }
561
562 /** Clears the serializeAfter part of this instruction.*/
563 void clearSerializeAfter() { status.reset(SerializeAfter); }
564
565 /** Checks if this serializeAfter is only temporarily set. */
566 bool isTempSerializeAfter() { return status[SerializeAfter]; }
567
568 /** Sets the serialization part of this instruction as handled. */
569 void setSerializeHandled() { status.set(SerializeHandled); }
570
571 /** Checks if the serialization part of this instruction has been
572 * handled. This does not apply to the temporary serializing
573 * state; it only applies to this instruction's own permanent
574 * serializing state.
575 */
576 bool isSerializeHandled() { return status[SerializeHandled]; }
577
578 /** Returns the opclass of this instruction. */
579 OpClass opClass() const { return staticInst->opClass(); }
580
581 /** Returns the branch target address. */
582 TheISA::PCState branchTarget() const
583 { return staticInst->branchTarget(pc); }
584
585 /** Returns the number of source registers. */
586 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
587
588 /** Returns the number of destination registers. */
589 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
590
591 // the following are used to track physical register usage
592 // for machines with separate int & FP reg files
593 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
594 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
595
596 /** Returns the logical register index of the i'th destination register. */
597 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
598
599 /** Returns the logical register index of the i'th source register. */
600 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
601
602 /** Pops a result off the instResult queue */
603 template <class T>
604 void popResult(T& t)
605 {
606 if (!instResult.empty()) {
607 instResult.front().get(t);
608 instResult.pop();
609 }
610 }
611
612 /** Read the most recent result stored by this instruction */
613 template <class T>
614 void readResult(T& t)
615 {
616 instResult.back().get(t);
617 }
618
619 /** Pushes a result onto the instResult queue */
620 template <class T>
621 void setResult(T t)
622 {
623 if (instFlags[RecordResult]) {
624 Result instRes;
625 instRes.set(t);
626 instResult.push(instRes);
627 }
628 }
629
630 /** Records an integer register being set to a value. */
631 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
632 {
633 setResult<uint64_t>(val);
634 }
635
| 4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 union Result {
103 uint64_t integer;
104 double dbl;
105 void set(uint64_t i) { integer = i; }
106 void set(double d) { dbl = d; }
107 void get(uint64_t& i) { i = integer; }
108 void get(double& d) { d = dbl; }
109 };
110
111 protected:
112 enum Status {
113 IqEntry, /// Instruction is in the IQ
114 RobEntry, /// Instruction is in the ROB
115 LsqEntry, /// Instruction is in the LSQ
116 Completed, /// Instruction has completed
117 ResultReady, /// Instruction has its result
118 CanIssue, /// Instruction can issue and execute
119 Issued, /// Instruction has issued
120 Executed, /// Instruction has executed
121 CanCommit, /// Instruction can commit
122 AtCommit, /// Instruction has reached commit
123 Committed, /// Instruction has committed
124 Squashed, /// Instruction is squashed
125 SquashedInIQ, /// Instruction is squashed in the IQ
126 SquashedInLSQ, /// Instruction is squashed in the LSQ
127 SquashedInROB, /// Instruction is squashed in the ROB
128 RecoverInst, /// Is a recover instruction
129 BlockingInst, /// Is a blocking instruction
130 ThreadsyncWait, /// Is a thread synchronization instruction
131 SerializeBefore, /// Needs to serialize on
132 /// instructions ahead of it
133 SerializeAfter, /// Needs to serialize instructions behind it
134 SerializeHandled, /// Serialization has been handled
135 NumStatus
136 };
137
138 enum Flags {
139 TranslationStarted,
140 TranslationCompleted,
141 PossibleLoadViolation,
142 HitExternalSnoop,
143 EffAddrValid,
144 RecordResult,
145 Predicate,
146 PredTaken,
147 /** Whether or not the effective address calculation is completed.
148 * @todo: Consider if this is necessary or not.
149 */
150 EACalcDone,
151 IsUncacheable,
152 ReqMade,
153 MemOpDone,
154 MaxFlags
155 };
156
157 public:
158 /** The sequence number of the instruction. */
159 InstSeqNum seqNum;
160
161 /** The StaticInst used by this BaseDynInst. */
162 StaticInstPtr staticInst;
163
164 /** Pointer to the Impl's CPU object. */
165 ImplCPU *cpu;
166
167 /** Pointer to the thread state. */
168 ImplState *thread;
169
170 /** The kind of fault this instruction has generated. */
171 Fault fault;
172
173 /** InstRecord that tracks this instructions. */
174 Trace::InstRecord *traceData;
175
176 protected:
177 /** The result of the instruction; assumes an instruction can have many
178 * destination registers.
179 */
180 std::queue<Result> instResult;
181
182 /** PC state for this instruction. */
183 TheISA::PCState pc;
184
185 /* An amalgamation of a lot of boolean values into one */
186 std::bitset<MaxFlags> instFlags;
187
188 /** The status of this BaseDynInst. Several bits can be set. */
189 std::bitset<NumStatus> status;
190
191 /** Whether or not the source register is ready.
192 * @todo: Not sure this should be here vs the derived class.
193 */
194 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
195
196 public:
197 /** The thread this instruction is from. */
198 ThreadID threadNumber;
199
200 /** Iterator pointing to this BaseDynInst in the list of all insts. */
201 ListIt instListIt;
202
203 ////////////////////// Branch Data ///////////////
204 /** Predicted PC state after this instruction. */
205 TheISA::PCState predPC;
206
207 /** The Macroop if one exists */
208 StaticInstPtr macroop;
209
210 /** How many source registers are ready. */
211 uint8_t readyRegs;
212
213 public:
214 /////////////////////// Load Store Data //////////////////////
215 /** The effective virtual address (lds & stores only). */
216 Addr effAddr;
217
218 /** The effective physical address. */
219 Addr physEffAddr;
220
221 /** The memory request flags (from translation). */
222 unsigned memReqFlags;
223
224 /** data address space ID, for loads & stores. */
225 short asid;
226
227 /** The size of the request */
228 uint8_t effSize;
229
230 /** Pointer to the data for the memory access. */
231 uint8_t *memData;
232
233 /** Load queue index. */
234 int16_t lqIdx;
235
236 /** Store queue index. */
237 int16_t sqIdx;
238
239
240 /////////////////////// TLB Miss //////////////////////
241 /**
242 * Saved memory requests (needed when the DTB address translation is
243 * delayed due to a hw page table walk).
244 */
245 RequestPtr savedReq;
246 RequestPtr savedSreqLow;
247 RequestPtr savedSreqHigh;
248
249 /////////////////////// Checker //////////////////////
250 // Need a copy of main request pointer to verify on writes.
251 RequestPtr reqToVerify;
252
253 private:
254 /** Instruction effective address.
255 * @todo: Consider if this is necessary or not.
256 */
257 Addr instEffAddr;
258
259 protected:
260 /** Flattened register index of the destination registers of this
261 * instruction.
262 */
263 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
264
265 /** Physical register index of the destination registers of this
266 * instruction.
267 */
268 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
269
270 /** Physical register index of the source registers of this
271 * instruction.
272 */
273 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
274
275 /** Physical register index of the previous producers of the
276 * architected destinations.
277 */
278 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
279
280
281 public:
282 /** Records changes to result? */
283 void recordResult(bool f) { instFlags[RecordResult] = f; }
284
285 /** Is the effective virtual address valid. */
286 bool effAddrValid() const { return instFlags[EffAddrValid]; }
287
288 /** Whether or not the memory operation is done. */
289 bool memOpDone() const { return instFlags[MemOpDone]; }
290 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
291
292
293 ////////////////////////////////////////////
294 //
295 // INSTRUCTION EXECUTION
296 //
297 ////////////////////////////////////////////
298
299 void demapPage(Addr vaddr, uint64_t asn)
300 {
301 cpu->demapPage(vaddr, asn);
302 }
303 void demapInstPage(Addr vaddr, uint64_t asn)
304 {
305 cpu->demapPage(vaddr, asn);
306 }
307 void demapDataPage(Addr vaddr, uint64_t asn)
308 {
309 cpu->demapPage(vaddr, asn);
310 }
311
312 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
313
314 Fault writeMem(uint8_t *data, unsigned size,
315 Addr addr, unsigned flags, uint64_t *res);
316
317 /** Splits a request in two if it crosses a dcache block. */
318 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
319 RequestPtr &sreqHigh);
320
321 /** Initiate a DTB address translation. */
322 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
323 RequestPtr sreqHigh, uint64_t *res,
324 BaseTLB::Mode mode);
325
326 /** Finish a DTB address translation. */
327 void finishTranslation(WholeTranslationState *state);
328
329 /** True if the DTB address translation has started. */
330 bool translationStarted() const { return instFlags[TranslationStarted]; }
331 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
332
333 /** True if the DTB address translation has completed. */
334 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
335 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
336
337 /** True if this address was found to match a previous load and they issued
338 * out of order. If that happend, then it's only a problem if an incoming
339 * snoop invalidate modifies the line, in which case we need to squash.
340 * If nothing modified the line the order doesn't matter.
341 */
342 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
343 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
344
345 /** True if the address hit a external snoop while sitting in the LSQ.
346 * If this is true and a older instruction sees it, this instruction must
347 * reexecute
348 */
349 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
350 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
351
352 /**
353 * Returns true if the DTB address translation is being delayed due to a hw
354 * page table walk.
355 */
356 bool isTranslationDelayed() const
357 {
358 return (translationStarted() && !translationCompleted());
359 }
360
361 public:
362#ifdef DEBUG
363 void dumpSNList();
364#endif
365
366 /** Returns the physical register index of the i'th destination
367 * register.
368 */
369 PhysRegIndex renamedDestRegIdx(int idx) const
370 {
371 return _destRegIdx[idx];
372 }
373
374 /** Returns the physical register index of the i'th source register. */
375 PhysRegIndex renamedSrcRegIdx(int idx) const
376 {
377 assert(TheISA::MaxInstSrcRegs > idx);
378 return _srcRegIdx[idx];
379 }
380
381 /** Returns the flattened register index of the i'th destination
382 * register.
383 */
384 TheISA::RegIndex flattenedDestRegIdx(int idx) const
385 {
386 return _flatDestRegIdx[idx];
387 }
388
389 /** Returns the physical register index of the previous physical register
390 * that remapped to the same logical register index.
391 */
392 PhysRegIndex prevDestRegIdx(int idx) const
393 {
394 return _prevDestRegIdx[idx];
395 }
396
397 /** Renames a destination register to a physical register. Also records
398 * the previous physical register that the logical register mapped to.
399 */
400 void renameDestReg(int idx,
401 PhysRegIndex renamed_dest,
402 PhysRegIndex previous_rename)
403 {
404 _destRegIdx[idx] = renamed_dest;
405 _prevDestRegIdx[idx] = previous_rename;
406 }
407
408 /** Renames a source logical register to the physical register which
409 * has/will produce that logical register's result.
410 * @todo: add in whether or not the source register is ready.
411 */
412 void renameSrcReg(int idx, PhysRegIndex renamed_src)
413 {
414 _srcRegIdx[idx] = renamed_src;
415 }
416
417 /** Flattens a destination architectural register index into a logical
418 * index.
419 */
420 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
421 {
422 _flatDestRegIdx[idx] = flattened_dest;
423 }
424 /** BaseDynInst constructor given a binary instruction.
425 * @param staticInst A StaticInstPtr to the underlying instruction.
426 * @param pc The PC state for the instruction.
427 * @param predPC The predicted next PC state for the instruction.
428 * @param seq_num The sequence number of the instruction.
429 * @param cpu Pointer to the instruction's CPU.
430 */
431 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
432 TheISA::PCState pc, TheISA::PCState predPC,
433 InstSeqNum seq_num, ImplCPU *cpu);
434
435 /** BaseDynInst constructor given a StaticInst pointer.
436 * @param _staticInst The StaticInst for this BaseDynInst.
437 */
438 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
439
440 /** BaseDynInst destructor. */
441 ~BaseDynInst();
442
443 private:
444 /** Function to initialize variables in the constructors. */
445 void initVars();
446
447 public:
448 /** Dumps out contents of this BaseDynInst. */
449 void dump();
450
451 /** Dumps out contents of this BaseDynInst into given string. */
452 void dump(std::string &outstring);
453
454 /** Read this CPU's ID. */
455 int cpuId() { return cpu->cpuId(); }
456
457 /** Read this CPU's data requestor ID */
458 MasterID masterId() { return cpu->dataMasterId(); }
459
460 /** Read this context's system-wide ID **/
461 int contextId() { return thread->contextId(); }
462
463 /** Returns the fault type. */
464 Fault getFault() { return fault; }
465
466 /** Checks whether or not this instruction has had its branch target
467 * calculated yet. For now it is not utilized and is hacked to be
468 * always false.
469 * @todo: Actually use this instruction.
470 */
471 bool doneTargCalc() { return false; }
472
473 /** Set the predicted target of this current instruction. */
474 void setPredTarg(const TheISA::PCState &_predPC)
475 {
476 predPC = _predPC;
477 }
478
479 const TheISA::PCState &readPredTarg() { return predPC; }
480
481 /** Returns the predicted PC immediately after the branch. */
482 Addr predInstAddr() { return predPC.instAddr(); }
483
484 /** Returns the predicted PC two instructions after the branch */
485 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
486
487 /** Returns the predicted micro PC after the branch */
488 Addr predMicroPC() { return predPC.microPC(); }
489
490 /** Returns whether the instruction was predicted taken or not. */
491 bool readPredTaken()
492 {
493 return instFlags[PredTaken];
494 }
495
496 void setPredTaken(bool predicted_taken)
497 {
498 instFlags[PredTaken] = predicted_taken;
499 }
500
501 /** Returns whether the instruction mispredicted. */
502 bool mispredicted()
503 {
504 TheISA::PCState tempPC = pc;
505 TheISA::advancePC(tempPC, staticInst);
506 return !(tempPC == predPC);
507 }
508
509 //
510 // Instruction types. Forward checks to StaticInst object.
511 //
512 bool isNop() const { return staticInst->isNop(); }
513 bool isMemRef() const { return staticInst->isMemRef(); }
514 bool isLoad() const { return staticInst->isLoad(); }
515 bool isStore() const { return staticInst->isStore(); }
516 bool isStoreConditional() const
517 { return staticInst->isStoreConditional(); }
518 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
519 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
520 bool isInteger() const { return staticInst->isInteger(); }
521 bool isFloating() const { return staticInst->isFloating(); }
522 bool isControl() const { return staticInst->isControl(); }
523 bool isCall() const { return staticInst->isCall(); }
524 bool isReturn() const { return staticInst->isReturn(); }
525 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
526 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
527 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
528 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
529 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
530 bool isThreadSync() const { return staticInst->isThreadSync(); }
531 bool isSerializing() const { return staticInst->isSerializing(); }
532 bool isSerializeBefore() const
533 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
534 bool isSerializeAfter() const
535 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
536 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
537 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
538 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
539 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
540 bool isQuiesce() const { return staticInst->isQuiesce(); }
541 bool isIprAccess() const { return staticInst->isIprAccess(); }
542 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
543 bool isSyscall() const { return staticInst->isSyscall(); }
544 bool isMacroop() const { return staticInst->isMacroop(); }
545 bool isMicroop() const { return staticInst->isMicroop(); }
546 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
547 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
548 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
549 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
550
551 /** Temporarily sets this instruction as a serialize before instruction. */
552 void setSerializeBefore() { status.set(SerializeBefore); }
553
554 /** Clears the serializeBefore part of this instruction. */
555 void clearSerializeBefore() { status.reset(SerializeBefore); }
556
557 /** Checks if this serializeBefore is only temporarily set. */
558 bool isTempSerializeBefore() { return status[SerializeBefore]; }
559
560 /** Temporarily sets this instruction as a serialize after instruction. */
561 void setSerializeAfter() { status.set(SerializeAfter); }
562
563 /** Clears the serializeAfter part of this instruction.*/
564 void clearSerializeAfter() { status.reset(SerializeAfter); }
565
566 /** Checks if this serializeAfter is only temporarily set. */
567 bool isTempSerializeAfter() { return status[SerializeAfter]; }
568
569 /** Sets the serialization part of this instruction as handled. */
570 void setSerializeHandled() { status.set(SerializeHandled); }
571
572 /** Checks if the serialization part of this instruction has been
573 * handled. This does not apply to the temporary serializing
574 * state; it only applies to this instruction's own permanent
575 * serializing state.
576 */
577 bool isSerializeHandled() { return status[SerializeHandled]; }
578
579 /** Returns the opclass of this instruction. */
580 OpClass opClass() const { return staticInst->opClass(); }
581
582 /** Returns the branch target address. */
583 TheISA::PCState branchTarget() const
584 { return staticInst->branchTarget(pc); }
585
586 /** Returns the number of source registers. */
587 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
588
589 /** Returns the number of destination registers. */
590 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
591
592 // the following are used to track physical register usage
593 // for machines with separate int & FP reg files
594 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
595 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
596
597 /** Returns the logical register index of the i'th destination register. */
598 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
599
600 /** Returns the logical register index of the i'th source register. */
601 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
602
603 /** Pops a result off the instResult queue */
604 template <class T>
605 void popResult(T& t)
606 {
607 if (!instResult.empty()) {
608 instResult.front().get(t);
609 instResult.pop();
610 }
611 }
612
613 /** Read the most recent result stored by this instruction */
614 template <class T>
615 void readResult(T& t)
616 {
617 instResult.back().get(t);
618 }
619
620 /** Pushes a result onto the instResult queue */
621 template <class T>
622 void setResult(T t)
623 {
624 if (instFlags[RecordResult]) {
625 Result instRes;
626 instRes.set(t);
627 instResult.push(instRes);
628 }
629 }
630
631 /** Records an integer register being set to a value. */
632 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
633 {
634 setResult<uint64_t>(val);
635 }
636
|
636 /** Records an fp register being set to a value. */
637 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
638 int width)
639 {
640 if (width == 32 || width == 64) {
641 setResult<double>(val);
642 } else {
643 panic("Unsupported width!");
644 }
645 }
646
647 /** Records an fp register being set to a value. */
648 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
649 {
650 setResult<double>(val);
651 }
652
653 /** Records an fp register being set to an integer value. */
654 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
655 int width)
656 {
657 setResult<uint64_t>(val);
658 }
659
660 /** Records an fp register being set to an integer value. */
661 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
662 {
663 setResult<uint64_t>(val);
664 }
665
666 /** Records that one of the source registers is ready. */
667 void markSrcRegReady();
668
669 /** Marks a specific register as ready. */
670 void markSrcRegReady(RegIndex src_idx);
671
672 /** Returns if a source register is ready. */
673 bool isReadySrcRegIdx(int idx) const
674 {
675 return this->_readySrcRegIdx[idx];
676 }
677
678 /** Sets this instruction as completed. */
679 void setCompleted() { status.set(Completed); }
680
681 /** Returns whether or not this instruction is completed. */
682 bool isCompleted() const { return status[Completed]; }
683
684 /** Marks the result as ready. */
685 void setResultReady() { status.set(ResultReady); }
686
687 /** Returns whether or not the result is ready. */
688 bool isResultReady() const { return status[ResultReady]; }
689
690 /** Sets this instruction as ready to issue. */
691 void setCanIssue() { status.set(CanIssue); }
692
693 /** Returns whether or not this instruction is ready to issue. */
694 bool readyToIssue() const { return status[CanIssue]; }
695
696 /** Clears this instruction being able to issue. */
697 void clearCanIssue() { status.reset(CanIssue); }
698
699 /** Sets this instruction as issued from the IQ. */
700 void setIssued() { status.set(Issued); }
701
702 /** Returns whether or not this instruction has issued. */
703 bool isIssued() const { return status[Issued]; }
704
705 /** Clears this instruction as being issued. */
706 void clearIssued() { status.reset(Issued); }
707
708 /** Sets this instruction as executed. */
709 void setExecuted() { status.set(Executed); }
710
711 /** Returns whether or not this instruction has executed. */
712 bool isExecuted() const { return status[Executed]; }
713
714 /** Sets this instruction as ready to commit. */
715 void setCanCommit() { status.set(CanCommit); }
716
717 /** Clears this instruction as being ready to commit. */
718 void clearCanCommit() { status.reset(CanCommit); }
719
720 /** Returns whether or not this instruction is ready to commit. */
721 bool readyToCommit() const { return status[CanCommit]; }
722
723 void setAtCommit() { status.set(AtCommit); }
724
725 bool isAtCommit() { return status[AtCommit]; }
726
727 /** Sets this instruction as committed. */
728 void setCommitted() { status.set(Committed); }
729
730 /** Returns whether or not this instruction is committed. */
731 bool isCommitted() const { return status[Committed]; }
732
733 /** Sets this instruction as squashed. */
734 void setSquashed() { status.set(Squashed); }
735
736 /** Returns whether or not this instruction is squashed. */
737 bool isSquashed() const { return status[Squashed]; }
738
739 //Instruction Queue Entry
740 //-----------------------
741 /** Sets this instruction as a entry the IQ. */
742 void setInIQ() { status.set(IqEntry); }
743
744 /** Sets this instruction as a entry the IQ. */
745 void clearInIQ() { status.reset(IqEntry); }
746
747 /** Returns whether or not this instruction has issued. */
748 bool isInIQ() const { return status[IqEntry]; }
749
750 /** Sets this instruction as squashed in the IQ. */
751 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
752
753 /** Returns whether or not this instruction is squashed in the IQ. */
754 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
755
756
757 //Load / Store Queue Functions
758 //-----------------------
759 /** Sets this instruction as a entry the LSQ. */
760 void setInLSQ() { status.set(LsqEntry); }
761
762 /** Sets this instruction as a entry the LSQ. */
763 void removeInLSQ() { status.reset(LsqEntry); }
764
765 /** Returns whether or not this instruction is in the LSQ. */
766 bool isInLSQ() const { return status[LsqEntry]; }
767
768 /** Sets this instruction as squashed in the LSQ. */
769 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
770
771 /** Returns whether or not this instruction is squashed in the LSQ. */
772 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
773
774
775 //Reorder Buffer Functions
776 //-----------------------
777 /** Sets this instruction as a entry the ROB. */
778 void setInROB() { status.set(RobEntry); }
779
780 /** Sets this instruction as a entry the ROB. */
781 void clearInROB() { status.reset(RobEntry); }
782
783 /** Returns whether or not this instruction is in the ROB. */
784 bool isInROB() const { return status[RobEntry]; }
785
786 /** Sets this instruction as squashed in the ROB. */
787 void setSquashedInROB() { status.set(SquashedInROB); }
788
789 /** Returns whether or not this instruction is squashed in the ROB. */
790 bool isSquashedInROB() const { return status[SquashedInROB]; }
791
792 /** Read the PC state of this instruction. */
793 const TheISA::PCState pcState() const { return pc; }
794
795 /** Set the PC state of this instruction. */
796 const void pcState(const TheISA::PCState &val) { pc = val; }
797
798 /** Read the PC of this instruction. */
799 const Addr instAddr() const { return pc.instAddr(); }
800
801 /** Read the PC of the next instruction. */
802 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
803
804 /**Read the micro PC of this instruction. */
805 const Addr microPC() const { return pc.microPC(); }
806
807 bool readPredicate()
808 {
809 return instFlags[Predicate];
810 }
811
812 void setPredicate(bool val)
813 {
814 instFlags[Predicate] = val;
815
816 if (traceData) {
817 traceData->setPredicate(val);
818 }
819 }
820
821 /** Sets the ASID. */
822 void setASID(short addr_space_id) { asid = addr_space_id; }
823
824 /** Sets the thread id. */
825 void setTid(ThreadID tid) { threadNumber = tid; }
826
827 /** Sets the pointer to the thread state. */
828 void setThreadState(ImplState *state) { thread = state; }
829
830 /** Returns the thread context. */
831 ThreadContext *tcBase() { return thread->getTC(); }
832
833 public:
834 /** Sets the effective address. */
835 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
836
837 /** Returns the effective address. */
838 const Addr &getEA() const { return instEffAddr; }
839
840 /** Returns whether or not the eff. addr. calculation has been completed. */
841 bool doneEACalc() { return instFlags[EACalcDone]; }
842
843 /** Returns whether or not the eff. addr. source registers are ready. */
844 bool eaSrcsReady();
845
846 /** Is this instruction's memory access uncacheable. */
847 bool uncacheable() { return instFlags[IsUncacheable]; }
848
849 /** Has this instruction generated a memory request. */
850 bool hasRequest() { return instFlags[ReqMade]; }
851
852 /** Returns iterator to this instruction in the list of all insts. */
853 ListIt &getInstListIt() { return instListIt; }
854
855 /** Sets iterator for this instruction in the list of all insts. */
856 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
857
858 public:
859 /** Returns the number of consecutive store conditional failures. */
860 unsigned readStCondFailures()
861 { return thread->storeCondFailures; }
862
863 /** Sets the number of consecutive store conditional failures. */
864 void setStCondFailures(unsigned sc_failures)
865 { thread->storeCondFailures = sc_failures; }
866};
867
868template<class Impl>
869Fault
870BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
871 unsigned size, unsigned flags)
872{
873 instFlags[ReqMade] = true;
874 Request *req = NULL;
875 Request *sreqLow = NULL;
876 Request *sreqHigh = NULL;
877
878 if (instFlags[ReqMade] && translationStarted()) {
879 req = savedReq;
880 sreqLow = savedSreqLow;
881 sreqHigh = savedSreqHigh;
882 } else {
883 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
884 thread->contextId(), threadNumber);
885
886 // Only split the request if the ISA supports unaligned accesses.
887 if (TheISA::HasUnalignedMemAcc) {
888 splitRequest(req, sreqLow, sreqHigh);
889 }
890 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
891 }
892
893 if (translationCompleted()) {
894 if (fault == NoFault) {
895 effAddr = req->getVaddr();
896 effSize = size;
897 instFlags[EffAddrValid] = true;
898
899 if (cpu->checker) {
900 if (reqToVerify != NULL) {
901 delete reqToVerify;
902 }
903 reqToVerify = new Request(*req);
904 }
905 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
906 } else {
907 // Commit will have to clean up whatever happened. Set this
908 // instruction as executed.
909 this->setExecuted();
910 }
911
912 if (fault != NoFault) {
913 // Return a fixed value to keep simulation deterministic even
914 // along misspeculated paths.
915 if (data)
916 bzero(data, size);
917 }
918 }
919
920 if (traceData) {
921 traceData->setAddr(addr);
922 }
923
924 return fault;
925}
926
927template<class Impl>
928Fault
929BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
930 Addr addr, unsigned flags, uint64_t *res)
931{
932 if (traceData) {
933 traceData->setAddr(addr);
934 }
935
936 instFlags[ReqMade] = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (instFlags[ReqMade] && translationStarted()) {
942 req = savedReq;
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
945 } else {
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
947 thread->contextId(), threadNumber);
948
949 // Only split the request if the ISA supports unaligned accesses.
950 if (TheISA::HasUnalignedMemAcc) {
951 splitRequest(req, sreqLow, sreqHigh);
952 }
953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
954 }
955
956 if (fault == NoFault && translationCompleted()) {
957 effAddr = req->getVaddr();
958 effSize = size;
959 instFlags[EffAddrValid] = true;
960
961 if (cpu->checker) {
962 if (reqToVerify != NULL) {
963 delete reqToVerify;
964 }
965 reqToVerify = new Request(*req);
966 }
967 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
968 }
969
970 return fault;
971}
972
973template<class Impl>
974inline void
975BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
976 RequestPtr &sreqHigh)
977{
978 // Check to see if the request crosses the next level block boundary.
979 unsigned block_size = cpu->cacheLineSize();
980 Addr addr = req->getVaddr();
981 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
982 assert(split_addr <= addr || split_addr - addr < block_size);
983
984 // Spans two blocks.
985 if (split_addr > addr) {
986 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
987 }
988}
989
990template<class Impl>
991inline void
992BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
993 RequestPtr sreqHigh, uint64_t *res,
994 BaseTLB::Mode mode)
995{
996 translationStarted(true);
997
998 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
999 WholeTranslationState *state =
1000 new WholeTranslationState(req, NULL, res, mode);
1001
1002 // One translation if the request isn't split.
1003 DataTranslation<BaseDynInstPtr> *trans =
1004 new DataTranslation<BaseDynInstPtr>(this, state);
1005 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1006 if (!translationCompleted()) {
1007 // Save memory requests.
1008 savedReq = state->mainReq;
1009 savedSreqLow = state->sreqLow;
1010 savedSreqHigh = state->sreqHigh;
1011 }
1012 } else {
1013 WholeTranslationState *state =
1014 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1015
1016 // Two translations when the request is split.
1017 DataTranslation<BaseDynInstPtr> *stransLow =
1018 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1019 DataTranslation<BaseDynInstPtr> *stransHigh =
1020 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1021
1022 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1023 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1024 if (!translationCompleted()) {
1025 // Save memory requests.
1026 savedReq = state->mainReq;
1027 savedSreqLow = state->sreqLow;
1028 savedSreqHigh = state->sreqHigh;
1029 }
1030 }
1031}
1032
1033template<class Impl>
1034inline void
1035BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1036{
1037 fault = state->getFault();
1038
1039 instFlags[IsUncacheable] = state->isUncacheable();
1040
1041 if (fault == NoFault) {
1042 physEffAddr = state->getPaddr();
1043 memReqFlags = state->getFlags();
1044
1045 if (state->mainReq->isCondSwap()) {
1046 assert(state->res);
1047 state->mainReq->setExtraData(*state->res);
1048 }
1049
1050 } else {
1051 state->deleteReqs();
1052 }
1053 delete state;
1054
1055 translationCompleted(true);
1056}
1057
1058#endif // __CPU_BASE_DYN_INST_HH__
| 643 /** Records an fp register being set to a value. */
644 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
645 int width)
646 {
647 if (width == 32 || width == 64) {
648 setResult<double>(val);
649 } else {
650 panic("Unsupported width!");
651 }
652 }
653
654 /** Records an fp register being set to a value. */
655 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
656 {
657 setResult<double>(val);
658 }
659
660 /** Records an fp register being set to an integer value. */
661 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
662 int width)
663 {
664 setResult<uint64_t>(val);
665 }
666
667 /** Records an fp register being set to an integer value. */
668 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
669 {
670 setResult<uint64_t>(val);
671 }
672
673 /** Records that one of the source registers is ready. */
674 void markSrcRegReady();
675
676 /** Marks a specific register as ready. */
677 void markSrcRegReady(RegIndex src_idx);
678
679 /** Returns if a source register is ready. */
680 bool isReadySrcRegIdx(int idx) const
681 {
682 return this->_readySrcRegIdx[idx];
683 }
684
685 /** Sets this instruction as completed. */
686 void setCompleted() { status.set(Completed); }
687
688 /** Returns whether or not this instruction is completed. */
689 bool isCompleted() const { return status[Completed]; }
690
691 /** Marks the result as ready. */
692 void setResultReady() { status.set(ResultReady); }
693
694 /** Returns whether or not the result is ready. */
695 bool isResultReady() const { return status[ResultReady]; }
696
697 /** Sets this instruction as ready to issue. */
698 void setCanIssue() { status.set(CanIssue); }
699
700 /** Returns whether or not this instruction is ready to issue. */
701 bool readyToIssue() const { return status[CanIssue]; }
702
703 /** Clears this instruction being able to issue. */
704 void clearCanIssue() { status.reset(CanIssue); }
705
706 /** Sets this instruction as issued from the IQ. */
707 void setIssued() { status.set(Issued); }
708
709 /** Returns whether or not this instruction has issued. */
710 bool isIssued() const { return status[Issued]; }
711
712 /** Clears this instruction as being issued. */
713 void clearIssued() { status.reset(Issued); }
714
715 /** Sets this instruction as executed. */
716 void setExecuted() { status.set(Executed); }
717
718 /** Returns whether or not this instruction has executed. */
719 bool isExecuted() const { return status[Executed]; }
720
721 /** Sets this instruction as ready to commit. */
722 void setCanCommit() { status.set(CanCommit); }
723
724 /** Clears this instruction as being ready to commit. */
725 void clearCanCommit() { status.reset(CanCommit); }
726
727 /** Returns whether or not this instruction is ready to commit. */
728 bool readyToCommit() const { return status[CanCommit]; }
729
730 void setAtCommit() { status.set(AtCommit); }
731
732 bool isAtCommit() { return status[AtCommit]; }
733
734 /** Sets this instruction as committed. */
735 void setCommitted() { status.set(Committed); }
736
737 /** Returns whether or not this instruction is committed. */
738 bool isCommitted() const { return status[Committed]; }
739
740 /** Sets this instruction as squashed. */
741 void setSquashed() { status.set(Squashed); }
742
743 /** Returns whether or not this instruction is squashed. */
744 bool isSquashed() const { return status[Squashed]; }
745
746 //Instruction Queue Entry
747 //-----------------------
748 /** Sets this instruction as a entry the IQ. */
749 void setInIQ() { status.set(IqEntry); }
750
751 /** Sets this instruction as a entry the IQ. */
752 void clearInIQ() { status.reset(IqEntry); }
753
754 /** Returns whether or not this instruction has issued. */
755 bool isInIQ() const { return status[IqEntry]; }
756
757 /** Sets this instruction as squashed in the IQ. */
758 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
759
760 /** Returns whether or not this instruction is squashed in the IQ. */
761 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
762
763
764 //Load / Store Queue Functions
765 //-----------------------
766 /** Sets this instruction as a entry the LSQ. */
767 void setInLSQ() { status.set(LsqEntry); }
768
769 /** Sets this instruction as a entry the LSQ. */
770 void removeInLSQ() { status.reset(LsqEntry); }
771
772 /** Returns whether or not this instruction is in the LSQ. */
773 bool isInLSQ() const { return status[LsqEntry]; }
774
775 /** Sets this instruction as squashed in the LSQ. */
776 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
777
778 /** Returns whether or not this instruction is squashed in the LSQ. */
779 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
780
781
782 //Reorder Buffer Functions
783 //-----------------------
784 /** Sets this instruction as a entry the ROB. */
785 void setInROB() { status.set(RobEntry); }
786
787 /** Sets this instruction as a entry the ROB. */
788 void clearInROB() { status.reset(RobEntry); }
789
790 /** Returns whether or not this instruction is in the ROB. */
791 bool isInROB() const { return status[RobEntry]; }
792
793 /** Sets this instruction as squashed in the ROB. */
794 void setSquashedInROB() { status.set(SquashedInROB); }
795
796 /** Returns whether or not this instruction is squashed in the ROB. */
797 bool isSquashedInROB() const { return status[SquashedInROB]; }
798
799 /** Read the PC state of this instruction. */
800 const TheISA::PCState pcState() const { return pc; }
801
802 /** Set the PC state of this instruction. */
803 const void pcState(const TheISA::PCState &val) { pc = val; }
804
805 /** Read the PC of this instruction. */
806 const Addr instAddr() const { return pc.instAddr(); }
807
808 /** Read the PC of the next instruction. */
809 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
810
811 /**Read the micro PC of this instruction. */
812 const Addr microPC() const { return pc.microPC(); }
813
814 bool readPredicate()
815 {
816 return instFlags[Predicate];
817 }
818
819 void setPredicate(bool val)
820 {
821 instFlags[Predicate] = val;
822
823 if (traceData) {
824 traceData->setPredicate(val);
825 }
826 }
827
828 /** Sets the ASID. */
829 void setASID(short addr_space_id) { asid = addr_space_id; }
830
831 /** Sets the thread id. */
832 void setTid(ThreadID tid) { threadNumber = tid; }
833
834 /** Sets the pointer to the thread state. */
835 void setThreadState(ImplState *state) { thread = state; }
836
837 /** Returns the thread context. */
838 ThreadContext *tcBase() { return thread->getTC(); }
839
840 public:
841 /** Sets the effective address. */
842 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
843
844 /** Returns the effective address. */
845 const Addr &getEA() const { return instEffAddr; }
846
847 /** Returns whether or not the eff. addr. calculation has been completed. */
848 bool doneEACalc() { return instFlags[EACalcDone]; }
849
850 /** Returns whether or not the eff. addr. source registers are ready. */
851 bool eaSrcsReady();
852
853 /** Is this instruction's memory access uncacheable. */
854 bool uncacheable() { return instFlags[IsUncacheable]; }
855
856 /** Has this instruction generated a memory request. */
857 bool hasRequest() { return instFlags[ReqMade]; }
858
859 /** Returns iterator to this instruction in the list of all insts. */
860 ListIt &getInstListIt() { return instListIt; }
861
862 /** Sets iterator for this instruction in the list of all insts. */
863 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
864
865 public:
866 /** Returns the number of consecutive store conditional failures. */
867 unsigned readStCondFailures()
868 { return thread->storeCondFailures; }
869
870 /** Sets the number of consecutive store conditional failures. */
871 void setStCondFailures(unsigned sc_failures)
872 { thread->storeCondFailures = sc_failures; }
873};
874
875template<class Impl>
876Fault
877BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
878 unsigned size, unsigned flags)
879{
880 instFlags[ReqMade] = true;
881 Request *req = NULL;
882 Request *sreqLow = NULL;
883 Request *sreqHigh = NULL;
884
885 if (instFlags[ReqMade] && translationStarted()) {
886 req = savedReq;
887 sreqLow = savedSreqLow;
888 sreqHigh = savedSreqHigh;
889 } else {
890 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
891 thread->contextId(), threadNumber);
892
893 // Only split the request if the ISA supports unaligned accesses.
894 if (TheISA::HasUnalignedMemAcc) {
895 splitRequest(req, sreqLow, sreqHigh);
896 }
897 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
898 }
899
900 if (translationCompleted()) {
901 if (fault == NoFault) {
902 effAddr = req->getVaddr();
903 effSize = size;
904 instFlags[EffAddrValid] = true;
905
906 if (cpu->checker) {
907 if (reqToVerify != NULL) {
908 delete reqToVerify;
909 }
910 reqToVerify = new Request(*req);
911 }
912 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
913 } else {
914 // Commit will have to clean up whatever happened. Set this
915 // instruction as executed.
916 this->setExecuted();
917 }
918
919 if (fault != NoFault) {
920 // Return a fixed value to keep simulation deterministic even
921 // along misspeculated paths.
922 if (data)
923 bzero(data, size);
924 }
925 }
926
927 if (traceData) {
928 traceData->setAddr(addr);
929 }
930
931 return fault;
932}
933
934template<class Impl>
935Fault
936BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
937 Addr addr, unsigned flags, uint64_t *res)
938{
939 if (traceData) {
940 traceData->setAddr(addr);
941 }
942
943 instFlags[ReqMade] = true;
944 Request *req = NULL;
945 Request *sreqLow = NULL;
946 Request *sreqHigh = NULL;
947
948 if (instFlags[ReqMade] && translationStarted()) {
949 req = savedReq;
950 sreqLow = savedSreqLow;
951 sreqHigh = savedSreqHigh;
952 } else {
953 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
954 thread->contextId(), threadNumber);
955
956 // Only split the request if the ISA supports unaligned accesses.
957 if (TheISA::HasUnalignedMemAcc) {
958 splitRequest(req, sreqLow, sreqHigh);
959 }
960 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
961 }
962
963 if (fault == NoFault && translationCompleted()) {
964 effAddr = req->getVaddr();
965 effSize = size;
966 instFlags[EffAddrValid] = true;
967
968 if (cpu->checker) {
969 if (reqToVerify != NULL) {
970 delete reqToVerify;
971 }
972 reqToVerify = new Request(*req);
973 }
974 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
975 }
976
977 return fault;
978}
979
980template<class Impl>
981inline void
982BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
983 RequestPtr &sreqHigh)
984{
985 // Check to see if the request crosses the next level block boundary.
986 unsigned block_size = cpu->cacheLineSize();
987 Addr addr = req->getVaddr();
988 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
989 assert(split_addr <= addr || split_addr - addr < block_size);
990
991 // Spans two blocks.
992 if (split_addr > addr) {
993 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
994 }
995}
996
997template<class Impl>
998inline void
999BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1000 RequestPtr sreqHigh, uint64_t *res,
1001 BaseTLB::Mode mode)
1002{
1003 translationStarted(true);
1004
1005 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1006 WholeTranslationState *state =
1007 new WholeTranslationState(req, NULL, res, mode);
1008
1009 // One translation if the request isn't split.
1010 DataTranslation<BaseDynInstPtr> *trans =
1011 new DataTranslation<BaseDynInstPtr>(this, state);
1012 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1013 if (!translationCompleted()) {
1014 // Save memory requests.
1015 savedReq = state->mainReq;
1016 savedSreqLow = state->sreqLow;
1017 savedSreqHigh = state->sreqHigh;
1018 }
1019 } else {
1020 WholeTranslationState *state =
1021 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1022
1023 // Two translations when the request is split.
1024 DataTranslation<BaseDynInstPtr> *stransLow =
1025 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1026 DataTranslation<BaseDynInstPtr> *stransHigh =
1027 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1028
1029 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1030 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1031 if (!translationCompleted()) {
1032 // Save memory requests.
1033 savedReq = state->mainReq;
1034 savedSreqLow = state->sreqLow;
1035 savedSreqHigh = state->sreqHigh;
1036 }
1037 }
1038}
1039
1040template<class Impl>
1041inline void
1042BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1043{
1044 fault = state->getFault();
1045
1046 instFlags[IsUncacheable] = state->isUncacheable();
1047
1048 if (fault == NoFault) {
1049 physEffAddr = state->getPaddr();
1050 memReqFlags = state->getFlags();
1051
1052 if (state->mainReq->isCondSwap()) {
1053 assert(state->res);
1054 state->mainReq->setExtraData(*state->res);
1055 }
1056
1057 } else {
1058 state->deleteReqs();
1059 }
1060 delete state;
1061
1062 translationCompleted(true);
1063}
1064
1065#endif // __CPU_BASE_DYN_INST_HH__
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