1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Timothy M. Jones
43 */
44
45#ifndef __CPU_BASE_DYN_INST_HH__
46#define __CPU_BASE_DYN_INST_HH__
47
48#include <bitset>
49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "config/use_checker.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public FastAlloc, public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
100 };
101
102 /** The StaticInst used by this BaseDynInst. */
103 StaticInstPtr staticInst;
104 StaticInstPtr macroop;
105
106 ////////////////////////////////////////////
107 //
108 // INSTRUCTION EXECUTION
109 //
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
113
114 void demapPage(Addr vaddr, uint64_t asn)
115 {
116 cpu->demapPage(vaddr, asn);
117 }
118 void demapInstPage(Addr vaddr, uint64_t asn)
119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,
139 BaseTLB::Mode mode);
140
141 /** Finish a DTB address translation. */
142 void finishTranslation(WholeTranslationState *state);
143
144 /** True if the DTB address translation has started. */
145 bool translationStarted;
146
147 /** True if the DTB address translation has completed. */
148 bool translationCompleted;
149
150 /** True if this address was found to match a previous load and they issued
151 * out of order. If that happend, then it's only a problem if an incoming
152 * snoop invalidate modifies the line, in which case we need to squash.
153 * If nothing modified the line the order doesn't matter.
154 */
155 bool possibleLoadViolation;
156
157 /** True if the address hit a external snoop while sitting in the LSQ.
158 * If this is true and a older instruction sees it, this instruction must
159 * reexecute
160 */
161 bool hitExternalSnoop;
162
163 /**
164 * Returns true if the DTB address translation is being delayed due to a hw
165 * page table walk.
166 */
167 bool isTranslationDelayed() const
168 {
169 return (translationStarted && !translationCompleted);
170 }
171
172 /**
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
175 */
176 RequestPtr savedReq;
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
179
180#if USE_CHECKER
181 // Need a copy of main request pointer to verify on writes.
182 RequestPtr reqToVerify;
183#endif //USE_CHECKER
184
185 /** @todo: Consider making this private. */
186 public:
187 /** The sequence number of the instruction. */
188 InstSeqNum seqNum;
189
190 enum Status {
191 IqEntry, /// Instruction is in the IQ
192 RobEntry, /// Instruction is in the ROB
193 LsqEntry, /// Instruction is in the LSQ
194 Completed, /// Instruction has completed
195 ResultReady, /// Instruction has its result
196 CanIssue, /// Instruction can issue and execute
197 Issued, /// Instruction has issued
198 Executed, /// Instruction has executed
199 CanCommit, /// Instruction can commit
200 AtCommit, /// Instruction has reached commit
201 Committed, /// Instruction has committed
202 Squashed, /// Instruction is squashed
203 SquashedInIQ, /// Instruction is squashed in the IQ
204 SquashedInLSQ, /// Instruction is squashed in the LSQ
205 SquashedInROB, /// Instruction is squashed in the ROB
206 RecoverInst, /// Is a recover instruction
207 BlockingInst, /// Is a blocking instruction
208 ThreadsyncWait, /// Is a thread synchronization instruction
209 SerializeBefore, /// Needs to serialize on
210 /// instructions ahead of it
211 SerializeAfter, /// Needs to serialize instructions behind it
212 SerializeHandled, /// Serialization has been handled
213 NumStatus
214 };
215
216 /** The status of this BaseDynInst. Several bits can be set. */
217 std::bitset<NumStatus> status;
218
219 /** The thread this instruction is from. */
220 ThreadID threadNumber;
221
222 /** data address space ID, for loads & stores. */
223 short asid;
224
225 /** How many source registers are ready. */
226 unsigned readyRegs;
227
228 /** Pointer to the Impl's CPU object. */
229 ImplCPU *cpu;
230
231 /** Pointer to the thread state. */
232 ImplState *thread;
233
234 /** The kind of fault this instruction has generated. */
235 Fault fault;
236
237 /** Pointer to the data for the memory access. */
238 uint8_t *memData;
239
240 /** The effective virtual address (lds & stores only). */
241 Addr effAddr;
242
243 /** The size of the request */
244 Addr effSize;
245
246 /** Is the effective virtual address valid. */
247 bool effAddrValid;
248
249 /** The effective physical address. */
250 Addr physEffAddr;
251
252 /** The memory request flags (from translation). */
253 unsigned memReqFlags;
254
255 union Result {
256 uint64_t integer;
257 double dbl;
258 void set(uint64_t i) { integer = i; }
259 void set(double d) { dbl = d; }
260 void get(uint64_t& i) { i = integer; }
261 void get(double& d) { d = dbl; }
262 };
263
264 /** The result of the instruction; assumes an instruction can have many
265 * destination registers.
266 */
267 std::queue<Result> instResult;
268
269 /** Records changes to result? */
270 bool recordResult;
271
272 /** Did this instruction execute, or is it predicated false */
273 bool predicate;
274
275 protected:
276 /** PC state for this instruction. */
277 TheISA::PCState pc;
278
279 /** Predicted PC state after this instruction. */
280 TheISA::PCState predPC;
281
282 /** If this is a branch that was predicted taken */
283 bool predTaken;
284
285 public:
286
287#ifdef DEBUG
288 void dumpSNList();
289#endif
290
291 /** Whether or not the source register is ready.
292 * @todo: Not sure this should be here vs the derived class.
293 */
294 bool _readySrcRegIdx[MaxInstSrcRegs];
295
296 protected:
297 /** Flattened register index of the destination registers of this
298 * instruction.
299 */
300 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
301
302 /** Flattened register index of the source registers of this
303 * instruction.
304 */
305 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
306
307 /** Physical register index of the destination registers of this
308 * instruction.
309 */
310 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
311
312 /** Physical register index of the source registers of this
313 * instruction.
314 */
315 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
316
317 /** Physical register index of the previous producers of the
318 * architected destinations.
319 */
320 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
321
322 public:
323
324 /** Returns the physical register index of the i'th destination
325 * register.
326 */
327 PhysRegIndex renamedDestRegIdx(int idx) const
328 {
329 return _destRegIdx[idx];
330 }
331
332 /** Returns the physical register index of the i'th source register. */
333 PhysRegIndex renamedSrcRegIdx(int idx) const
334 {
335 return _srcRegIdx[idx];
336 }
337
338 /** Returns the flattened register index of the i'th destination
339 * register.
340 */
341 TheISA::RegIndex flattenedDestRegIdx(int idx) const
342 {
343 return _flatDestRegIdx[idx];
344 }
345
346 /** Returns the flattened register index of the i'th source register */
347 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
348 {
349 return _flatSrcRegIdx[idx];
350 }
351
352 /** Returns the physical register index of the previous physical register
353 * that remapped to the same logical register index.
354 */
355 PhysRegIndex prevDestRegIdx(int idx) const
356 {
357 return _prevDestRegIdx[idx];
358 }
359
360 /** Renames a destination register to a physical register. Also records
361 * the previous physical register that the logical register mapped to.
362 */
363 void renameDestReg(int idx,
364 PhysRegIndex renamed_dest,
365 PhysRegIndex previous_rename)
366 {
367 _destRegIdx[idx] = renamed_dest;
368 _prevDestRegIdx[idx] = previous_rename;
369 }
370
371 /** Renames a source logical register to the physical register which
372 * has/will produce that logical register's result.
373 * @todo: add in whether or not the source register is ready.
374 */
375 void renameSrcReg(int idx, PhysRegIndex renamed_src)
376 {
377 _srcRegIdx[idx] = renamed_src;
378 }
379
380 /** Flattens a source architectural register index into a logical index.
381 */
382 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
383 {
384 _flatSrcRegIdx[idx] = flattened_src;
385 }
386
387 /** Flattens a destination architectural register index into a logical
388 * index.
389 */
390 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
391 {
392 _flatDestRegIdx[idx] = flattened_dest;
393 }
394 /** BaseDynInst constructor given a binary instruction.
395 * @param staticInst A StaticInstPtr to the underlying instruction.
396 * @param pc The PC state for the instruction.
397 * @param predPC The predicted next PC state for the instruction.
398 * @param seq_num The sequence number of the instruction.
399 * @param cpu Pointer to the instruction's CPU.
400 */
401 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
402 TheISA::PCState pc, TheISA::PCState predPC,
403 InstSeqNum seq_num, ImplCPU *cpu);
404
405 /** BaseDynInst constructor given a StaticInst pointer.
406 * @param _staticInst The StaticInst for this BaseDynInst.
407 */
408 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
409
410 /** BaseDynInst destructor. */
411 ~BaseDynInst();
412
413 private:
414 /** Function to initialize variables in the constructors. */
415 void initVars();
416
417 public:
418 /** Dumps out contents of this BaseDynInst. */
419 void dump();
420
421 /** Dumps out contents of this BaseDynInst into given string. */
422 void dump(std::string &outstring);
423
424 /** Read this CPU's ID. */
425 int cpuId() { return cpu->cpuId(); }
426
427 /** Read this CPU's data requestor ID */
428 MasterID masterId() { return cpu->dataMasterId(); }
429
430 /** Read this context's system-wide ID **/
431 int contextId() { return thread->contextId(); }
432
433 /** Returns the fault type. */
434 Fault getFault() { return fault; }
435
436 /** Checks whether or not this instruction has had its branch target
437 * calculated yet. For now it is not utilized and is hacked to be
438 * always false.
439 * @todo: Actually use this instruction.
440 */
441 bool doneTargCalc() { return false; }
442
443 /** Set the predicted target of this current instruction. */
444 void setPredTarg(const TheISA::PCState &_predPC)
445 {
446 predPC = _predPC;
447 }
448
449 const TheISA::PCState &readPredTarg() { return predPC; }
450
451 /** Returns the predicted PC immediately after the branch. */
452 Addr predInstAddr() { return predPC.instAddr(); }
453
454 /** Returns the predicted PC two instructions after the branch */
455 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
456
457 /** Returns the predicted micro PC after the branch */
458 Addr predMicroPC() { return predPC.microPC(); }
459
460 /** Returns whether the instruction was predicted taken or not. */
461 bool readPredTaken()
462 {
463 return predTaken;
464 }
465
466 void setPredTaken(bool predicted_taken)
467 {
468 predTaken = predicted_taken;
469 }
470
471 /** Returns whether the instruction mispredicted. */
472 bool mispredicted()
473 {
474 TheISA::PCState tempPC = pc;
475 TheISA::advancePC(tempPC, staticInst);
476 return !(tempPC == predPC);
477 }
478
479 //
480 // Instruction types. Forward checks to StaticInst object.
481 //
482 bool isNop() const { return staticInst->isNop(); }
483 bool isMemRef() const { return staticInst->isMemRef(); }
484 bool isLoad() const { return staticInst->isLoad(); }
485 bool isStore() const { return staticInst->isStore(); }
486 bool isStoreConditional() const
487 { return staticInst->isStoreConditional(); }
488 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
489 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
490 bool isInteger() const { return staticInst->isInteger(); }
491 bool isFloating() const { return staticInst->isFloating(); }
492 bool isControl() const { return staticInst->isControl(); }
493 bool isCall() const { return staticInst->isCall(); }
494 bool isReturn() const { return staticInst->isReturn(); }
495 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
496 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
497 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
498 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
499 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
500 bool isThreadSync() const { return staticInst->isThreadSync(); }
501 bool isSerializing() const { return staticInst->isSerializing(); }
502 bool isSerializeBefore() const
503 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
504 bool isSerializeAfter() const
505 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
506 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
507 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
508 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
509 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
510 bool isQuiesce() const { return staticInst->isQuiesce(); }
511 bool isIprAccess() const { return staticInst->isIprAccess(); }
512 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
513 bool isSyscall() const { return staticInst->isSyscall(); }
514 bool isMacroop() const { return staticInst->isMacroop(); }
515 bool isMicroop() const { return staticInst->isMicroop(); }
516 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
517 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
518 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
519 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
520
521 /** Temporarily sets this instruction as a serialize before instruction. */
522 void setSerializeBefore() { status.set(SerializeBefore); }
523
524 /** Clears the serializeBefore part of this instruction. */
525 void clearSerializeBefore() { status.reset(SerializeBefore); }
526
527 /** Checks if this serializeBefore is only temporarily set. */
528 bool isTempSerializeBefore() { return status[SerializeBefore]; }
529
530 /** Temporarily sets this instruction as a serialize after instruction. */
531 void setSerializeAfter() { status.set(SerializeAfter); }
532
533 /** Clears the serializeAfter part of this instruction.*/
534 void clearSerializeAfter() { status.reset(SerializeAfter); }
535
536 /** Checks if this serializeAfter is only temporarily set. */
537 bool isTempSerializeAfter() { return status[SerializeAfter]; }
538
539 /** Sets the serialization part of this instruction as handled. */
540 void setSerializeHandled() { status.set(SerializeHandled); }
541
542 /** Checks if the serialization part of this instruction has been
543 * handled. This does not apply to the temporary serializing
544 * state; it only applies to this instruction's own permanent
545 * serializing state.
546 */
547 bool isSerializeHandled() { return status[SerializeHandled]; }
548
549 /** Returns the opclass of this instruction. */
550 OpClass opClass() const { return staticInst->opClass(); }
551
552 /** Returns the branch target address. */
553 TheISA::PCState branchTarget() const
554 { return staticInst->branchTarget(pc); }
555
556 /** Returns the number of source registers. */
557 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
558
559 /** Returns the number of destination registers. */
560 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
561
562 // the following are used to track physical register usage
563 // for machines with separate int & FP reg files
564 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
565 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
566
567 /** Returns the logical register index of the i'th destination register. */
568 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
569
570 /** Returns the logical register index of the i'th source register. */
571 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
572
573 /** Pops a result off the instResult queue */
574 template <class T>
575 void popResult(T& t)
576 {
577 if (!instResult.empty()) {
578 instResult.front().get(t);
579 instResult.pop();
580 }
581 }
582
583 /** Read the most recent result stored by this instruction */
584 template <class T>
585 void readResult(T& t)
586 {
587 instResult.back().get(t);
588 }
589
590 /** Pushes a result onto the instResult queue */
591 template <class T>
592 void setResult(T t)
593 {
594 if (recordResult) {
595 Result instRes;
596 instRes.set(t);
597 instResult.push(instRes);
598 }
599 }
600
601 /** Records an integer register being set to a value. */
602 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
603 {
604 setResult<uint64_t>(val);
605 }
606
607 /** Records an fp register being set to a value. */
608 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
609 int width)
610 {
611 if (width == 32 || width == 64) {
612 setResult<double>(val);
613 } else {
614 panic("Unsupported width!");
615 }
616 }
617
618 /** Records an fp register being set to a value. */
619 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
620 {
621 setResult<double>(val);
622 }
623
624 /** Records an fp register being set to an integer value. */
625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
626 int width)
627 {
628 setResult<uint64_t>(val);
629 }
630
631 /** Records an fp register being set to an integer value. */
632 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
633 {
634 setResult<uint64_t>(val);
635 }
636
637 /** Records that one of the source registers is ready. */
638 void markSrcRegReady();
639
640 /** Marks a specific register as ready. */
641 void markSrcRegReady(RegIndex src_idx);
642
643 /** Returns if a source register is ready. */
644 bool isReadySrcRegIdx(int idx) const
645 {
646 return this->_readySrcRegIdx[idx];
647 }
648
649 /** Sets this instruction as completed. */
650 void setCompleted() { status.set(Completed); }
651
652 /** Returns whether or not this instruction is completed. */
653 bool isCompleted() const { return status[Completed]; }
654
655 /** Marks the result as ready. */
656 void setResultReady() { status.set(ResultReady); }
657
658 /** Returns whether or not the result is ready. */
659 bool isResultReady() const { return status[ResultReady]; }
660
661 /** Sets this instruction as ready to issue. */
662 void setCanIssue() { status.set(CanIssue); }
663
664 /** Returns whether or not this instruction is ready to issue. */
665 bool readyToIssue() const { return status[CanIssue]; }
666
667 /** Clears this instruction being able to issue. */
668 void clearCanIssue() { status.reset(CanIssue); }
669
670 /** Sets this instruction as issued from the IQ. */
671 void setIssued() { status.set(Issued); }
672
673 /** Returns whether or not this instruction has issued. */
674 bool isIssued() const { return status[Issued]; }
675
676 /** Clears this instruction as being issued. */
677 void clearIssued() { status.reset(Issued); }
678
679 /** Sets this instruction as executed. */
680 void setExecuted() { status.set(Executed); }
681
682 /** Returns whether or not this instruction has executed. */
683 bool isExecuted() const { return status[Executed]; }
684
685 /** Sets this instruction as ready to commit. */
686 void setCanCommit() { status.set(CanCommit); }
687
688 /** Clears this instruction as being ready to commit. */
689 void clearCanCommit() { status.reset(CanCommit); }
690
691 /** Returns whether or not this instruction is ready to commit. */
692 bool readyToCommit() const { return status[CanCommit]; }
693
694 void setAtCommit() { status.set(AtCommit); }
695
696 bool isAtCommit() { return status[AtCommit]; }
697
698 /** Sets this instruction as committed. */
699 void setCommitted() { status.set(Committed); }
700
701 /** Returns whether or not this instruction is committed. */
702 bool isCommitted() const { return status[Committed]; }
703
704 /** Sets this instruction as squashed. */
705 void setSquashed() { status.set(Squashed); }
706
707 /** Returns whether or not this instruction is squashed. */
708 bool isSquashed() const { return status[Squashed]; }
709
710 //Instruction Queue Entry
711 //-----------------------
712 /** Sets this instruction as a entry the IQ. */
713 void setInIQ() { status.set(IqEntry); }
714
715 /** Sets this instruction as a entry the IQ. */
716 void clearInIQ() { status.reset(IqEntry); }
717
718 /** Returns whether or not this instruction has issued. */
719 bool isInIQ() const { return status[IqEntry]; }
720
721 /** Sets this instruction as squashed in the IQ. */
722 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
723
724 /** Returns whether or not this instruction is squashed in the IQ. */
725 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
726
727
728 //Load / Store Queue Functions
729 //-----------------------
730 /** Sets this instruction as a entry the LSQ. */
731 void setInLSQ() { status.set(LsqEntry); }
732
733 /** Sets this instruction as a entry the LSQ. */
734 void removeInLSQ() { status.reset(LsqEntry); }
735
736 /** Returns whether or not this instruction is in the LSQ. */
737 bool isInLSQ() const { return status[LsqEntry]; }
738
739 /** Sets this instruction as squashed in the LSQ. */
740 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
741
742 /** Returns whether or not this instruction is squashed in the LSQ. */
743 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
744
745
746 //Reorder Buffer Functions
747 //-----------------------
748 /** Sets this instruction as a entry the ROB. */
749 void setInROB() { status.set(RobEntry); }
750
751 /** Sets this instruction as a entry the ROB. */
752 void clearInROB() { status.reset(RobEntry); }
753
754 /** Returns whether or not this instruction is in the ROB. */
755 bool isInROB() const { return status[RobEntry]; }
756
757 /** Sets this instruction as squashed in the ROB. */
758 void setSquashedInROB() { status.set(SquashedInROB); }
759
760 /** Returns whether or not this instruction is squashed in the ROB. */
761 bool isSquashedInROB() const { return status[SquashedInROB]; }
762
763 /** Read the PC state of this instruction. */
764 const TheISA::PCState pcState() const { return pc; }
765
766 /** Set the PC state of this instruction. */
767 const void pcState(const TheISA::PCState &val) { pc = val; }
768
769 /** Read the PC of this instruction. */
770 const Addr instAddr() const { return pc.instAddr(); }
771
772 /** Read the PC of the next instruction. */
773 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
774
775 /**Read the micro PC of this instruction. */
776 const Addr microPC() const { return pc.microPC(); }
777
778 bool readPredicate()
779 {
780 return predicate;
781 }
782
783 void setPredicate(bool val)
784 {
785 predicate = val;
786
787 if (traceData) {
788 traceData->setPredicate(val);
789 }
790 }
791
792 /** Sets the ASID. */
793 void setASID(short addr_space_id) { asid = addr_space_id; }
794
795 /** Sets the thread id. */
796 void setTid(ThreadID tid) { threadNumber = tid; }
797
798 /** Sets the pointer to the thread state. */
799 void setThreadState(ImplState *state) { thread = state; }
800
801 /** Returns the thread context. */
802 ThreadContext *tcBase() { return thread->getTC(); }
803
804 private:
805 /** Instruction effective address.
806 * @todo: Consider if this is necessary or not.
807 */
808 Addr instEffAddr;
809
810 /** Whether or not the effective address calculation is completed.
811 * @todo: Consider if this is necessary or not.
812 */
813 bool eaCalcDone;
814
815 /** Is this instruction's memory access uncacheable. */
816 bool isUncacheable;
817
818 /** Has this instruction generated a memory request. */
819 bool reqMade;
820
821 public:
822 /** Sets the effective address. */
823 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
824
825 /** Returns the effective address. */
826 const Addr &getEA() const { return instEffAddr; }
827
828 /** Returns whether or not the eff. addr. calculation has been completed. */
829 bool doneEACalc() { return eaCalcDone; }
830
831 /** Returns whether or not the eff. addr. source registers are ready. */
832 bool eaSrcsReady();
833
834 /** Whether or not the memory operation is done. */
835 bool memOpDone;
836
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return isUncacheable; }
839
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return reqMade; }
842
843 public:
844 /** Load queue index. */
845 int16_t lqIdx;
846
847 /** Store queue index. */
848 int16_t sqIdx;
849
850 /** Iterator pointing to this BaseDynInst in the list of all insts. */
851 ListIt instListIt;
852
853 /** Returns iterator to this instruction in the list of all insts. */
854 ListIt &getInstListIt() { return instListIt; }
855
856 /** Sets iterator for this instruction in the list of all insts. */
857 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
858
859 public:
860 /** Returns the number of consecutive store conditional failures. */
861 unsigned readStCondFailures()
862 { return thread->storeCondFailures; }
863
864 /** Sets the number of consecutive store conditional failures. */
865 void setStCondFailures(unsigned sc_failures)
866 { thread->storeCondFailures = sc_failures; }
867};
868
869template<class Impl>
870Fault
871BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
872 unsigned size, unsigned flags)
873{
874 reqMade = true;
875 Request *req = NULL;
876 Request *sreqLow = NULL;
877 Request *sreqHigh = NULL;
878
879 if (reqMade && translationStarted) {
880 req = savedReq;
881 sreqLow = savedSreqLow;
882 sreqHigh = savedSreqHigh;
883 } else {
884 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
885 thread->contextId(), threadNumber);
886
887 // Only split the request if the ISA supports unaligned accesses.
888 if (TheISA::HasUnalignedMemAcc) {
889 splitRequest(req, sreqLow, sreqHigh);
890 }
891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
892 }
893
894 if (translationCompleted) {
895 if (fault == NoFault) {
896 effAddr = req->getVaddr();
897 effSize = size;
898 effAddrValid = true;
899#if USE_CHECKER
900 if (reqToVerify != NULL) {
901 delete reqToVerify;
902 }
903 reqToVerify = new Request(*req);
904#endif //USE_CHECKER
905 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
906 } else {
907 // Commit will have to clean up whatever happened. Set this
908 // instruction as executed.
909 this->setExecuted();
910 }
911
912 if (fault != NoFault) {
913 // Return a fixed value to keep simulation deterministic even
914 // along misspeculated paths.
915 if (data)
916 bzero(data, size);
917 }
918 }
919
920 if (traceData) {
921 traceData->setAddr(addr);
922 }
923
924 return fault;
925}
926
927template<class Impl>
928Fault
929BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
930 Addr addr, unsigned flags, uint64_t *res)
931{
932 if (traceData) {
933 traceData->setAddr(addr);
934 }
935
936 reqMade = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (reqMade && translationStarted) {
942 req = savedReq;
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
945 } else {
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
947 thread->contextId(), threadNumber);
948
949 // Only split the request if the ISA supports unaligned accesses.
950 if (TheISA::HasUnalignedMemAcc) {
951 splitRequest(req, sreqLow, sreqHigh);
952 }
953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
954 }
955
956 if (fault == NoFault && translationCompleted) {
957 effAddr = req->getVaddr();
958 effSize = size;
959 effAddrValid = true;
960#if USE_CHECKER
961 if (reqToVerify != NULL) {
962 delete reqToVerify;
963 }
964 reqToVerify = new Request(*req);
965#endif // USE_CHECKER
966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>
973inline void
974BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
975 RequestPtr &sreqHigh)
976{
977 // Check to see if the request crosses the next level block boundary.
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Timothy M. Jones
43 */
44
45#ifndef __CPU_BASE_DYN_INST_HH__
46#define __CPU_BASE_DYN_INST_HH__
47
48#include <bitset>
49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "config/use_checker.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public FastAlloc, public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
100 };
101
102 /** The StaticInst used by this BaseDynInst. */
103 StaticInstPtr staticInst;
104 StaticInstPtr macroop;
105
106 ////////////////////////////////////////////
107 //
108 // INSTRUCTION EXECUTION
109 //
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
113
114 void demapPage(Addr vaddr, uint64_t asn)
115 {
116 cpu->demapPage(vaddr, asn);
117 }
118 void demapInstPage(Addr vaddr, uint64_t asn)
119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,
139 BaseTLB::Mode mode);
140
141 /** Finish a DTB address translation. */
142 void finishTranslation(WholeTranslationState *state);
143
144 /** True if the DTB address translation has started. */
145 bool translationStarted;
146
147 /** True if the DTB address translation has completed. */
148 bool translationCompleted;
149
150 /** True if this address was found to match a previous load and they issued
151 * out of order. If that happend, then it's only a problem if an incoming
152 * snoop invalidate modifies the line, in which case we need to squash.
153 * If nothing modified the line the order doesn't matter.
154 */
155 bool possibleLoadViolation;
156
157 /** True if the address hit a external snoop while sitting in the LSQ.
158 * If this is true and a older instruction sees it, this instruction must
159 * reexecute
160 */
161 bool hitExternalSnoop;
162
163 /**
164 * Returns true if the DTB address translation is being delayed due to a hw
165 * page table walk.
166 */
167 bool isTranslationDelayed() const
168 {
169 return (translationStarted && !translationCompleted);
170 }
171
172 /**
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
175 */
176 RequestPtr savedReq;
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
179
180#if USE_CHECKER
181 // Need a copy of main request pointer to verify on writes.
182 RequestPtr reqToVerify;
183#endif //USE_CHECKER
184
185 /** @todo: Consider making this private. */
186 public:
187 /** The sequence number of the instruction. */
188 InstSeqNum seqNum;
189
190 enum Status {
191 IqEntry, /// Instruction is in the IQ
192 RobEntry, /// Instruction is in the ROB
193 LsqEntry, /// Instruction is in the LSQ
194 Completed, /// Instruction has completed
195 ResultReady, /// Instruction has its result
196 CanIssue, /// Instruction can issue and execute
197 Issued, /// Instruction has issued
198 Executed, /// Instruction has executed
199 CanCommit, /// Instruction can commit
200 AtCommit, /// Instruction has reached commit
201 Committed, /// Instruction has committed
202 Squashed, /// Instruction is squashed
203 SquashedInIQ, /// Instruction is squashed in the IQ
204 SquashedInLSQ, /// Instruction is squashed in the LSQ
205 SquashedInROB, /// Instruction is squashed in the ROB
206 RecoverInst, /// Is a recover instruction
207 BlockingInst, /// Is a blocking instruction
208 ThreadsyncWait, /// Is a thread synchronization instruction
209 SerializeBefore, /// Needs to serialize on
210 /// instructions ahead of it
211 SerializeAfter, /// Needs to serialize instructions behind it
212 SerializeHandled, /// Serialization has been handled
213 NumStatus
214 };
215
216 /** The status of this BaseDynInst. Several bits can be set. */
217 std::bitset<NumStatus> status;
218
219 /** The thread this instruction is from. */
220 ThreadID threadNumber;
221
222 /** data address space ID, for loads & stores. */
223 short asid;
224
225 /** How many source registers are ready. */
226 unsigned readyRegs;
227
228 /** Pointer to the Impl's CPU object. */
229 ImplCPU *cpu;
230
231 /** Pointer to the thread state. */
232 ImplState *thread;
233
234 /** The kind of fault this instruction has generated. */
235 Fault fault;
236
237 /** Pointer to the data for the memory access. */
238 uint8_t *memData;
239
240 /** The effective virtual address (lds & stores only). */
241 Addr effAddr;
242
243 /** The size of the request */
244 Addr effSize;
245
246 /** Is the effective virtual address valid. */
247 bool effAddrValid;
248
249 /** The effective physical address. */
250 Addr physEffAddr;
251
252 /** The memory request flags (from translation). */
253 unsigned memReqFlags;
254
255 union Result {
256 uint64_t integer;
257 double dbl;
258 void set(uint64_t i) { integer = i; }
259 void set(double d) { dbl = d; }
260 void get(uint64_t& i) { i = integer; }
261 void get(double& d) { d = dbl; }
262 };
263
264 /** The result of the instruction; assumes an instruction can have many
265 * destination registers.
266 */
267 std::queue<Result> instResult;
268
269 /** Records changes to result? */
270 bool recordResult;
271
272 /** Did this instruction execute, or is it predicated false */
273 bool predicate;
274
275 protected:
276 /** PC state for this instruction. */
277 TheISA::PCState pc;
278
279 /** Predicted PC state after this instruction. */
280 TheISA::PCState predPC;
281
282 /** If this is a branch that was predicted taken */
283 bool predTaken;
284
285 public:
286
287#ifdef DEBUG
288 void dumpSNList();
289#endif
290
291 /** Whether or not the source register is ready.
292 * @todo: Not sure this should be here vs the derived class.
293 */
294 bool _readySrcRegIdx[MaxInstSrcRegs];
295
296 protected:
297 /** Flattened register index of the destination registers of this
298 * instruction.
299 */
300 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
301
302 /** Flattened register index of the source registers of this
303 * instruction.
304 */
305 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
306
307 /** Physical register index of the destination registers of this
308 * instruction.
309 */
310 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
311
312 /** Physical register index of the source registers of this
313 * instruction.
314 */
315 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
316
317 /** Physical register index of the previous producers of the
318 * architected destinations.
319 */
320 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
321
322 public:
323
324 /** Returns the physical register index of the i'th destination
325 * register.
326 */
327 PhysRegIndex renamedDestRegIdx(int idx) const
328 {
329 return _destRegIdx[idx];
330 }
331
332 /** Returns the physical register index of the i'th source register. */
333 PhysRegIndex renamedSrcRegIdx(int idx) const
334 {
335 return _srcRegIdx[idx];
336 }
337
338 /** Returns the flattened register index of the i'th destination
339 * register.
340 */
341 TheISA::RegIndex flattenedDestRegIdx(int idx) const
342 {
343 return _flatDestRegIdx[idx];
344 }
345
346 /** Returns the flattened register index of the i'th source register */
347 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
348 {
349 return _flatSrcRegIdx[idx];
350 }
351
352 /** Returns the physical register index of the previous physical register
353 * that remapped to the same logical register index.
354 */
355 PhysRegIndex prevDestRegIdx(int idx) const
356 {
357 return _prevDestRegIdx[idx];
358 }
359
360 /** Renames a destination register to a physical register. Also records
361 * the previous physical register that the logical register mapped to.
362 */
363 void renameDestReg(int idx,
364 PhysRegIndex renamed_dest,
365 PhysRegIndex previous_rename)
366 {
367 _destRegIdx[idx] = renamed_dest;
368 _prevDestRegIdx[idx] = previous_rename;
369 }
370
371 /** Renames a source logical register to the physical register which
372 * has/will produce that logical register's result.
373 * @todo: add in whether or not the source register is ready.
374 */
375 void renameSrcReg(int idx, PhysRegIndex renamed_src)
376 {
377 _srcRegIdx[idx] = renamed_src;
378 }
379
380 /** Flattens a source architectural register index into a logical index.
381 */
382 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
383 {
384 _flatSrcRegIdx[idx] = flattened_src;
385 }
386
387 /** Flattens a destination architectural register index into a logical
388 * index.
389 */
390 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
391 {
392 _flatDestRegIdx[idx] = flattened_dest;
393 }
394 /** BaseDynInst constructor given a binary instruction.
395 * @param staticInst A StaticInstPtr to the underlying instruction.
396 * @param pc The PC state for the instruction.
397 * @param predPC The predicted next PC state for the instruction.
398 * @param seq_num The sequence number of the instruction.
399 * @param cpu Pointer to the instruction's CPU.
400 */
401 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
402 TheISA::PCState pc, TheISA::PCState predPC,
403 InstSeqNum seq_num, ImplCPU *cpu);
404
405 /** BaseDynInst constructor given a StaticInst pointer.
406 * @param _staticInst The StaticInst for this BaseDynInst.
407 */
408 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
409
410 /** BaseDynInst destructor. */
411 ~BaseDynInst();
412
413 private:
414 /** Function to initialize variables in the constructors. */
415 void initVars();
416
417 public:
418 /** Dumps out contents of this BaseDynInst. */
419 void dump();
420
421 /** Dumps out contents of this BaseDynInst into given string. */
422 void dump(std::string &outstring);
423
424 /** Read this CPU's ID. */
425 int cpuId() { return cpu->cpuId(); }
426
427 /** Read this CPU's data requestor ID */
428 MasterID masterId() { return cpu->dataMasterId(); }
429
430 /** Read this context's system-wide ID **/
431 int contextId() { return thread->contextId(); }
432
433 /** Returns the fault type. */
434 Fault getFault() { return fault; }
435
436 /** Checks whether or not this instruction has had its branch target
437 * calculated yet. For now it is not utilized and is hacked to be
438 * always false.
439 * @todo: Actually use this instruction.
440 */
441 bool doneTargCalc() { return false; }
442
443 /** Set the predicted target of this current instruction. */
444 void setPredTarg(const TheISA::PCState &_predPC)
445 {
446 predPC = _predPC;
447 }
448
449 const TheISA::PCState &readPredTarg() { return predPC; }
450
451 /** Returns the predicted PC immediately after the branch. */
452 Addr predInstAddr() { return predPC.instAddr(); }
453
454 /** Returns the predicted PC two instructions after the branch */
455 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
456
457 /** Returns the predicted micro PC after the branch */
458 Addr predMicroPC() { return predPC.microPC(); }
459
460 /** Returns whether the instruction was predicted taken or not. */
461 bool readPredTaken()
462 {
463 return predTaken;
464 }
465
466 void setPredTaken(bool predicted_taken)
467 {
468 predTaken = predicted_taken;
469 }
470
471 /** Returns whether the instruction mispredicted. */
472 bool mispredicted()
473 {
474 TheISA::PCState tempPC = pc;
475 TheISA::advancePC(tempPC, staticInst);
476 return !(tempPC == predPC);
477 }
478
479 //
480 // Instruction types. Forward checks to StaticInst object.
481 //
482 bool isNop() const { return staticInst->isNop(); }
483 bool isMemRef() const { return staticInst->isMemRef(); }
484 bool isLoad() const { return staticInst->isLoad(); }
485 bool isStore() const { return staticInst->isStore(); }
486 bool isStoreConditional() const
487 { return staticInst->isStoreConditional(); }
488 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
489 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
490 bool isInteger() const { return staticInst->isInteger(); }
491 bool isFloating() const { return staticInst->isFloating(); }
492 bool isControl() const { return staticInst->isControl(); }
493 bool isCall() const { return staticInst->isCall(); }
494 bool isReturn() const { return staticInst->isReturn(); }
495 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
496 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
497 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
498 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
499 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
500 bool isThreadSync() const { return staticInst->isThreadSync(); }
501 bool isSerializing() const { return staticInst->isSerializing(); }
502 bool isSerializeBefore() const
503 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
504 bool isSerializeAfter() const
505 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
506 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
507 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
508 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
509 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
510 bool isQuiesce() const { return staticInst->isQuiesce(); }
511 bool isIprAccess() const { return staticInst->isIprAccess(); }
512 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
513 bool isSyscall() const { return staticInst->isSyscall(); }
514 bool isMacroop() const { return staticInst->isMacroop(); }
515 bool isMicroop() const { return staticInst->isMicroop(); }
516 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
517 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
518 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
519 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
520
521 /** Temporarily sets this instruction as a serialize before instruction. */
522 void setSerializeBefore() { status.set(SerializeBefore); }
523
524 /** Clears the serializeBefore part of this instruction. */
525 void clearSerializeBefore() { status.reset(SerializeBefore); }
526
527 /** Checks if this serializeBefore is only temporarily set. */
528 bool isTempSerializeBefore() { return status[SerializeBefore]; }
529
530 /** Temporarily sets this instruction as a serialize after instruction. */
531 void setSerializeAfter() { status.set(SerializeAfter); }
532
533 /** Clears the serializeAfter part of this instruction.*/
534 void clearSerializeAfter() { status.reset(SerializeAfter); }
535
536 /** Checks if this serializeAfter is only temporarily set. */
537 bool isTempSerializeAfter() { return status[SerializeAfter]; }
538
539 /** Sets the serialization part of this instruction as handled. */
540 void setSerializeHandled() { status.set(SerializeHandled); }
541
542 /** Checks if the serialization part of this instruction has been
543 * handled. This does not apply to the temporary serializing
544 * state; it only applies to this instruction's own permanent
545 * serializing state.
546 */
547 bool isSerializeHandled() { return status[SerializeHandled]; }
548
549 /** Returns the opclass of this instruction. */
550 OpClass opClass() const { return staticInst->opClass(); }
551
552 /** Returns the branch target address. */
553 TheISA::PCState branchTarget() const
554 { return staticInst->branchTarget(pc); }
555
556 /** Returns the number of source registers. */
557 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
558
559 /** Returns the number of destination registers. */
560 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
561
562 // the following are used to track physical register usage
563 // for machines with separate int & FP reg files
564 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
565 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
566
567 /** Returns the logical register index of the i'th destination register. */
568 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
569
570 /** Returns the logical register index of the i'th source register. */
571 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
572
573 /** Pops a result off the instResult queue */
574 template <class T>
575 void popResult(T& t)
576 {
577 if (!instResult.empty()) {
578 instResult.front().get(t);
579 instResult.pop();
580 }
581 }
582
583 /** Read the most recent result stored by this instruction */
584 template <class T>
585 void readResult(T& t)
586 {
587 instResult.back().get(t);
588 }
589
590 /** Pushes a result onto the instResult queue */
591 template <class T>
592 void setResult(T t)
593 {
594 if (recordResult) {
595 Result instRes;
596 instRes.set(t);
597 instResult.push(instRes);
598 }
599 }
600
601 /** Records an integer register being set to a value. */
602 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
603 {
604 setResult<uint64_t>(val);
605 }
606
607 /** Records an fp register being set to a value. */
608 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
609 int width)
610 {
611 if (width == 32 || width == 64) {
612 setResult<double>(val);
613 } else {
614 panic("Unsupported width!");
615 }
616 }
617
618 /** Records an fp register being set to a value. */
619 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
620 {
621 setResult<double>(val);
622 }
623
624 /** Records an fp register being set to an integer value. */
625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
626 int width)
627 {
628 setResult<uint64_t>(val);
629 }
630
631 /** Records an fp register being set to an integer value. */
632 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
633 {
634 setResult<uint64_t>(val);
635 }
636
637 /** Records that one of the source registers is ready. */
638 void markSrcRegReady();
639
640 /** Marks a specific register as ready. */
641 void markSrcRegReady(RegIndex src_idx);
642
643 /** Returns if a source register is ready. */
644 bool isReadySrcRegIdx(int idx) const
645 {
646 return this->_readySrcRegIdx[idx];
647 }
648
649 /** Sets this instruction as completed. */
650 void setCompleted() { status.set(Completed); }
651
652 /** Returns whether or not this instruction is completed. */
653 bool isCompleted() const { return status[Completed]; }
654
655 /** Marks the result as ready. */
656 void setResultReady() { status.set(ResultReady); }
657
658 /** Returns whether or not the result is ready. */
659 bool isResultReady() const { return status[ResultReady]; }
660
661 /** Sets this instruction as ready to issue. */
662 void setCanIssue() { status.set(CanIssue); }
663
664 /** Returns whether or not this instruction is ready to issue. */
665 bool readyToIssue() const { return status[CanIssue]; }
666
667 /** Clears this instruction being able to issue. */
668 void clearCanIssue() { status.reset(CanIssue); }
669
670 /** Sets this instruction as issued from the IQ. */
671 void setIssued() { status.set(Issued); }
672
673 /** Returns whether or not this instruction has issued. */
674 bool isIssued() const { return status[Issued]; }
675
676 /** Clears this instruction as being issued. */
677 void clearIssued() { status.reset(Issued); }
678
679 /** Sets this instruction as executed. */
680 void setExecuted() { status.set(Executed); }
681
682 /** Returns whether or not this instruction has executed. */
683 bool isExecuted() const { return status[Executed]; }
684
685 /** Sets this instruction as ready to commit. */
686 void setCanCommit() { status.set(CanCommit); }
687
688 /** Clears this instruction as being ready to commit. */
689 void clearCanCommit() { status.reset(CanCommit); }
690
691 /** Returns whether or not this instruction is ready to commit. */
692 bool readyToCommit() const { return status[CanCommit]; }
693
694 void setAtCommit() { status.set(AtCommit); }
695
696 bool isAtCommit() { return status[AtCommit]; }
697
698 /** Sets this instruction as committed. */
699 void setCommitted() { status.set(Committed); }
700
701 /** Returns whether or not this instruction is committed. */
702 bool isCommitted() const { return status[Committed]; }
703
704 /** Sets this instruction as squashed. */
705 void setSquashed() { status.set(Squashed); }
706
707 /** Returns whether or not this instruction is squashed. */
708 bool isSquashed() const { return status[Squashed]; }
709
710 //Instruction Queue Entry
711 //-----------------------
712 /** Sets this instruction as a entry the IQ. */
713 void setInIQ() { status.set(IqEntry); }
714
715 /** Sets this instruction as a entry the IQ. */
716 void clearInIQ() { status.reset(IqEntry); }
717
718 /** Returns whether or not this instruction has issued. */
719 bool isInIQ() const { return status[IqEntry]; }
720
721 /** Sets this instruction as squashed in the IQ. */
722 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
723
724 /** Returns whether or not this instruction is squashed in the IQ. */
725 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
726
727
728 //Load / Store Queue Functions
729 //-----------------------
730 /** Sets this instruction as a entry the LSQ. */
731 void setInLSQ() { status.set(LsqEntry); }
732
733 /** Sets this instruction as a entry the LSQ. */
734 void removeInLSQ() { status.reset(LsqEntry); }
735
736 /** Returns whether or not this instruction is in the LSQ. */
737 bool isInLSQ() const { return status[LsqEntry]; }
738
739 /** Sets this instruction as squashed in the LSQ. */
740 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
741
742 /** Returns whether or not this instruction is squashed in the LSQ. */
743 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
744
745
746 //Reorder Buffer Functions
747 //-----------------------
748 /** Sets this instruction as a entry the ROB. */
749 void setInROB() { status.set(RobEntry); }
750
751 /** Sets this instruction as a entry the ROB. */
752 void clearInROB() { status.reset(RobEntry); }
753
754 /** Returns whether or not this instruction is in the ROB. */
755 bool isInROB() const { return status[RobEntry]; }
756
757 /** Sets this instruction as squashed in the ROB. */
758 void setSquashedInROB() { status.set(SquashedInROB); }
759
760 /** Returns whether or not this instruction is squashed in the ROB. */
761 bool isSquashedInROB() const { return status[SquashedInROB]; }
762
763 /** Read the PC state of this instruction. */
764 const TheISA::PCState pcState() const { return pc; }
765
766 /** Set the PC state of this instruction. */
767 const void pcState(const TheISA::PCState &val) { pc = val; }
768
769 /** Read the PC of this instruction. */
770 const Addr instAddr() const { return pc.instAddr(); }
771
772 /** Read the PC of the next instruction. */
773 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
774
775 /**Read the micro PC of this instruction. */
776 const Addr microPC() const { return pc.microPC(); }
777
778 bool readPredicate()
779 {
780 return predicate;
781 }
782
783 void setPredicate(bool val)
784 {
785 predicate = val;
786
787 if (traceData) {
788 traceData->setPredicate(val);
789 }
790 }
791
792 /** Sets the ASID. */
793 void setASID(short addr_space_id) { asid = addr_space_id; }
794
795 /** Sets the thread id. */
796 void setTid(ThreadID tid) { threadNumber = tid; }
797
798 /** Sets the pointer to the thread state. */
799 void setThreadState(ImplState *state) { thread = state; }
800
801 /** Returns the thread context. */
802 ThreadContext *tcBase() { return thread->getTC(); }
803
804 private:
805 /** Instruction effective address.
806 * @todo: Consider if this is necessary or not.
807 */
808 Addr instEffAddr;
809
810 /** Whether or not the effective address calculation is completed.
811 * @todo: Consider if this is necessary or not.
812 */
813 bool eaCalcDone;
814
815 /** Is this instruction's memory access uncacheable. */
816 bool isUncacheable;
817
818 /** Has this instruction generated a memory request. */
819 bool reqMade;
820
821 public:
822 /** Sets the effective address. */
823 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
824
825 /** Returns the effective address. */
826 const Addr &getEA() const { return instEffAddr; }
827
828 /** Returns whether or not the eff. addr. calculation has been completed. */
829 bool doneEACalc() { return eaCalcDone; }
830
831 /** Returns whether or not the eff. addr. source registers are ready. */
832 bool eaSrcsReady();
833
834 /** Whether or not the memory operation is done. */
835 bool memOpDone;
836
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return isUncacheable; }
839
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return reqMade; }
842
843 public:
844 /** Load queue index. */
845 int16_t lqIdx;
846
847 /** Store queue index. */
848 int16_t sqIdx;
849
850 /** Iterator pointing to this BaseDynInst in the list of all insts. */
851 ListIt instListIt;
852
853 /** Returns iterator to this instruction in the list of all insts. */
854 ListIt &getInstListIt() { return instListIt; }
855
856 /** Sets iterator for this instruction in the list of all insts. */
857 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
858
859 public:
860 /** Returns the number of consecutive store conditional failures. */
861 unsigned readStCondFailures()
862 { return thread->storeCondFailures; }
863
864 /** Sets the number of consecutive store conditional failures. */
865 void setStCondFailures(unsigned sc_failures)
866 { thread->storeCondFailures = sc_failures; }
867};
868
869template<class Impl>
870Fault
871BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
872 unsigned size, unsigned flags)
873{
874 reqMade = true;
875 Request *req = NULL;
876 Request *sreqLow = NULL;
877 Request *sreqHigh = NULL;
878
879 if (reqMade && translationStarted) {
880 req = savedReq;
881 sreqLow = savedSreqLow;
882 sreqHigh = savedSreqHigh;
883 } else {
884 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
885 thread->contextId(), threadNumber);
886
887 // Only split the request if the ISA supports unaligned accesses.
888 if (TheISA::HasUnalignedMemAcc) {
889 splitRequest(req, sreqLow, sreqHigh);
890 }
891 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
892 }
893
894 if (translationCompleted) {
895 if (fault == NoFault) {
896 effAddr = req->getVaddr();
897 effSize = size;
898 effAddrValid = true;
899#if USE_CHECKER
900 if (reqToVerify != NULL) {
901 delete reqToVerify;
902 }
903 reqToVerify = new Request(*req);
904#endif //USE_CHECKER
905 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
906 } else {
907 // Commit will have to clean up whatever happened. Set this
908 // instruction as executed.
909 this->setExecuted();
910 }
911
912 if (fault != NoFault) {
913 // Return a fixed value to keep simulation deterministic even
914 // along misspeculated paths.
915 if (data)
916 bzero(data, size);
917 }
918 }
919
920 if (traceData) {
921 traceData->setAddr(addr);
922 }
923
924 return fault;
925}
926
927template<class Impl>
928Fault
929BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
930 Addr addr, unsigned flags, uint64_t *res)
931{
932 if (traceData) {
933 traceData->setAddr(addr);
934 }
935
936 reqMade = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (reqMade && translationStarted) {
942 req = savedReq;
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
945 } else {
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
947 thread->contextId(), threadNumber);
948
949 // Only split the request if the ISA supports unaligned accesses.
950 if (TheISA::HasUnalignedMemAcc) {
951 splitRequest(req, sreqLow, sreqHigh);
952 }
953 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
954 }
955
956 if (fault == NoFault && translationCompleted) {
957 effAddr = req->getVaddr();
958 effSize = size;
959 effAddrValid = true;
960#if USE_CHECKER
961 if (reqToVerify != NULL) {
962 delete reqToVerify;
963 }
964 reqToVerify = new Request(*req);
965#endif // USE_CHECKER
966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>
973inline void
974BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
975 RequestPtr &sreqHigh)
976{
977 // Check to see if the request crosses the next level block boundary.
|
979 Addr addr = req->getVaddr();
980 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
981 assert(split_addr <= addr || split_addr - addr < block_size);
982
983 // Spans two blocks.
984 if (split_addr > addr) {
985 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
986 }
987}
988
989template<class Impl>
990inline void
991BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
992 RequestPtr sreqHigh, uint64_t *res,
993 BaseTLB::Mode mode)
994{
995 translationStarted = true;
996
997 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
998 WholeTranslationState *state =
999 new WholeTranslationState(req, NULL, res, mode);
1000
1001 // One translation if the request isn't split.
1002 DataTranslation<BaseDynInstPtr> *trans =
1003 new DataTranslation<BaseDynInstPtr>(this, state);
1004 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1005 if (!translationCompleted) {
1006 // Save memory requests.
1007 savedReq = state->mainReq;
1008 savedSreqLow = state->sreqLow;
1009 savedSreqHigh = state->sreqHigh;
1010 }
1011 } else {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1014
1015 // Two translations when the request is split.
1016 DataTranslation<BaseDynInstPtr> *stransLow =
1017 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1018 DataTranslation<BaseDynInstPtr> *stransHigh =
1019 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1020
1021 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1022 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1023 if (!translationCompleted) {
1024 // Save memory requests.
1025 savedReq = state->mainReq;
1026 savedSreqLow = state->sreqLow;
1027 savedSreqHigh = state->sreqHigh;
1028 }
1029 }
1030}
1031
1032template<class Impl>
1033inline void
1034BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1035{
1036 fault = state->getFault();
1037
1038 if (state->isUncacheable())
1039 isUncacheable = true;
1040
1041 if (fault == NoFault) {
1042 physEffAddr = state->getPaddr();
1043 memReqFlags = state->getFlags();
1044
1045 if (state->mainReq->isCondSwap()) {
1046 assert(state->res);
1047 state->mainReq->setExtraData(*state->res);
1048 }
1049
1050 } else {
1051 state->deleteReqs();
1052 }
1053 delete state;
1054
1055 translationCompleted = true;
1056}
1057
1058#endif // __CPU_BASE_DYN_INST_HH__
| 979 Addr addr = req->getVaddr();
980 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
981 assert(split_addr <= addr || split_addr - addr < block_size);
982
983 // Spans two blocks.
984 if (split_addr > addr) {
985 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
986 }
987}
988
989template<class Impl>
990inline void
991BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
992 RequestPtr sreqHigh, uint64_t *res,
993 BaseTLB::Mode mode)
994{
995 translationStarted = true;
996
997 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
998 WholeTranslationState *state =
999 new WholeTranslationState(req, NULL, res, mode);
1000
1001 // One translation if the request isn't split.
1002 DataTranslation<BaseDynInstPtr> *trans =
1003 new DataTranslation<BaseDynInstPtr>(this, state);
1004 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1005 if (!translationCompleted) {
1006 // Save memory requests.
1007 savedReq = state->mainReq;
1008 savedSreqLow = state->sreqLow;
1009 savedSreqHigh = state->sreqHigh;
1010 }
1011 } else {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1014
1015 // Two translations when the request is split.
1016 DataTranslation<BaseDynInstPtr> *stransLow =
1017 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1018 DataTranslation<BaseDynInstPtr> *stransHigh =
1019 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1020
1021 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1022 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1023 if (!translationCompleted) {
1024 // Save memory requests.
1025 savedReq = state->mainReq;
1026 savedSreqLow = state->sreqLow;
1027 savedSreqHigh = state->sreqHigh;
1028 }
1029 }
1030}
1031
1032template<class Impl>
1033inline void
1034BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1035{
1036 fault = state->getFault();
1037
1038 if (state->isUncacheable())
1039 isUncacheable = true;
1040
1041 if (fault == NoFault) {
1042 physEffAddr = state->getPaddr();
1043 memReqFlags = state->getFlags();
1044
1045 if (state->mainReq->isCondSwap()) {
1046 assert(state->res);
1047 state->mainReq->setExtraData(*state->res);
1048 }
1049
1050 } else {
1051 state->deleteReqs();
1052 }
1053 delete state;
1054
1055 translationCompleted = true;
1056}
1057
1058#endif // __CPU_BASE_DYN_INST_HH__
|