1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Timothy M. Jones 31 */ 32 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" 41#include "base/fast_alloc.hh" 42#include "base/trace.hh" 43#include "config/full_system.hh" 44#include "config/the_isa.hh" 45#include "cpu/o3/comm.hh" 46#include "cpu/exetrace.hh" 47#include "cpu/inst_seq.hh" 48#include "cpu/op_class.hh" 49#include "cpu/static_inst.hh" 50#include "cpu/translation.hh" 51#include "mem/packet.hh" 52#include "sim/system.hh" 53#include "sim/tlb.hh" 54 55/** 56 * @file 57 * Defines a dynamic instruction context. 58 */ 59 60// Forward declaration. 61class StaticInstPtr; 62 63template <class Impl> 64class BaseDynInst : public FastAlloc, public RefCounted 65{ 66 public: 67 // Typedef for the CPU. 68 typedef typename Impl::CPUType ImplCPU; 69 typedef typename ImplCPU::ImplState ImplState; 70 71 // Logical register index type. 72 typedef TheISA::RegIndex RegIndex; 73 // Integer register type. 74 typedef TheISA::IntReg IntReg; 75 // Floating point register type. 76 typedef TheISA::FloatReg FloatReg; 77 78 // The DynInstPtr type. 79 typedef typename Impl::DynInstPtr DynInstPtr; 80 81 // The list of instructions iterator type. 82 typedef typename std::list<DynInstPtr>::iterator ListIt; 83 84 enum { 85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 86 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 87 }; 88 89 /** The StaticInst used by this BaseDynInst. */ 90 StaticInstPtr staticInst; 91 92 //////////////////////////////////////////// 93 // 94 // INSTRUCTION EXECUTION 95 // 96 //////////////////////////////////////////// 97 /** InstRecord that tracks this instructions. */ 98 Trace::InstRecord *traceData; 99 100 void demapPage(Addr vaddr, uint64_t asn) 101 { 102 cpu->demapPage(vaddr, asn); 103 } 104 void demapInstPage(Addr vaddr, uint64_t asn) 105 { 106 cpu->demapPage(vaddr, asn); 107 } 108 void demapDataPage(Addr vaddr, uint64_t asn) 109 { 110 cpu->demapPage(vaddr, asn); 111 } 112 113 /** 114 * Does a read to a given address. 115 * @param addr The address to read. 116 * @param data The read's data is written into this parameter. 117 * @param flags The request's flags. 118 * @return Returns any fault due to the read. 119 */ 120 template <class T> 121 Fault read(Addr addr, T &data, unsigned flags); 122 123 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 124 125 /** 126 * Does a write to a given address. 127 * @param data The data to be written. 128 * @param addr The address to write to. 129 * @param flags The request's flags. 130 * @param res The result of the write (for load locked/store conditionals). 131 * @return Returns any fault due to the write. 132 */ 133 template <class T> 134 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 135 136 Fault writeBytes(uint8_t *data, unsigned size, 137 Addr addr, unsigned flags, uint64_t *res); 138 139 /** Splits a request in two if it crosses a dcache block. */ 140 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 141 RequestPtr &sreqHigh); 142 143 /** Initiate a DTB address translation. */ 144 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 145 RequestPtr sreqHigh, uint64_t *res, 146 BaseTLB::Mode mode); 147 148 /** Finish a DTB address translation. */ 149 void finishTranslation(WholeTranslationState *state); 150 151 void prefetch(Addr addr, unsigned flags); 152 void writeHint(Addr addr, int size, unsigned flags); 153 Fault copySrcTranslate(Addr src); 154 Fault copy(Addr dest); 155 156 /** @todo: Consider making this private. */ 157 public: 158 /** The sequence number of the instruction. */ 159 InstSeqNum seqNum; 160 161 enum Status { 162 IqEntry, /// Instruction is in the IQ 163 RobEntry, /// Instruction is in the ROB 164 LsqEntry, /// Instruction is in the LSQ 165 Completed, /// Instruction has completed 166 ResultReady, /// Instruction has its result 167 CanIssue, /// Instruction can issue and execute 168 Issued, /// Instruction has issued 169 Executed, /// Instruction has executed 170 CanCommit, /// Instruction can commit 171 AtCommit, /// Instruction has reached commit 172 Committed, /// Instruction has committed 173 Squashed, /// Instruction is squashed 174 SquashedInIQ, /// Instruction is squashed in the IQ 175 SquashedInLSQ, /// Instruction is squashed in the LSQ 176 SquashedInROB, /// Instruction is squashed in the ROB 177 RecoverInst, /// Is a recover instruction 178 BlockingInst, /// Is a blocking instruction 179 ThreadsyncWait, /// Is a thread synchronization instruction 180 SerializeBefore, /// Needs to serialize on 181 /// instructions ahead of it 182 SerializeAfter, /// Needs to serialize instructions behind it 183 SerializeHandled, /// Serialization has been handled 184 NumStatus 185 }; 186 187 /** The status of this BaseDynInst. Several bits can be set. */ 188 std::bitset<NumStatus> status; 189 190 /** The thread this instruction is from. */ 191 ThreadID threadNumber; 192 193 /** data address space ID, for loads & stores. */ 194 short asid; 195 196 /** How many source registers are ready. */ 197 unsigned readyRegs; 198 199 /** Pointer to the Impl's CPU object. */ 200 ImplCPU *cpu; 201 202 /** Pointer to the thread state. */ 203 ImplState *thread; 204 205 /** The kind of fault this instruction has generated. */ 206 Fault fault; 207 208 /** Pointer to the data for the memory access. */ 209 uint8_t *memData; 210 211 /** The effective virtual address (lds & stores only). */ 212 Addr effAddr; 213 214 /** Is the effective virtual address valid. */ 215 bool effAddrValid; 216 217 /** The effective physical address. */ 218 Addr physEffAddr; 219 220 /** Effective virtual address for a copy source. */ 221 Addr copySrcEffAddr; 222 223 /** Effective physical address for a copy source. */ 224 Addr copySrcPhysEffAddr; 225 226 /** The memory request flags (from translation). */ 227 unsigned memReqFlags; 228 229 union Result { 230 uint64_t integer; 231// float fp; 232 double dbl; 233 }; 234 235 /** The result of the instruction; assumes for now that there's only one 236 * destination register. 237 */ 238 Result instResult; 239 240 /** Records changes to result? */ 241 bool recordResult; 242 243 /** PC of this instruction. */ 244 Addr PC; 245 246 /** Micro PC of this instruction. */ 247 Addr microPC; 248
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Kevin Lim 30 * Timothy M. Jones 31 */ 32 33#ifndef __CPU_BASE_DYN_INST_HH__ 34#define __CPU_BASE_DYN_INST_HH__ 35 36#include <bitset> 37#include <list> 38#include <string> 39 40#include "arch/faults.hh" 41#include "base/fast_alloc.hh" 42#include "base/trace.hh" 43#include "config/full_system.hh" 44#include "config/the_isa.hh" 45#include "cpu/o3/comm.hh" 46#include "cpu/exetrace.hh" 47#include "cpu/inst_seq.hh" 48#include "cpu/op_class.hh" 49#include "cpu/static_inst.hh" 50#include "cpu/translation.hh" 51#include "mem/packet.hh" 52#include "sim/system.hh" 53#include "sim/tlb.hh" 54 55/** 56 * @file 57 * Defines a dynamic instruction context. 58 */ 59 60// Forward declaration. 61class StaticInstPtr; 62 63template <class Impl> 64class BaseDynInst : public FastAlloc, public RefCounted 65{ 66 public: 67 // Typedef for the CPU. 68 typedef typename Impl::CPUType ImplCPU; 69 typedef typename ImplCPU::ImplState ImplState; 70 71 // Logical register index type. 72 typedef TheISA::RegIndex RegIndex; 73 // Integer register type. 74 typedef TheISA::IntReg IntReg; 75 // Floating point register type. 76 typedef TheISA::FloatReg FloatReg; 77 78 // The DynInstPtr type. 79 typedef typename Impl::DynInstPtr DynInstPtr; 80 81 // The list of instructions iterator type. 82 typedef typename std::list<DynInstPtr>::iterator ListIt; 83 84 enum { 85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs 86 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs 87 }; 88 89 /** The StaticInst used by this BaseDynInst. */ 90 StaticInstPtr staticInst; 91 92 //////////////////////////////////////////// 93 // 94 // INSTRUCTION EXECUTION 95 // 96 //////////////////////////////////////////// 97 /** InstRecord that tracks this instructions. */ 98 Trace::InstRecord *traceData; 99 100 void demapPage(Addr vaddr, uint64_t asn) 101 { 102 cpu->demapPage(vaddr, asn); 103 } 104 void demapInstPage(Addr vaddr, uint64_t asn) 105 { 106 cpu->demapPage(vaddr, asn); 107 } 108 void demapDataPage(Addr vaddr, uint64_t asn) 109 { 110 cpu->demapPage(vaddr, asn); 111 } 112 113 /** 114 * Does a read to a given address. 115 * @param addr The address to read. 116 * @param data The read's data is written into this parameter. 117 * @param flags The request's flags. 118 * @return Returns any fault due to the read. 119 */ 120 template <class T> 121 Fault read(Addr addr, T &data, unsigned flags); 122 123 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags); 124 125 /** 126 * Does a write to a given address. 127 * @param data The data to be written. 128 * @param addr The address to write to. 129 * @param flags The request's flags. 130 * @param res The result of the write (for load locked/store conditionals). 131 * @return Returns any fault due to the write. 132 */ 133 template <class T> 134 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 135 136 Fault writeBytes(uint8_t *data, unsigned size, 137 Addr addr, unsigned flags, uint64_t *res); 138 139 /** Splits a request in two if it crosses a dcache block. */ 140 void splitRequest(RequestPtr req, RequestPtr &sreqLow, 141 RequestPtr &sreqHigh); 142 143 /** Initiate a DTB address translation. */ 144 void initiateTranslation(RequestPtr req, RequestPtr sreqLow, 145 RequestPtr sreqHigh, uint64_t *res, 146 BaseTLB::Mode mode); 147 148 /** Finish a DTB address translation. */ 149 void finishTranslation(WholeTranslationState *state); 150 151 void prefetch(Addr addr, unsigned flags); 152 void writeHint(Addr addr, int size, unsigned flags); 153 Fault copySrcTranslate(Addr src); 154 Fault copy(Addr dest); 155 156 /** @todo: Consider making this private. */ 157 public: 158 /** The sequence number of the instruction. */ 159 InstSeqNum seqNum; 160 161 enum Status { 162 IqEntry, /// Instruction is in the IQ 163 RobEntry, /// Instruction is in the ROB 164 LsqEntry, /// Instruction is in the LSQ 165 Completed, /// Instruction has completed 166 ResultReady, /// Instruction has its result 167 CanIssue, /// Instruction can issue and execute 168 Issued, /// Instruction has issued 169 Executed, /// Instruction has executed 170 CanCommit, /// Instruction can commit 171 AtCommit, /// Instruction has reached commit 172 Committed, /// Instruction has committed 173 Squashed, /// Instruction is squashed 174 SquashedInIQ, /// Instruction is squashed in the IQ 175 SquashedInLSQ, /// Instruction is squashed in the LSQ 176 SquashedInROB, /// Instruction is squashed in the ROB 177 RecoverInst, /// Is a recover instruction 178 BlockingInst, /// Is a blocking instruction 179 ThreadsyncWait, /// Is a thread synchronization instruction 180 SerializeBefore, /// Needs to serialize on 181 /// instructions ahead of it 182 SerializeAfter, /// Needs to serialize instructions behind it 183 SerializeHandled, /// Serialization has been handled 184 NumStatus 185 }; 186 187 /** The status of this BaseDynInst. Several bits can be set. */ 188 std::bitset<NumStatus> status; 189 190 /** The thread this instruction is from. */ 191 ThreadID threadNumber; 192 193 /** data address space ID, for loads & stores. */ 194 short asid; 195 196 /** How many source registers are ready. */ 197 unsigned readyRegs; 198 199 /** Pointer to the Impl's CPU object. */ 200 ImplCPU *cpu; 201 202 /** Pointer to the thread state. */ 203 ImplState *thread; 204 205 /** The kind of fault this instruction has generated. */ 206 Fault fault; 207 208 /** Pointer to the data for the memory access. */ 209 uint8_t *memData; 210 211 /** The effective virtual address (lds & stores only). */ 212 Addr effAddr; 213 214 /** Is the effective virtual address valid. */ 215 bool effAddrValid; 216 217 /** The effective physical address. */ 218 Addr physEffAddr; 219 220 /** Effective virtual address for a copy source. */ 221 Addr copySrcEffAddr; 222 223 /** Effective physical address for a copy source. */ 224 Addr copySrcPhysEffAddr; 225 226 /** The memory request flags (from translation). */ 227 unsigned memReqFlags; 228 229 union Result { 230 uint64_t integer; 231// float fp; 232 double dbl; 233 }; 234 235 /** The result of the instruction; assumes for now that there's only one 236 * destination register. 237 */ 238 Result instResult; 239 240 /** Records changes to result? */ 241 bool recordResult; 242 243 /** PC of this instruction. */ 244 Addr PC; 245 246 /** Micro PC of this instruction. */ 247 Addr microPC; 248
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| 249 /** Did this instruction execute, or is it predicated false */ 250 bool predicate; 251
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249 protected: 250 /** Next non-speculative PC. It is not filled in at fetch, but rather 251 * once the target of the branch is truly known (either decode or 252 * execute). 253 */ 254 Addr nextPC; 255 256 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 257 Addr nextNPC; 258 259 /** Next non-speculative micro PC. */ 260 Addr nextMicroPC; 261 262 /** Predicted next PC. */ 263 Addr predPC; 264 265 /** Predicted next NPC. */ 266 Addr predNPC; 267 268 /** Predicted next microPC */ 269 Addr predMicroPC; 270 271 /** If this is a branch that was predicted taken */ 272 bool predTaken; 273 274 public: 275 276#ifdef DEBUG 277 void dumpSNList(); 278#endif 279 280 /** Whether or not the source register is ready. 281 * @todo: Not sure this should be here vs the derived class. 282 */ 283 bool _readySrcRegIdx[MaxInstSrcRegs]; 284 285 protected: 286 /** Flattened register index of the destination registers of this 287 * instruction. 288 */ 289 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 290 291 /** Flattened register index of the source registers of this 292 * instruction. 293 */ 294 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 295 296 /** Physical register index of the destination registers of this 297 * instruction. 298 */ 299 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 300 301 /** Physical register index of the source registers of this 302 * instruction. 303 */ 304 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 305 306 /** Physical register index of the previous producers of the 307 * architected destinations. 308 */ 309 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 310 311 public: 312 313 /** Returns the physical register index of the i'th destination 314 * register. 315 */ 316 PhysRegIndex renamedDestRegIdx(int idx) const 317 { 318 return _destRegIdx[idx]; 319 } 320 321 /** Returns the physical register index of the i'th source register. */ 322 PhysRegIndex renamedSrcRegIdx(int idx) const 323 { 324 return _srcRegIdx[idx]; 325 } 326 327 /** Returns the flattened register index of the i'th destination 328 * register. 329 */ 330 TheISA::RegIndex flattenedDestRegIdx(int idx) const 331 { 332 return _flatDestRegIdx[idx]; 333 } 334 335 /** Returns the flattened register index of the i'th source register */ 336 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 337 { 338 return _flatSrcRegIdx[idx]; 339 } 340 341 /** Returns the physical register index of the previous physical register 342 * that remapped to the same logical register index. 343 */ 344 PhysRegIndex prevDestRegIdx(int idx) const 345 { 346 return _prevDestRegIdx[idx]; 347 } 348 349 /** Renames a destination register to a physical register. Also records 350 * the previous physical register that the logical register mapped to. 351 */ 352 void renameDestReg(int idx, 353 PhysRegIndex renamed_dest, 354 PhysRegIndex previous_rename) 355 { 356 _destRegIdx[idx] = renamed_dest; 357 _prevDestRegIdx[idx] = previous_rename; 358 } 359 360 /** Renames a source logical register to the physical register which 361 * has/will produce that logical register's result. 362 * @todo: add in whether or not the source register is ready. 363 */ 364 void renameSrcReg(int idx, PhysRegIndex renamed_src) 365 { 366 _srcRegIdx[idx] = renamed_src; 367 } 368 369 /** Flattens a source architectural register index into a logical index. 370 */ 371 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 372 { 373 _flatSrcRegIdx[idx] = flattened_src; 374 } 375 376 /** Flattens a destination architectural register index into a logical 377 * index. 378 */ 379 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 380 { 381 _flatDestRegIdx[idx] = flattened_dest; 382 } 383 /** BaseDynInst constructor given a binary instruction. 384 * @param staticInst A StaticInstPtr to the underlying instruction. 385 * @param PC The PC of the instruction. 386 * @param pred_PC The predicted next PC. 387 * @param pred_NPC The predicted next NPC. 388 * @param seq_num The sequence number of the instruction. 389 * @param cpu Pointer to the instruction's CPU. 390 */ 391 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 392 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 393 InstSeqNum seq_num, ImplCPU *cpu); 394 395 /** BaseDynInst constructor given a binary instruction. 396 * @param inst The binary instruction. 397 * @param PC The PC of the instruction. 398 * @param pred_PC The predicted next PC. 399 * @param pred_NPC The predicted next NPC. 400 * @param seq_num The sequence number of the instruction. 401 * @param cpu Pointer to the instruction's CPU. 402 */ 403 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 404 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 405 InstSeqNum seq_num, ImplCPU *cpu); 406 407 /** BaseDynInst constructor given a StaticInst pointer. 408 * @param _staticInst The StaticInst for this BaseDynInst. 409 */ 410 BaseDynInst(StaticInstPtr &_staticInst); 411 412 /** BaseDynInst destructor. */ 413 ~BaseDynInst(); 414 415 private: 416 /** Function to initialize variables in the constructors. */ 417 void initVars(); 418 419 public: 420 /** Dumps out contents of this BaseDynInst. */ 421 void dump(); 422 423 /** Dumps out contents of this BaseDynInst into given string. */ 424 void dump(std::string &outstring); 425 426 /** Read this CPU's ID. */ 427 int cpuId() { return cpu->cpuId(); } 428 429 /** Read this context's system-wide ID **/ 430 int contextId() { return thread->contextId(); } 431 432 /** Returns the fault type. */ 433 Fault getFault() { return fault; } 434 435 /** Checks whether or not this instruction has had its branch target 436 * calculated yet. For now it is not utilized and is hacked to be 437 * always false. 438 * @todo: Actually use this instruction. 439 */ 440 bool doneTargCalc() { return false; } 441 442 /** Returns the next PC. This could be the speculative next PC if it is 443 * called prior to the actual branch target being calculated. 444 */ 445 Addr readNextPC() { return nextPC; } 446 447 /** Returns the next NPC. This could be the speculative next NPC if it is 448 * called prior to the actual branch target being calculated. 449 */ 450 Addr readNextNPC() 451 { 452#if ISA_HAS_DELAY_SLOT 453 return nextNPC; 454#else 455 return nextPC + sizeof(TheISA::MachInst); 456#endif 457 } 458 459 Addr readNextMicroPC() 460 { 461 return nextMicroPC; 462 } 463 464 /** Set the predicted target of this current instruction. */ 465 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 466 Addr predicted_MicroPC) 467 { 468 predPC = predicted_PC; 469 predNPC = predicted_NPC; 470 predMicroPC = predicted_MicroPC; 471 } 472 473 /** Returns the predicted PC immediately after the branch. */ 474 Addr readPredPC() { return predPC; } 475 476 /** Returns the predicted PC two instructions after the branch */ 477 Addr readPredNPC() { return predNPC; } 478 479 /** Returns the predicted micro PC after the branch */ 480 Addr readPredMicroPC() { return predMicroPC; } 481 482 /** Returns whether the instruction was predicted taken or not. */ 483 bool readPredTaken() 484 { 485 return predTaken; 486 } 487 488 void setPredTaken(bool predicted_taken) 489 { 490 predTaken = predicted_taken; 491 } 492 493 /** Returns whether the instruction mispredicted. */ 494 bool mispredicted() 495 { 496 return readPredPC() != readNextPC() || 497 readPredNPC() != readNextNPC() || 498 readPredMicroPC() != readNextMicroPC(); 499 } 500 501 // 502 // Instruction types. Forward checks to StaticInst object. 503 // 504 bool isNop() const { return staticInst->isNop(); } 505 bool isMemRef() const { return staticInst->isMemRef(); } 506 bool isLoad() const { return staticInst->isLoad(); } 507 bool isStore() const { return staticInst->isStore(); } 508 bool isStoreConditional() const 509 { return staticInst->isStoreConditional(); } 510 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 511 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 512 bool isCopy() const { return staticInst->isCopy(); } 513 bool isInteger() const { return staticInst->isInteger(); } 514 bool isFloating() const { return staticInst->isFloating(); } 515 bool isControl() const { return staticInst->isControl(); } 516 bool isCall() const { return staticInst->isCall(); } 517 bool isReturn() const { return staticInst->isReturn(); } 518 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 519 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 520 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 521 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 522 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 523 bool isThreadSync() const { return staticInst->isThreadSync(); } 524 bool isSerializing() const { return staticInst->isSerializing(); } 525 bool isSerializeBefore() const 526 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 527 bool isSerializeAfter() const 528 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 529 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 530 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 531 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 532 bool isQuiesce() const { return staticInst->isQuiesce(); } 533 bool isIprAccess() const { return staticInst->isIprAccess(); } 534 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 535 bool isSyscall() const { return staticInst->isSyscall(); } 536 bool isMacroop() const { return staticInst->isMacroop(); } 537 bool isMicroop() const { return staticInst->isMicroop(); } 538 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 539 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 540 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 541 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 542 543 /** Temporarily sets this instruction as a serialize before instruction. */ 544 void setSerializeBefore() { status.set(SerializeBefore); } 545 546 /** Clears the serializeBefore part of this instruction. */ 547 void clearSerializeBefore() { status.reset(SerializeBefore); } 548 549 /** Checks if this serializeBefore is only temporarily set. */ 550 bool isTempSerializeBefore() { return status[SerializeBefore]; } 551 552 /** Temporarily sets this instruction as a serialize after instruction. */ 553 void setSerializeAfter() { status.set(SerializeAfter); } 554 555 /** Clears the serializeAfter part of this instruction.*/ 556 void clearSerializeAfter() { status.reset(SerializeAfter); } 557 558 /** Checks if this serializeAfter is only temporarily set. */ 559 bool isTempSerializeAfter() { return status[SerializeAfter]; } 560 561 /** Sets the serialization part of this instruction as handled. */ 562 void setSerializeHandled() { status.set(SerializeHandled); } 563 564 /** Checks if the serialization part of this instruction has been 565 * handled. This does not apply to the temporary serializing 566 * state; it only applies to this instruction's own permanent 567 * serializing state. 568 */ 569 bool isSerializeHandled() { return status[SerializeHandled]; } 570 571 /** Returns the opclass of this instruction. */ 572 OpClass opClass() const { return staticInst->opClass(); } 573 574 /** Returns the branch target address. */ 575 Addr branchTarget() const { return staticInst->branchTarget(PC); } 576 577 /** Returns the number of source registers. */ 578 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 579 580 /** Returns the number of destination registers. */ 581 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 582 583 // the following are used to track physical register usage 584 // for machines with separate int & FP reg files 585 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 586 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 587 588 /** Returns the logical register index of the i'th destination register. */ 589 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 590 591 /** Returns the logical register index of the i'th source register. */ 592 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 593 594 /** Returns the result of an integer instruction. */ 595 uint64_t readIntResult() { return instResult.integer; } 596 597 /** Returns the result of a floating point instruction. */ 598 float readFloatResult() { return (float)instResult.dbl; } 599 600 /** Returns the result of a floating point (double) instruction. */ 601 double readDoubleResult() { return instResult.dbl; } 602 603 /** Records an integer register being set to a value. */ 604 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 605 { 606 if (recordResult) 607 instResult.integer = val; 608 } 609 610 /** Records an fp register being set to a value. */ 611 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 612 int width) 613 { 614 if (recordResult) { 615 if (width == 32) 616 instResult.dbl = (double)val; 617 else if (width == 64) 618 instResult.dbl = val; 619 else 620 panic("Unsupported width!"); 621 } 622 } 623 624 /** Records an fp register being set to a value. */ 625 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 626 { 627 if (recordResult) 628 instResult.dbl = (double)val; 629 } 630 631 /** Records an fp register being set to an integer value. */ 632 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 633 int width) 634 { 635 if (recordResult) 636 instResult.integer = val; 637 } 638 639 /** Records an fp register being set to an integer value. */ 640 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 641 { 642 if (recordResult) 643 instResult.integer = val; 644 } 645 646 /** Records that one of the source registers is ready. */ 647 void markSrcRegReady(); 648 649 /** Marks a specific register as ready. */ 650 void markSrcRegReady(RegIndex src_idx); 651 652 /** Returns if a source register is ready. */ 653 bool isReadySrcRegIdx(int idx) const 654 { 655 return this->_readySrcRegIdx[idx]; 656 } 657 658 /** Sets this instruction as completed. */ 659 void setCompleted() { status.set(Completed); } 660 661 /** Returns whether or not this instruction is completed. */ 662 bool isCompleted() const { return status[Completed]; } 663 664 /** Marks the result as ready. */ 665 void setResultReady() { status.set(ResultReady); } 666 667 /** Returns whether or not the result is ready. */ 668 bool isResultReady() const { return status[ResultReady]; } 669 670 /** Sets this instruction as ready to issue. */ 671 void setCanIssue() { status.set(CanIssue); } 672 673 /** Returns whether or not this instruction is ready to issue. */ 674 bool readyToIssue() const { return status[CanIssue]; } 675 676 /** Clears this instruction being able to issue. */ 677 void clearCanIssue() { status.reset(CanIssue); } 678 679 /** Sets this instruction as issued from the IQ. */ 680 void setIssued() { status.set(Issued); } 681 682 /** Returns whether or not this instruction has issued. */ 683 bool isIssued() const { return status[Issued]; } 684 685 /** Clears this instruction as being issued. */ 686 void clearIssued() { status.reset(Issued); } 687 688 /** Sets this instruction as executed. */ 689 void setExecuted() { status.set(Executed); } 690 691 /** Returns whether or not this instruction has executed. */ 692 bool isExecuted() const { return status[Executed]; } 693 694 /** Sets this instruction as ready to commit. */ 695 void setCanCommit() { status.set(CanCommit); } 696 697 /** Clears this instruction as being ready to commit. */ 698 void clearCanCommit() { status.reset(CanCommit); } 699 700 /** Returns whether or not this instruction is ready to commit. */ 701 bool readyToCommit() const { return status[CanCommit]; } 702 703 void setAtCommit() { status.set(AtCommit); } 704 705 bool isAtCommit() { return status[AtCommit]; } 706 707 /** Sets this instruction as committed. */ 708 void setCommitted() { status.set(Committed); } 709 710 /** Returns whether or not this instruction is committed. */ 711 bool isCommitted() const { return status[Committed]; } 712 713 /** Sets this instruction as squashed. */ 714 void setSquashed() { status.set(Squashed); } 715 716 /** Returns whether or not this instruction is squashed. */ 717 bool isSquashed() const { return status[Squashed]; } 718 719 //Instruction Queue Entry 720 //----------------------- 721 /** Sets this instruction as a entry the IQ. */ 722 void setInIQ() { status.set(IqEntry); } 723 724 /** Sets this instruction as a entry the IQ. */ 725 void clearInIQ() { status.reset(IqEntry); } 726 727 /** Returns whether or not this instruction has issued. */ 728 bool isInIQ() const { return status[IqEntry]; } 729 730 /** Sets this instruction as squashed in the IQ. */ 731 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 732 733 /** Returns whether or not this instruction is squashed in the IQ. */ 734 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 735 736 737 //Load / Store Queue Functions 738 //----------------------- 739 /** Sets this instruction as a entry the LSQ. */ 740 void setInLSQ() { status.set(LsqEntry); } 741 742 /** Sets this instruction as a entry the LSQ. */ 743 void removeInLSQ() { status.reset(LsqEntry); } 744 745 /** Returns whether or not this instruction is in the LSQ. */ 746 bool isInLSQ() const { return status[LsqEntry]; } 747 748 /** Sets this instruction as squashed in the LSQ. */ 749 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 750 751 /** Returns whether or not this instruction is squashed in the LSQ. */ 752 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 753 754 755 //Reorder Buffer Functions 756 //----------------------- 757 /** Sets this instruction as a entry the ROB. */ 758 void setInROB() { status.set(RobEntry); } 759 760 /** Sets this instruction as a entry the ROB. */ 761 void clearInROB() { status.reset(RobEntry); } 762 763 /** Returns whether or not this instruction is in the ROB. */ 764 bool isInROB() const { return status[RobEntry]; } 765 766 /** Sets this instruction as squashed in the ROB. */ 767 void setSquashedInROB() { status.set(SquashedInROB); } 768 769 /** Returns whether or not this instruction is squashed in the ROB. */ 770 bool isSquashedInROB() const { return status[SquashedInROB]; } 771 772 /** Read the PC of this instruction. */ 773 const Addr readPC() const { return PC; } 774 775 /**Read the micro PC of this instruction. */ 776 const Addr readMicroPC() const { return microPC; } 777 778 /** Set the next PC of this instruction (its actual target). */ 779 void setNextPC(Addr val) 780 { 781 nextPC = val; 782 } 783 784 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 785 void setNextNPC(Addr val) 786 { 787#if ISA_HAS_DELAY_SLOT 788 nextNPC = val; 789#endif 790 } 791 792 void setNextMicroPC(Addr val) 793 { 794 nextMicroPC = val; 795 } 796
| 252 protected: 253 /** Next non-speculative PC. It is not filled in at fetch, but rather 254 * once the target of the branch is truly known (either decode or 255 * execute). 256 */ 257 Addr nextPC; 258 259 /** Next non-speculative NPC. Target PC for Mips or Sparc. */ 260 Addr nextNPC; 261 262 /** Next non-speculative micro PC. */ 263 Addr nextMicroPC; 264 265 /** Predicted next PC. */ 266 Addr predPC; 267 268 /** Predicted next NPC. */ 269 Addr predNPC; 270 271 /** Predicted next microPC */ 272 Addr predMicroPC; 273 274 /** If this is a branch that was predicted taken */ 275 bool predTaken; 276 277 public: 278 279#ifdef DEBUG 280 void dumpSNList(); 281#endif 282 283 /** Whether or not the source register is ready. 284 * @todo: Not sure this should be here vs the derived class. 285 */ 286 bool _readySrcRegIdx[MaxInstSrcRegs]; 287 288 protected: 289 /** Flattened register index of the destination registers of this 290 * instruction. 291 */ 292 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs]; 293 294 /** Flattened register index of the source registers of this 295 * instruction. 296 */ 297 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs]; 298 299 /** Physical register index of the destination registers of this 300 * instruction. 301 */ 302 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs]; 303 304 /** Physical register index of the source registers of this 305 * instruction. 306 */ 307 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs]; 308 309 /** Physical register index of the previous producers of the 310 * architected destinations. 311 */ 312 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs]; 313 314 public: 315 316 /** Returns the physical register index of the i'th destination 317 * register. 318 */ 319 PhysRegIndex renamedDestRegIdx(int idx) const 320 { 321 return _destRegIdx[idx]; 322 } 323 324 /** Returns the physical register index of the i'th source register. */ 325 PhysRegIndex renamedSrcRegIdx(int idx) const 326 { 327 return _srcRegIdx[idx]; 328 } 329 330 /** Returns the flattened register index of the i'th destination 331 * register. 332 */ 333 TheISA::RegIndex flattenedDestRegIdx(int idx) const 334 { 335 return _flatDestRegIdx[idx]; 336 } 337 338 /** Returns the flattened register index of the i'th source register */ 339 TheISA::RegIndex flattenedSrcRegIdx(int idx) const 340 { 341 return _flatSrcRegIdx[idx]; 342 } 343 344 /** Returns the physical register index of the previous physical register 345 * that remapped to the same logical register index. 346 */ 347 PhysRegIndex prevDestRegIdx(int idx) const 348 { 349 return _prevDestRegIdx[idx]; 350 } 351 352 /** Renames a destination register to a physical register. Also records 353 * the previous physical register that the logical register mapped to. 354 */ 355 void renameDestReg(int idx, 356 PhysRegIndex renamed_dest, 357 PhysRegIndex previous_rename) 358 { 359 _destRegIdx[idx] = renamed_dest; 360 _prevDestRegIdx[idx] = previous_rename; 361 } 362 363 /** Renames a source logical register to the physical register which 364 * has/will produce that logical register's result. 365 * @todo: add in whether or not the source register is ready. 366 */ 367 void renameSrcReg(int idx, PhysRegIndex renamed_src) 368 { 369 _srcRegIdx[idx] = renamed_src; 370 } 371 372 /** Flattens a source architectural register index into a logical index. 373 */ 374 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src) 375 { 376 _flatSrcRegIdx[idx] = flattened_src; 377 } 378 379 /** Flattens a destination architectural register index into a logical 380 * index. 381 */ 382 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest) 383 { 384 _flatDestRegIdx[idx] = flattened_dest; 385 } 386 /** BaseDynInst constructor given a binary instruction. 387 * @param staticInst A StaticInstPtr to the underlying instruction. 388 * @param PC The PC of the instruction. 389 * @param pred_PC The predicted next PC. 390 * @param pred_NPC The predicted next NPC. 391 * @param seq_num The sequence number of the instruction. 392 * @param cpu Pointer to the instruction's CPU. 393 */ 394 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC, 395 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 396 InstSeqNum seq_num, ImplCPU *cpu); 397 398 /** BaseDynInst constructor given a binary instruction. 399 * @param inst The binary instruction. 400 * @param PC The PC of the instruction. 401 * @param pred_PC The predicted next PC. 402 * @param pred_NPC The predicted next NPC. 403 * @param seq_num The sequence number of the instruction. 404 * @param cpu Pointer to the instruction's CPU. 405 */ 406 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC, 407 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC, 408 InstSeqNum seq_num, ImplCPU *cpu); 409 410 /** BaseDynInst constructor given a StaticInst pointer. 411 * @param _staticInst The StaticInst for this BaseDynInst. 412 */ 413 BaseDynInst(StaticInstPtr &_staticInst); 414 415 /** BaseDynInst destructor. */ 416 ~BaseDynInst(); 417 418 private: 419 /** Function to initialize variables in the constructors. */ 420 void initVars(); 421 422 public: 423 /** Dumps out contents of this BaseDynInst. */ 424 void dump(); 425 426 /** Dumps out contents of this BaseDynInst into given string. */ 427 void dump(std::string &outstring); 428 429 /** Read this CPU's ID. */ 430 int cpuId() { return cpu->cpuId(); } 431 432 /** Read this context's system-wide ID **/ 433 int contextId() { return thread->contextId(); } 434 435 /** Returns the fault type. */ 436 Fault getFault() { return fault; } 437 438 /** Checks whether or not this instruction has had its branch target 439 * calculated yet. For now it is not utilized and is hacked to be 440 * always false. 441 * @todo: Actually use this instruction. 442 */ 443 bool doneTargCalc() { return false; } 444 445 /** Returns the next PC. This could be the speculative next PC if it is 446 * called prior to the actual branch target being calculated. 447 */ 448 Addr readNextPC() { return nextPC; } 449 450 /** Returns the next NPC. This could be the speculative next NPC if it is 451 * called prior to the actual branch target being calculated. 452 */ 453 Addr readNextNPC() 454 { 455#if ISA_HAS_DELAY_SLOT 456 return nextNPC; 457#else 458 return nextPC + sizeof(TheISA::MachInst); 459#endif 460 } 461 462 Addr readNextMicroPC() 463 { 464 return nextMicroPC; 465 } 466 467 /** Set the predicted target of this current instruction. */ 468 void setPredTarg(Addr predicted_PC, Addr predicted_NPC, 469 Addr predicted_MicroPC) 470 { 471 predPC = predicted_PC; 472 predNPC = predicted_NPC; 473 predMicroPC = predicted_MicroPC; 474 } 475 476 /** Returns the predicted PC immediately after the branch. */ 477 Addr readPredPC() { return predPC; } 478 479 /** Returns the predicted PC two instructions after the branch */ 480 Addr readPredNPC() { return predNPC; } 481 482 /** Returns the predicted micro PC after the branch */ 483 Addr readPredMicroPC() { return predMicroPC; } 484 485 /** Returns whether the instruction was predicted taken or not. */ 486 bool readPredTaken() 487 { 488 return predTaken; 489 } 490 491 void setPredTaken(bool predicted_taken) 492 { 493 predTaken = predicted_taken; 494 } 495 496 /** Returns whether the instruction mispredicted. */ 497 bool mispredicted() 498 { 499 return readPredPC() != readNextPC() || 500 readPredNPC() != readNextNPC() || 501 readPredMicroPC() != readNextMicroPC(); 502 } 503 504 // 505 // Instruction types. Forward checks to StaticInst object. 506 // 507 bool isNop() const { return staticInst->isNop(); } 508 bool isMemRef() const { return staticInst->isMemRef(); } 509 bool isLoad() const { return staticInst->isLoad(); } 510 bool isStore() const { return staticInst->isStore(); } 511 bool isStoreConditional() const 512 { return staticInst->isStoreConditional(); } 513 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } 514 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } 515 bool isCopy() const { return staticInst->isCopy(); } 516 bool isInteger() const { return staticInst->isInteger(); } 517 bool isFloating() const { return staticInst->isFloating(); } 518 bool isControl() const { return staticInst->isControl(); } 519 bool isCall() const { return staticInst->isCall(); } 520 bool isReturn() const { return staticInst->isReturn(); } 521 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } 522 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } 523 bool isCondCtrl() const { return staticInst->isCondCtrl(); } 524 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } 525 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } 526 bool isThreadSync() const { return staticInst->isThreadSync(); } 527 bool isSerializing() const { return staticInst->isSerializing(); } 528 bool isSerializeBefore() const 529 { return staticInst->isSerializeBefore() || status[SerializeBefore]; } 530 bool isSerializeAfter() const 531 { return staticInst->isSerializeAfter() || status[SerializeAfter]; } 532 bool isMemBarrier() const { return staticInst->isMemBarrier(); } 533 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } 534 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } 535 bool isQuiesce() const { return staticInst->isQuiesce(); } 536 bool isIprAccess() const { return staticInst->isIprAccess(); } 537 bool isUnverifiable() const { return staticInst->isUnverifiable(); } 538 bool isSyscall() const { return staticInst->isSyscall(); } 539 bool isMacroop() const { return staticInst->isMacroop(); } 540 bool isMicroop() const { return staticInst->isMicroop(); } 541 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); } 542 bool isLastMicroop() const { return staticInst->isLastMicroop(); } 543 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); } 544 bool isMicroBranch() const { return staticInst->isMicroBranch(); } 545 546 /** Temporarily sets this instruction as a serialize before instruction. */ 547 void setSerializeBefore() { status.set(SerializeBefore); } 548 549 /** Clears the serializeBefore part of this instruction. */ 550 void clearSerializeBefore() { status.reset(SerializeBefore); } 551 552 /** Checks if this serializeBefore is only temporarily set. */ 553 bool isTempSerializeBefore() { return status[SerializeBefore]; } 554 555 /** Temporarily sets this instruction as a serialize after instruction. */ 556 void setSerializeAfter() { status.set(SerializeAfter); } 557 558 /** Clears the serializeAfter part of this instruction.*/ 559 void clearSerializeAfter() { status.reset(SerializeAfter); } 560 561 /** Checks if this serializeAfter is only temporarily set. */ 562 bool isTempSerializeAfter() { return status[SerializeAfter]; } 563 564 /** Sets the serialization part of this instruction as handled. */ 565 void setSerializeHandled() { status.set(SerializeHandled); } 566 567 /** Checks if the serialization part of this instruction has been 568 * handled. This does not apply to the temporary serializing 569 * state; it only applies to this instruction's own permanent 570 * serializing state. 571 */ 572 bool isSerializeHandled() { return status[SerializeHandled]; } 573 574 /** Returns the opclass of this instruction. */ 575 OpClass opClass() const { return staticInst->opClass(); } 576 577 /** Returns the branch target address. */ 578 Addr branchTarget() const { return staticInst->branchTarget(PC); } 579 580 /** Returns the number of source registers. */ 581 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } 582 583 /** Returns the number of destination registers. */ 584 int8_t numDestRegs() const { return staticInst->numDestRegs(); } 585 586 // the following are used to track physical register usage 587 // for machines with separate int & FP reg files 588 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); } 589 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } 590 591 /** Returns the logical register index of the i'th destination register. */ 592 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); } 593 594 /** Returns the logical register index of the i'th source register. */ 595 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); } 596 597 /** Returns the result of an integer instruction. */ 598 uint64_t readIntResult() { return instResult.integer; } 599 600 /** Returns the result of a floating point instruction. */ 601 float readFloatResult() { return (float)instResult.dbl; } 602 603 /** Returns the result of a floating point (double) instruction. */ 604 double readDoubleResult() { return instResult.dbl; } 605 606 /** Records an integer register being set to a value. */ 607 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 608 { 609 if (recordResult) 610 instResult.integer = val; 611 } 612 613 /** Records an fp register being set to a value. */ 614 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 615 int width) 616 { 617 if (recordResult) { 618 if (width == 32) 619 instResult.dbl = (double)val; 620 else if (width == 64) 621 instResult.dbl = val; 622 else 623 panic("Unsupported width!"); 624 } 625 } 626 627 /** Records an fp register being set to a value. */ 628 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 629 { 630 if (recordResult) 631 instResult.dbl = (double)val; 632 } 633 634 /** Records an fp register being set to an integer value. */ 635 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val, 636 int width) 637 { 638 if (recordResult) 639 instResult.integer = val; 640 } 641 642 /** Records an fp register being set to an integer value. */ 643 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val) 644 { 645 if (recordResult) 646 instResult.integer = val; 647 } 648 649 /** Records that one of the source registers is ready. */ 650 void markSrcRegReady(); 651 652 /** Marks a specific register as ready. */ 653 void markSrcRegReady(RegIndex src_idx); 654 655 /** Returns if a source register is ready. */ 656 bool isReadySrcRegIdx(int idx) const 657 { 658 return this->_readySrcRegIdx[idx]; 659 } 660 661 /** Sets this instruction as completed. */ 662 void setCompleted() { status.set(Completed); } 663 664 /** Returns whether or not this instruction is completed. */ 665 bool isCompleted() const { return status[Completed]; } 666 667 /** Marks the result as ready. */ 668 void setResultReady() { status.set(ResultReady); } 669 670 /** Returns whether or not the result is ready. */ 671 bool isResultReady() const { return status[ResultReady]; } 672 673 /** Sets this instruction as ready to issue. */ 674 void setCanIssue() { status.set(CanIssue); } 675 676 /** Returns whether or not this instruction is ready to issue. */ 677 bool readyToIssue() const { return status[CanIssue]; } 678 679 /** Clears this instruction being able to issue. */ 680 void clearCanIssue() { status.reset(CanIssue); } 681 682 /** Sets this instruction as issued from the IQ. */ 683 void setIssued() { status.set(Issued); } 684 685 /** Returns whether or not this instruction has issued. */ 686 bool isIssued() const { return status[Issued]; } 687 688 /** Clears this instruction as being issued. */ 689 void clearIssued() { status.reset(Issued); } 690 691 /** Sets this instruction as executed. */ 692 void setExecuted() { status.set(Executed); } 693 694 /** Returns whether or not this instruction has executed. */ 695 bool isExecuted() const { return status[Executed]; } 696 697 /** Sets this instruction as ready to commit. */ 698 void setCanCommit() { status.set(CanCommit); } 699 700 /** Clears this instruction as being ready to commit. */ 701 void clearCanCommit() { status.reset(CanCommit); } 702 703 /** Returns whether or not this instruction is ready to commit. */ 704 bool readyToCommit() const { return status[CanCommit]; } 705 706 void setAtCommit() { status.set(AtCommit); } 707 708 bool isAtCommit() { return status[AtCommit]; } 709 710 /** Sets this instruction as committed. */ 711 void setCommitted() { status.set(Committed); } 712 713 /** Returns whether or not this instruction is committed. */ 714 bool isCommitted() const { return status[Committed]; } 715 716 /** Sets this instruction as squashed. */ 717 void setSquashed() { status.set(Squashed); } 718 719 /** Returns whether or not this instruction is squashed. */ 720 bool isSquashed() const { return status[Squashed]; } 721 722 //Instruction Queue Entry 723 //----------------------- 724 /** Sets this instruction as a entry the IQ. */ 725 void setInIQ() { status.set(IqEntry); } 726 727 /** Sets this instruction as a entry the IQ. */ 728 void clearInIQ() { status.reset(IqEntry); } 729 730 /** Returns whether or not this instruction has issued. */ 731 bool isInIQ() const { return status[IqEntry]; } 732 733 /** Sets this instruction as squashed in the IQ. */ 734 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} 735 736 /** Returns whether or not this instruction is squashed in the IQ. */ 737 bool isSquashedInIQ() const { return status[SquashedInIQ]; } 738 739 740 //Load / Store Queue Functions 741 //----------------------- 742 /** Sets this instruction as a entry the LSQ. */ 743 void setInLSQ() { status.set(LsqEntry); } 744 745 /** Sets this instruction as a entry the LSQ. */ 746 void removeInLSQ() { status.reset(LsqEntry); } 747 748 /** Returns whether or not this instruction is in the LSQ. */ 749 bool isInLSQ() const { return status[LsqEntry]; } 750 751 /** Sets this instruction as squashed in the LSQ. */ 752 void setSquashedInLSQ() { status.set(SquashedInLSQ);} 753 754 /** Returns whether or not this instruction is squashed in the LSQ. */ 755 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } 756 757 758 //Reorder Buffer Functions 759 //----------------------- 760 /** Sets this instruction as a entry the ROB. */ 761 void setInROB() { status.set(RobEntry); } 762 763 /** Sets this instruction as a entry the ROB. */ 764 void clearInROB() { status.reset(RobEntry); } 765 766 /** Returns whether or not this instruction is in the ROB. */ 767 bool isInROB() const { return status[RobEntry]; } 768 769 /** Sets this instruction as squashed in the ROB. */ 770 void setSquashedInROB() { status.set(SquashedInROB); } 771 772 /** Returns whether or not this instruction is squashed in the ROB. */ 773 bool isSquashedInROB() const { return status[SquashedInROB]; } 774 775 /** Read the PC of this instruction. */ 776 const Addr readPC() const { return PC; } 777 778 /**Read the micro PC of this instruction. */ 779 const Addr readMicroPC() const { return microPC; } 780 781 /** Set the next PC of this instruction (its actual target). */ 782 void setNextPC(Addr val) 783 { 784 nextPC = val; 785 } 786 787 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/ 788 void setNextNPC(Addr val) 789 { 790#if ISA_HAS_DELAY_SLOT 791 nextNPC = val; 792#endif 793 } 794 795 void setNextMicroPC(Addr val) 796 { 797 nextMicroPC = val; 798 } 799
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| 800 bool readPredicate() 801 { 802 return predicate; 803 } 804 805 void setPredicate(bool val) 806 { 807 predicate = val; 808 } 809
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797 /** Sets the ASID. */ 798 void setASID(short addr_space_id) { asid = addr_space_id; } 799 800 /** Sets the thread id. */ 801 void setTid(ThreadID tid) { threadNumber = tid; } 802 803 /** Sets the pointer to the thread state. */ 804 void setThreadState(ImplState *state) { thread = state; } 805 806 /** Returns the thread context. */ 807 ThreadContext *tcBase() { return thread->getTC(); } 808 809 private: 810 /** Instruction effective address. 811 * @todo: Consider if this is necessary or not. 812 */ 813 Addr instEffAddr; 814 815 /** Whether or not the effective address calculation is completed. 816 * @todo: Consider if this is necessary or not. 817 */ 818 bool eaCalcDone; 819 820 /** Is this instruction's memory access uncacheable. */ 821 bool isUncacheable; 822 823 /** Has this instruction generated a memory request. */ 824 bool reqMade; 825 826 public: 827 /** Sets the effective address. */ 828 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 829 830 /** Returns the effective address. */ 831 const Addr &getEA() const { return instEffAddr; } 832 833 /** Returns whether or not the eff. addr. calculation has been completed. */ 834 bool doneEACalc() { return eaCalcDone; } 835 836 /** Returns whether or not the eff. addr. source registers are ready. */ 837 bool eaSrcsReady(); 838 839 /** Whether or not the memory operation is done. */ 840 bool memOpDone; 841 842 /** Is this instruction's memory access uncacheable. */ 843 bool uncacheable() { return isUncacheable; } 844 845 /** Has this instruction generated a memory request. */ 846 bool hasRequest() { return reqMade; } 847 848 public: 849 /** Load queue index. */ 850 int16_t lqIdx; 851 852 /** Store queue index. */ 853 int16_t sqIdx; 854 855 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 856 ListIt instListIt; 857 858 /** Returns iterator to this instruction in the list of all insts. */ 859 ListIt &getInstListIt() { return instListIt; } 860 861 /** Sets iterator for this instruction in the list of all insts. */ 862 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 863 864 public: 865 /** Returns the number of consecutive store conditional failures. */ 866 unsigned readStCondFailures() 867 { return thread->storeCondFailures; } 868 869 /** Sets the number of consecutive store conditional failures. */ 870 void setStCondFailures(unsigned sc_failures) 871 { thread->storeCondFailures = sc_failures; } 872}; 873 874template<class Impl> 875Fault 876BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 877 unsigned size, unsigned flags) 878{ 879 reqMade = true; 880 Request *req = new Request(asid, addr, size, flags, this->PC, 881 thread->contextId(), threadNumber); 882 883 Request *sreqLow = NULL; 884 Request *sreqHigh = NULL; 885 886 // Only split the request if the ISA supports unaligned accesses. 887 if (TheISA::HasUnalignedMemAcc) { 888 splitRequest(req, sreqLow, sreqHigh); 889 } 890 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 891 892 if (fault == NoFault) { 893 effAddr = req->getVaddr(); 894 effAddrValid = true; 895 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 896 } else { 897 // Commit will have to clean up whatever happened. Set this 898 // instruction as executed. 899 this->setExecuted(); 900 } 901 902 if (fault != NoFault) { 903 // Return a fixed value to keep simulation deterministic even 904 // along misspeculated paths. 905 bzero(data, size); 906 } 907 908 if (traceData) { 909 traceData->setAddr(addr); 910 } 911 912 return fault; 913} 914 915template<class Impl> 916template<class T> 917inline Fault 918BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 919{ 920 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 921 922 data = TheISA::gtoh(data); 923 924 if (traceData) { 925 traceData->setData(data); 926 } 927 928 return fault; 929} 930 931template<class Impl> 932Fault 933BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 934 Addr addr, unsigned flags, uint64_t *res) 935{ 936 if (traceData) { 937 traceData->setAddr(addr); 938 } 939 940 reqMade = true; 941 Request *req = new Request(asid, addr, size, flags, this->PC, 942 thread->contextId(), threadNumber); 943 944 Request *sreqLow = NULL; 945 Request *sreqHigh = NULL; 946 947 // Only split the request if the ISA supports unaligned accesses. 948 if (TheISA::HasUnalignedMemAcc) { 949 splitRequest(req, sreqLow, sreqHigh); 950 } 951 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 952 953 if (fault == NoFault) { 954 effAddr = req->getVaddr(); 955 effAddrValid = true; 956 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 957 } 958 959 return fault; 960} 961 962template<class Impl> 963template<class T> 964inline Fault 965BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 966{ 967 if (traceData) { 968 traceData->setData(data); 969 } 970 data = TheISA::htog(data); 971 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 972} 973 974template<class Impl> 975inline void 976BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 977 RequestPtr &sreqHigh) 978{ 979 // Check to see if the request crosses the next level block boundary. 980 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 981 Addr addr = req->getVaddr(); 982 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 983 assert(split_addr <= addr || split_addr - addr < block_size); 984 985 // Spans two blocks. 986 if (split_addr > addr) { 987 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 988 } 989} 990 991template<class Impl> 992inline void 993BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 994 RequestPtr sreqHigh, uint64_t *res, 995 BaseTLB::Mode mode) 996{ 997 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 998 WholeTranslationState *state = 999 new WholeTranslationState(req, NULL, res, mode); 1000 1001 // One translation if the request isn't split. 1002 DataTranslation<BaseDynInst<Impl> > *trans = 1003 new DataTranslation<BaseDynInst<Impl> >(this, state); 1004 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1005 } else { 1006 WholeTranslationState *state = 1007 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1008 1009 // Two translations when the request is split. 1010 DataTranslation<BaseDynInst<Impl> > *stransLow = 1011 new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 1012 DataTranslation<BaseDynInst<Impl> > *stransHigh = 1013 new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 1014 1015 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1016 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1017 } 1018} 1019 1020template<class Impl> 1021inline void 1022BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1023{ 1024 fault = state->getFault(); 1025 1026 if (state->isUncacheable()) 1027 isUncacheable = true; 1028 1029 if (fault == NoFault) { 1030 physEffAddr = state->getPaddr(); 1031 memReqFlags = state->getFlags(); 1032 1033 if (state->mainReq->isCondSwap()) { 1034 assert(state->res); 1035 state->mainReq->setExtraData(*state->res); 1036 } 1037 1038 } else { 1039 state->deleteReqs(); 1040 } 1041 delete state; 1042} 1043 1044#endif // __CPU_BASE_DYN_INST_HH__
| 810 /** Sets the ASID. */ 811 void setASID(short addr_space_id) { asid = addr_space_id; } 812 813 /** Sets the thread id. */ 814 void setTid(ThreadID tid) { threadNumber = tid; } 815 816 /** Sets the pointer to the thread state. */ 817 void setThreadState(ImplState *state) { thread = state; } 818 819 /** Returns the thread context. */ 820 ThreadContext *tcBase() { return thread->getTC(); } 821 822 private: 823 /** Instruction effective address. 824 * @todo: Consider if this is necessary or not. 825 */ 826 Addr instEffAddr; 827 828 /** Whether or not the effective address calculation is completed. 829 * @todo: Consider if this is necessary or not. 830 */ 831 bool eaCalcDone; 832 833 /** Is this instruction's memory access uncacheable. */ 834 bool isUncacheable; 835 836 /** Has this instruction generated a memory request. */ 837 bool reqMade; 838 839 public: 840 /** Sets the effective address. */ 841 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; } 842 843 /** Returns the effective address. */ 844 const Addr &getEA() const { return instEffAddr; } 845 846 /** Returns whether or not the eff. addr. calculation has been completed. */ 847 bool doneEACalc() { return eaCalcDone; } 848 849 /** Returns whether or not the eff. addr. source registers are ready. */ 850 bool eaSrcsReady(); 851 852 /** Whether or not the memory operation is done. */ 853 bool memOpDone; 854 855 /** Is this instruction's memory access uncacheable. */ 856 bool uncacheable() { return isUncacheable; } 857 858 /** Has this instruction generated a memory request. */ 859 bool hasRequest() { return reqMade; } 860 861 public: 862 /** Load queue index. */ 863 int16_t lqIdx; 864 865 /** Store queue index. */ 866 int16_t sqIdx; 867 868 /** Iterator pointing to this BaseDynInst in the list of all insts. */ 869 ListIt instListIt; 870 871 /** Returns iterator to this instruction in the list of all insts. */ 872 ListIt &getInstListIt() { return instListIt; } 873 874 /** Sets iterator for this instruction in the list of all insts. */ 875 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; } 876 877 public: 878 /** Returns the number of consecutive store conditional failures. */ 879 unsigned readStCondFailures() 880 { return thread->storeCondFailures; } 881 882 /** Sets the number of consecutive store conditional failures. */ 883 void setStCondFailures(unsigned sc_failures) 884 { thread->storeCondFailures = sc_failures; } 885}; 886 887template<class Impl> 888Fault 889BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data, 890 unsigned size, unsigned flags) 891{ 892 reqMade = true; 893 Request *req = new Request(asid, addr, size, flags, this->PC, 894 thread->contextId(), threadNumber); 895 896 Request *sreqLow = NULL; 897 Request *sreqHigh = NULL; 898 899 // Only split the request if the ISA supports unaligned accesses. 900 if (TheISA::HasUnalignedMemAcc) { 901 splitRequest(req, sreqLow, sreqHigh); 902 } 903 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read); 904 905 if (fault == NoFault) { 906 effAddr = req->getVaddr(); 907 effAddrValid = true; 908 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx); 909 } else { 910 // Commit will have to clean up whatever happened. Set this 911 // instruction as executed. 912 this->setExecuted(); 913 } 914 915 if (fault != NoFault) { 916 // Return a fixed value to keep simulation deterministic even 917 // along misspeculated paths. 918 bzero(data, size); 919 } 920 921 if (traceData) { 922 traceData->setAddr(addr); 923 } 924 925 return fault; 926} 927 928template<class Impl> 929template<class T> 930inline Fault 931BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 932{ 933 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags); 934 935 data = TheISA::gtoh(data); 936 937 if (traceData) { 938 traceData->setData(data); 939 } 940 941 return fault; 942} 943 944template<class Impl> 945Fault 946BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size, 947 Addr addr, unsigned flags, uint64_t *res) 948{ 949 if (traceData) { 950 traceData->setAddr(addr); 951 } 952 953 reqMade = true; 954 Request *req = new Request(asid, addr, size, flags, this->PC, 955 thread->contextId(), threadNumber); 956 957 Request *sreqLow = NULL; 958 Request *sreqHigh = NULL; 959 960 // Only split the request if the ISA supports unaligned accesses. 961 if (TheISA::HasUnalignedMemAcc) { 962 splitRequest(req, sreqLow, sreqHigh); 963 } 964 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write); 965 966 if (fault == NoFault) { 967 effAddr = req->getVaddr(); 968 effAddrValid = true; 969 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx); 970 } 971 972 return fault; 973} 974 975template<class Impl> 976template<class T> 977inline Fault 978BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 979{ 980 if (traceData) { 981 traceData->setData(data); 982 } 983 data = TheISA::htog(data); 984 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res); 985} 986 987template<class Impl> 988inline void 989BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow, 990 RequestPtr &sreqHigh) 991{ 992 // Check to see if the request crosses the next level block boundary. 993 unsigned block_size = cpu->getDcachePort()->peerBlockSize(); 994 Addr addr = req->getVaddr(); 995 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size); 996 assert(split_addr <= addr || split_addr - addr < block_size); 997 998 // Spans two blocks. 999 if (split_addr > addr) { 1000 req->splitOnVaddr(split_addr, sreqLow, sreqHigh); 1001 } 1002} 1003 1004template<class Impl> 1005inline void 1006BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow, 1007 RequestPtr sreqHigh, uint64_t *res, 1008 BaseTLB::Mode mode) 1009{ 1010 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) { 1011 WholeTranslationState *state = 1012 new WholeTranslationState(req, NULL, res, mode); 1013 1014 // One translation if the request isn't split. 1015 DataTranslation<BaseDynInst<Impl> > *trans = 1016 new DataTranslation<BaseDynInst<Impl> >(this, state); 1017 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode); 1018 } else { 1019 WholeTranslationState *state = 1020 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode); 1021 1022 // Two translations when the request is split. 1023 DataTranslation<BaseDynInst<Impl> > *stransLow = 1024 new DataTranslation<BaseDynInst<Impl> >(this, state, 0); 1025 DataTranslation<BaseDynInst<Impl> > *stransHigh = 1026 new DataTranslation<BaseDynInst<Impl> >(this, state, 1); 1027 1028 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode); 1029 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode); 1030 } 1031} 1032 1033template<class Impl> 1034inline void 1035BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state) 1036{ 1037 fault = state->getFault(); 1038 1039 if (state->isUncacheable()) 1040 isUncacheable = true; 1041 1042 if (fault == NoFault) { 1043 physEffAddr = state->getPaddr(); 1044 memReqFlags = state->getFlags(); 1045 1046 if (state->mainReq->isCondSwap()) { 1047 assert(state->res); 1048 state->mainReq->setExtraData(*state->res); 1049 } 1050 1051 } else { 1052 state->deleteReqs(); 1053 } 1054 delete state; 1055} 1056 1057#endif // __CPU_BASE_DYN_INST_HH__
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