1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Timothy M. Jones
31 */
32
33#ifndef __CPU_BASE_DYN_INST_HH__
34#define __CPU_BASE_DYN_INST_HH__
35
36#include <bitset>
37#include <list>
38#include <string>
39
40#include "arch/faults.hh"
41#include "base/fast_alloc.hh"
42#include "base/trace.hh"
43#include "config/full_system.hh"
44#include "config/the_isa.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/op_class.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/translation.hh"
51#include "mem/packet.hh"
52#include "sim/system.hh"
53#include "sim/tlb.hh"
54
55/**
56 * @file
57 * Defines a dynamic instruction context.
58 */
59
60// Forward declaration.
61class StaticInstPtr;
62
63template <class Impl>
64class BaseDynInst : public FastAlloc, public RefCounted
65{
66 public:
67 // Typedef for the CPU.
68 typedef typename Impl::CPUType ImplCPU;
69 typedef typename ImplCPU::ImplState ImplState;
70
71 // Logical register index type.
72 typedef TheISA::RegIndex RegIndex;
73 // Integer register type.
74 typedef TheISA::IntReg IntReg;
75 // Floating point register type.
76 typedef TheISA::FloatReg FloatReg;
77
78 // The DynInstPtr type.
79 typedef typename Impl::DynInstPtr DynInstPtr;
80
81 // The list of instructions iterator type.
82 typedef typename std::list<DynInstPtr>::iterator ListIt;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
87 };
88
89 /** The StaticInst used by this BaseDynInst. */
90 StaticInstPtr staticInst;
91
92 ////////////////////////////////////////////
93 //
94 // INSTRUCTION EXECUTION
95 //
96 ////////////////////////////////////////////
97 /** InstRecord that tracks this instructions. */
98 Trace::InstRecord *traceData;
99
100 void demapPage(Addr vaddr, uint64_t asn)
101 {
102 cpu->demapPage(vaddr, asn);
103 }
104 void demapInstPage(Addr vaddr, uint64_t asn)
105 {
106 cpu->demapPage(vaddr, asn);
107 }
108 void demapDataPage(Addr vaddr, uint64_t asn)
109 {
110 cpu->demapPage(vaddr, asn);
111 }
112
113 /**
114 * Does a read to a given address.
115 * @param addr The address to read.
116 * @param data The read's data is written into this parameter.
117 * @param flags The request's flags.
118 * @return Returns any fault due to the read.
119 */
120 template <class T>
121 Fault read(Addr addr, T &data, unsigned flags);
122
123 /**
124 * Does a write to a given address.
125 * @param data The data to be written.
126 * @param addr The address to write to.
127 * @param flags The request's flags.
128 * @param res The result of the write (for load locked/store conditionals).
129 * @return Returns any fault due to the write.
130 */
131 template <class T>
132 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
133
134 /** Splits a request in two if it crosses a dcache block. */
135 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
136 RequestPtr &sreqHigh);
137
138 /** Initiate a DTB address translation. */
139 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
140 RequestPtr sreqHigh, uint64_t *res,
141 BaseTLB::Mode mode);
142
143 /** Finish a DTB address translation. */
144 void finishTranslation(WholeTranslationState *state);
145
146 void prefetch(Addr addr, unsigned flags);
147 void writeHint(Addr addr, int size, unsigned flags);
148 Fault copySrcTranslate(Addr src);
149 Fault copy(Addr dest);
150
151 /** @todo: Consider making this private. */
152 public:
153 /** The sequence number of the instruction. */
154 InstSeqNum seqNum;
155
156 enum Status {
157 IqEntry, /// Instruction is in the IQ
158 RobEntry, /// Instruction is in the ROB
159 LsqEntry, /// Instruction is in the LSQ
160 Completed, /// Instruction has completed
161 ResultReady, /// Instruction has its result
162 CanIssue, /// Instruction can issue and execute
163 Issued, /// Instruction has issued
164 Executed, /// Instruction has executed
165 CanCommit, /// Instruction can commit
166 AtCommit, /// Instruction has reached commit
167 Committed, /// Instruction has committed
168 Squashed, /// Instruction is squashed
169 SquashedInIQ, /// Instruction is squashed in the IQ
170 SquashedInLSQ, /// Instruction is squashed in the LSQ
171 SquashedInROB, /// Instruction is squashed in the ROB
172 RecoverInst, /// Is a recover instruction
173 BlockingInst, /// Is a blocking instruction
174 ThreadsyncWait, /// Is a thread synchronization instruction
175 SerializeBefore, /// Needs to serialize on
176 /// instructions ahead of it
177 SerializeAfter, /// Needs to serialize instructions behind it
178 SerializeHandled, /// Serialization has been handled
179 NumStatus
180 };
181
182 /** The status of this BaseDynInst. Several bits can be set. */
183 std::bitset<NumStatus> status;
184
185 /** The thread this instruction is from. */
186 ThreadID threadNumber;
187
188 /** data address space ID, for loads & stores. */
189 short asid;
190
191 /** How many source registers are ready. */
192 unsigned readyRegs;
193
194 /** Pointer to the Impl's CPU object. */
195 ImplCPU *cpu;
196
197 /** Pointer to the thread state. */
198 ImplState *thread;
199
200 /** The kind of fault this instruction has generated. */
201 Fault fault;
202
203 /** Pointer to the data for the memory access. */
204 uint8_t *memData;
205
206 /** The effective virtual address (lds & stores only). */
207 Addr effAddr;
208
209 /** Is the effective virtual address valid. */
210 bool effAddrValid;
211
212 /** The effective physical address. */
213 Addr physEffAddr;
214
215 /** Effective virtual address for a copy source. */
216 Addr copySrcEffAddr;
217
218 /** Effective physical address for a copy source. */
219 Addr copySrcPhysEffAddr;
220
221 /** The memory request flags (from translation). */
222 unsigned memReqFlags;
223
224 union Result {
225 uint64_t integer;
226// float fp;
227 double dbl;
228 };
229
230 /** The result of the instruction; assumes for now that there's only one
231 * destination register.
232 */
233 Result instResult;
234
235 /** Records changes to result? */
236 bool recordResult;
237
238 /** PC of this instruction. */
239 Addr PC;
240
241 /** Micro PC of this instruction. */
242 Addr microPC;
243
244 protected:
245 /** Next non-speculative PC. It is not filled in at fetch, but rather
246 * once the target of the branch is truly known (either decode or
247 * execute).
248 */
249 Addr nextPC;
250
251 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
252 Addr nextNPC;
253
254 /** Next non-speculative micro PC. */
255 Addr nextMicroPC;
256
257 /** Predicted next PC. */
258 Addr predPC;
259
260 /** Predicted next NPC. */
261 Addr predNPC;
262
263 /** Predicted next microPC */
264 Addr predMicroPC;
265
266 /** If this is a branch that was predicted taken */
267 bool predTaken;
268
269 public:
270
271#ifdef DEBUG
272 void dumpSNList();
273#endif
274
275 /** Whether or not the source register is ready.
276 * @todo: Not sure this should be here vs the derived class.
277 */
278 bool _readySrcRegIdx[MaxInstSrcRegs];
279
280 protected:
281 /** Flattened register index of the destination registers of this
282 * instruction.
283 */
284 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
285
286 /** Flattened register index of the source registers of this
287 * instruction.
288 */
289 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
290
291 /** Physical register index of the destination registers of this
292 * instruction.
293 */
294 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
295
296 /** Physical register index of the source registers of this
297 * instruction.
298 */
299 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
300
301 /** Physical register index of the previous producers of the
302 * architected destinations.
303 */
304 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
305
306 public:
307
308 /** Returns the physical register index of the i'th destination
309 * register.
310 */
311 PhysRegIndex renamedDestRegIdx(int idx) const
312 {
313 return _destRegIdx[idx];
314 }
315
316 /** Returns the physical register index of the i'th source register. */
317 PhysRegIndex renamedSrcRegIdx(int idx) const
318 {
319 return _srcRegIdx[idx];
320 }
321
322 /** Returns the flattened register index of the i'th destination
323 * register.
324 */
325 TheISA::RegIndex flattenedDestRegIdx(int idx) const
326 {
327 return _flatDestRegIdx[idx];
328 }
329
330 /** Returns the flattened register index of the i'th source register */
331 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
332 {
333 return _flatSrcRegIdx[idx];
334 }
335
336 /** Returns the physical register index of the previous physical register
337 * that remapped to the same logical register index.
338 */
339 PhysRegIndex prevDestRegIdx(int idx) const
340 {
341 return _prevDestRegIdx[idx];
342 }
343
344 /** Renames a destination register to a physical register. Also records
345 * the previous physical register that the logical register mapped to.
346 */
347 void renameDestReg(int idx,
348 PhysRegIndex renamed_dest,
349 PhysRegIndex previous_rename)
350 {
351 _destRegIdx[idx] = renamed_dest;
352 _prevDestRegIdx[idx] = previous_rename;
353 }
354
355 /** Renames a source logical register to the physical register which
356 * has/will produce that logical register's result.
357 * @todo: add in whether or not the source register is ready.
358 */
359 void renameSrcReg(int idx, PhysRegIndex renamed_src)
360 {
361 _srcRegIdx[idx] = renamed_src;
362 }
363
364 /** Flattens a source architectural register index into a logical index.
365 */
366 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
367 {
368 _flatSrcRegIdx[idx] = flattened_src;
369 }
370
371 /** Flattens a destination architectural register index into a logical
372 * index.
373 */
374 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
375 {
376 _flatDestRegIdx[idx] = flattened_dest;
377 }
378 /** BaseDynInst constructor given a binary instruction.
379 * @param staticInst A StaticInstPtr to the underlying instruction.
380 * @param PC The PC of the instruction.
381 * @param pred_PC The predicted next PC.
382 * @param pred_NPC The predicted next NPC.
383 * @param seq_num The sequence number of the instruction.
384 * @param cpu Pointer to the instruction's CPU.
385 */
386 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
387 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
388 InstSeqNum seq_num, ImplCPU *cpu);
389
390 /** BaseDynInst constructor given a binary instruction.
391 * @param inst The binary instruction.
392 * @param PC The PC of the instruction.
393 * @param pred_PC The predicted next PC.
394 * @param pred_NPC The predicted next NPC.
395 * @param seq_num The sequence number of the instruction.
396 * @param cpu Pointer to the instruction's CPU.
397 */
398 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
399 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
400 InstSeqNum seq_num, ImplCPU *cpu);
401
402 /** BaseDynInst constructor given a StaticInst pointer.
403 * @param _staticInst The StaticInst for this BaseDynInst.
404 */
405 BaseDynInst(StaticInstPtr &_staticInst);
406
407 /** BaseDynInst destructor. */
408 ~BaseDynInst();
409
410 private:
411 /** Function to initialize variables in the constructors. */
412 void initVars();
413
414 public:
415 /** Dumps out contents of this BaseDynInst. */
416 void dump();
417
418 /** Dumps out contents of this BaseDynInst into given string. */
419 void dump(std::string &outstring);
420
421 /** Read this CPU's ID. */
422 int cpuId() { return cpu->cpuId(); }
423
424 /** Read this context's system-wide ID **/
425 int contextId() { return thread->contextId(); }
426
427 /** Returns the fault type. */
428 Fault getFault() { return fault; }
429
430 /** Checks whether or not this instruction has had its branch target
431 * calculated yet. For now it is not utilized and is hacked to be
432 * always false.
433 * @todo: Actually use this instruction.
434 */
435 bool doneTargCalc() { return false; }
436
437 /** Returns the next PC. This could be the speculative next PC if it is
438 * called prior to the actual branch target being calculated.
439 */
440 Addr readNextPC() { return nextPC; }
441
442 /** Returns the next NPC. This could be the speculative next NPC if it is
443 * called prior to the actual branch target being calculated.
444 */
445 Addr readNextNPC()
446 {
447#if ISA_HAS_DELAY_SLOT
448 return nextNPC;
449#else
450 return nextPC + sizeof(TheISA::MachInst);
451#endif
452 }
453
454 Addr readNextMicroPC()
455 {
456 return nextMicroPC;
457 }
458
459 /** Set the predicted target of this current instruction. */
460 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
461 Addr predicted_MicroPC)
462 {
463 predPC = predicted_PC;
464 predNPC = predicted_NPC;
465 predMicroPC = predicted_MicroPC;
466 }
467
468 /** Returns the predicted PC immediately after the branch. */
469 Addr readPredPC() { return predPC; }
470
471 /** Returns the predicted PC two instructions after the branch */
472 Addr readPredNPC() { return predNPC; }
473
474 /** Returns the predicted micro PC after the branch */
475 Addr readPredMicroPC() { return predMicroPC; }
476
477 /** Returns whether the instruction was predicted taken or not. */
478 bool readPredTaken()
479 {
480 return predTaken;
481 }
482
483 void setPredTaken(bool predicted_taken)
484 {
485 predTaken = predicted_taken;
486 }
487
488 /** Returns whether the instruction mispredicted. */
489 bool mispredicted()
490 {
491 return readPredPC() != readNextPC() ||
492 readPredNPC() != readNextNPC() ||
493 readPredMicroPC() != readNextMicroPC();
494 }
495
496 //
497 // Instruction types. Forward checks to StaticInst object.
498 //
499 bool isNop() const { return staticInst->isNop(); }
500 bool isMemRef() const { return staticInst->isMemRef(); }
501 bool isLoad() const { return staticInst->isLoad(); }
502 bool isStore() const { return staticInst->isStore(); }
503 bool isStoreConditional() const
504 { return staticInst->isStoreConditional(); }
505 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
506 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
507 bool isCopy() const { return staticInst->isCopy(); }
508 bool isInteger() const { return staticInst->isInteger(); }
509 bool isFloating() const { return staticInst->isFloating(); }
510 bool isControl() const { return staticInst->isControl(); }
511 bool isCall() const { return staticInst->isCall(); }
512 bool isReturn() const { return staticInst->isReturn(); }
513 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
514 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
515 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
516 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
517 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
518 bool isThreadSync() const { return staticInst->isThreadSync(); }
519 bool isSerializing() const { return staticInst->isSerializing(); }
520 bool isSerializeBefore() const
521 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
522 bool isSerializeAfter() const
523 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
524 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
525 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
526 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
527 bool isQuiesce() const { return staticInst->isQuiesce(); }
528 bool isIprAccess() const { return staticInst->isIprAccess(); }
529 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
530 bool isSyscall() const { return staticInst->isSyscall(); }
531 bool isMacroop() const { return staticInst->isMacroop(); }
532 bool isMicroop() const { return staticInst->isMicroop(); }
533 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
534 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
535 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
536 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
537
538 /** Temporarily sets this instruction as a serialize before instruction. */
539 void setSerializeBefore() { status.set(SerializeBefore); }
540
541 /** Clears the serializeBefore part of this instruction. */
542 void clearSerializeBefore() { status.reset(SerializeBefore); }
543
544 /** Checks if this serializeBefore is only temporarily set. */
545 bool isTempSerializeBefore() { return status[SerializeBefore]; }
546
547 /** Temporarily sets this instruction as a serialize after instruction. */
548 void setSerializeAfter() { status.set(SerializeAfter); }
549
550 /** Clears the serializeAfter part of this instruction.*/
551 void clearSerializeAfter() { status.reset(SerializeAfter); }
552
553 /** Checks if this serializeAfter is only temporarily set. */
554 bool isTempSerializeAfter() { return status[SerializeAfter]; }
555
556 /** Sets the serialization part of this instruction as handled. */
557 void setSerializeHandled() { status.set(SerializeHandled); }
558
559 /** Checks if the serialization part of this instruction has been
560 * handled. This does not apply to the temporary serializing
561 * state; it only applies to this instruction's own permanent
562 * serializing state.
563 */
564 bool isSerializeHandled() { return status[SerializeHandled]; }
565
566 /** Returns the opclass of this instruction. */
567 OpClass opClass() const { return staticInst->opClass(); }
568
569 /** Returns the branch target address. */
570 Addr branchTarget() const { return staticInst->branchTarget(PC); }
571
572 /** Returns the number of source registers. */
573 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
574
575 /** Returns the number of destination registers. */
576 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
577
578 // the following are used to track physical register usage
579 // for machines with separate int & FP reg files
580 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
581 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
582
583 /** Returns the logical register index of the i'th destination register. */
584 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
585
586 /** Returns the logical register index of the i'th source register. */
587 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
588
589 /** Returns the result of an integer instruction. */
590 uint64_t readIntResult() { return instResult.integer; }
591
592 /** Returns the result of a floating point instruction. */
593 float readFloatResult() { return (float)instResult.dbl; }
594
595 /** Returns the result of a floating point (double) instruction. */
596 double readDoubleResult() { return instResult.dbl; }
597
598 /** Records an integer register being set to a value. */
599 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
600 {
601 if (recordResult)
602 instResult.integer = val;
603 }
604
605 /** Records an fp register being set to a value. */
606 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
607 int width)
608 {
609 if (recordResult) {
610 if (width == 32)
611 instResult.dbl = (double)val;
612 else if (width == 64)
613 instResult.dbl = val;
614 else
615 panic("Unsupported width!");
616 }
617 }
618
619 /** Records an fp register being set to a value. */
620 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
621 {
622 if (recordResult)
623 instResult.dbl = (double)val;
624 }
625
626 /** Records an fp register being set to an integer value. */
627 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
628 int width)
629 {
630 if (recordResult)
631 instResult.integer = val;
632 }
633
634 /** Records an fp register being set to an integer value. */
635 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
636 {
637 if (recordResult)
638 instResult.integer = val;
639 }
640
641 /** Records that one of the source registers is ready. */
642 void markSrcRegReady();
643
644 /** Marks a specific register as ready. */
645 void markSrcRegReady(RegIndex src_idx);
646
647 /** Returns if a source register is ready. */
648 bool isReadySrcRegIdx(int idx) const
649 {
650 return this->_readySrcRegIdx[idx];
651 }
652
653 /** Sets this instruction as completed. */
654 void setCompleted() { status.set(Completed); }
655
656 /** Returns whether or not this instruction is completed. */
657 bool isCompleted() const { return status[Completed]; }
658
659 /** Marks the result as ready. */
660 void setResultReady() { status.set(ResultReady); }
661
662 /** Returns whether or not the result is ready. */
663 bool isResultReady() const { return status[ResultReady]; }
664
665 /** Sets this instruction as ready to issue. */
666 void setCanIssue() { status.set(CanIssue); }
667
668 /** Returns whether or not this instruction is ready to issue. */
669 bool readyToIssue() const { return status[CanIssue]; }
670
671 /** Clears this instruction being able to issue. */
672 void clearCanIssue() { status.reset(CanIssue); }
673
674 /** Sets this instruction as issued from the IQ. */
675 void setIssued() { status.set(Issued); }
676
677 /** Returns whether or not this instruction has issued. */
678 bool isIssued() const { return status[Issued]; }
679
680 /** Clears this instruction as being issued. */
681 void clearIssued() { status.reset(Issued); }
682
683 /** Sets this instruction as executed. */
684 void setExecuted() { status.set(Executed); }
685
686 /** Returns whether or not this instruction has executed. */
687 bool isExecuted() const { return status[Executed]; }
688
689 /** Sets this instruction as ready to commit. */
690 void setCanCommit() { status.set(CanCommit); }
691
692 /** Clears this instruction as being ready to commit. */
693 void clearCanCommit() { status.reset(CanCommit); }
694
695 /** Returns whether or not this instruction is ready to commit. */
696 bool readyToCommit() const { return status[CanCommit]; }
697
698 void setAtCommit() { status.set(AtCommit); }
699
700 bool isAtCommit() { return status[AtCommit]; }
701
702 /** Sets this instruction as committed. */
703 void setCommitted() { status.set(Committed); }
704
705 /** Returns whether or not this instruction is committed. */
706 bool isCommitted() const { return status[Committed]; }
707
708 /** Sets this instruction as squashed. */
709 void setSquashed() { status.set(Squashed); }
710
711 /** Returns whether or not this instruction is squashed. */
712 bool isSquashed() const { return status[Squashed]; }
713
714 //Instruction Queue Entry
715 //-----------------------
716 /** Sets this instruction as a entry the IQ. */
717 void setInIQ() { status.set(IqEntry); }
718
719 /** Sets this instruction as a entry the IQ. */
720 void clearInIQ() { status.reset(IqEntry); }
721
722 /** Returns whether or not this instruction has issued. */
723 bool isInIQ() const { return status[IqEntry]; }
724
725 /** Sets this instruction as squashed in the IQ. */
726 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
727
728 /** Returns whether or not this instruction is squashed in the IQ. */
729 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
730
731
732 //Load / Store Queue Functions
733 //-----------------------
734 /** Sets this instruction as a entry the LSQ. */
735 void setInLSQ() { status.set(LsqEntry); }
736
737 /** Sets this instruction as a entry the LSQ. */
738 void removeInLSQ() { status.reset(LsqEntry); }
739
740 /** Returns whether or not this instruction is in the LSQ. */
741 bool isInLSQ() const { return status[LsqEntry]; }
742
743 /** Sets this instruction as squashed in the LSQ. */
744 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
745
746 /** Returns whether or not this instruction is squashed in the LSQ. */
747 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
748
749
750 //Reorder Buffer Functions
751 //-----------------------
752 /** Sets this instruction as a entry the ROB. */
753 void setInROB() { status.set(RobEntry); }
754
755 /** Sets this instruction as a entry the ROB. */
756 void clearInROB() { status.reset(RobEntry); }
757
758 /** Returns whether or not this instruction is in the ROB. */
759 bool isInROB() const { return status[RobEntry]; }
760
761 /** Sets this instruction as squashed in the ROB. */
762 void setSquashedInROB() { status.set(SquashedInROB); }
763
764 /** Returns whether or not this instruction is squashed in the ROB. */
765 bool isSquashedInROB() const { return status[SquashedInROB]; }
766
767 /** Read the PC of this instruction. */
768 const Addr readPC() const { return PC; }
769
770 /**Read the micro PC of this instruction. */
771 const Addr readMicroPC() const { return microPC; }
772
773 /** Set the next PC of this instruction (its actual target). */
774 void setNextPC(Addr val)
775 {
776 nextPC = val;
777 }
778
779 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
780 void setNextNPC(Addr val)
781 {
782#if ISA_HAS_DELAY_SLOT
783 nextNPC = val;
784#endif
785 }
786
787 void setNextMicroPC(Addr val)
788 {
789 nextMicroPC = val;
790 }
791
792 /** Sets the ASID. */
793 void setASID(short addr_space_id) { asid = addr_space_id; }
794
795 /** Sets the thread id. */
796 void setTid(ThreadID tid) { threadNumber = tid; }
797
798 /** Sets the pointer to the thread state. */
799 void setThreadState(ImplState *state) { thread = state; }
800
801 /** Returns the thread context. */
802 ThreadContext *tcBase() { return thread->getTC(); }
803
804 private:
805 /** Instruction effective address.
806 * @todo: Consider if this is necessary or not.
807 */
808 Addr instEffAddr;
809
810 /** Whether or not the effective address calculation is completed.
811 * @todo: Consider if this is necessary or not.
812 */
813 bool eaCalcDone;
814
815 /** Is this instruction's memory access uncacheable. */
816 bool isUncacheable;
817
818 /** Has this instruction generated a memory request. */
819 bool reqMade;
820
821 public:
822 /** Sets the effective address. */
823 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
824
825 /** Returns the effective address. */
826 const Addr &getEA() const { return instEffAddr; }
827
828 /** Returns whether or not the eff. addr. calculation has been completed. */
829 bool doneEACalc() { return eaCalcDone; }
830
831 /** Returns whether or not the eff. addr. source registers are ready. */
832 bool eaSrcsReady();
833
834 /** Whether or not the memory operation is done. */
835 bool memOpDone;
836
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return isUncacheable; }
839
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return reqMade; }
842
843 public:
844 /** Load queue index. */
845 int16_t lqIdx;
846
847 /** Store queue index. */
848 int16_t sqIdx;
849
850 /** Iterator pointing to this BaseDynInst in the list of all insts. */
851 ListIt instListIt;
852
853 /** Returns iterator to this instruction in the list of all insts. */
854 ListIt &getInstListIt() { return instListIt; }
855
856 /** Sets iterator for this instruction in the list of all insts. */
857 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
858
859 public:
860 /** Returns the number of consecutive store conditional failures. */
861 unsigned readStCondFailures()
862 { return thread->storeCondFailures; }
863
864 /** Sets the number of consecutive store conditional failures. */
865 void setStCondFailures(unsigned sc_failures)
866 { thread->storeCondFailures = sc_failures; }
867};
868
869template<class Impl>
870template<class T>
871inline Fault
872BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
873{
874 reqMade = true;
875 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
876 thread->contextId(), threadNumber);
877
878 Request *sreqLow = NULL;
879 Request *sreqHigh = NULL;
880
881 // Only split the request if the ISA supports unaligned accesses.
882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
884 }
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
889 effAddrValid = true;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Timothy M. Jones
31 */
32
33#ifndef __CPU_BASE_DYN_INST_HH__
34#define __CPU_BASE_DYN_INST_HH__
35
36#include <bitset>
37#include <list>
38#include <string>
39
40#include "arch/faults.hh"
41#include "base/fast_alloc.hh"
42#include "base/trace.hh"
43#include "config/full_system.hh"
44#include "config/the_isa.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/op_class.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/translation.hh"
51#include "mem/packet.hh"
52#include "sim/system.hh"
53#include "sim/tlb.hh"
54
55/**
56 * @file
57 * Defines a dynamic instruction context.
58 */
59
60// Forward declaration.
61class StaticInstPtr;
62
63template <class Impl>
64class BaseDynInst : public FastAlloc, public RefCounted
65{
66 public:
67 // Typedef for the CPU.
68 typedef typename Impl::CPUType ImplCPU;
69 typedef typename ImplCPU::ImplState ImplState;
70
71 // Logical register index type.
72 typedef TheISA::RegIndex RegIndex;
73 // Integer register type.
74 typedef TheISA::IntReg IntReg;
75 // Floating point register type.
76 typedef TheISA::FloatReg FloatReg;
77
78 // The DynInstPtr type.
79 typedef typename Impl::DynInstPtr DynInstPtr;
80
81 // The list of instructions iterator type.
82 typedef typename std::list<DynInstPtr>::iterator ListIt;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
87 };
88
89 /** The StaticInst used by this BaseDynInst. */
90 StaticInstPtr staticInst;
91
92 ////////////////////////////////////////////
93 //
94 // INSTRUCTION EXECUTION
95 //
96 ////////////////////////////////////////////
97 /** InstRecord that tracks this instructions. */
98 Trace::InstRecord *traceData;
99
100 void demapPage(Addr vaddr, uint64_t asn)
101 {
102 cpu->demapPage(vaddr, asn);
103 }
104 void demapInstPage(Addr vaddr, uint64_t asn)
105 {
106 cpu->demapPage(vaddr, asn);
107 }
108 void demapDataPage(Addr vaddr, uint64_t asn)
109 {
110 cpu->demapPage(vaddr, asn);
111 }
112
113 /**
114 * Does a read to a given address.
115 * @param addr The address to read.
116 * @param data The read's data is written into this parameter.
117 * @param flags The request's flags.
118 * @return Returns any fault due to the read.
119 */
120 template <class T>
121 Fault read(Addr addr, T &data, unsigned flags);
122
123 /**
124 * Does a write to a given address.
125 * @param data The data to be written.
126 * @param addr The address to write to.
127 * @param flags The request's flags.
128 * @param res The result of the write (for load locked/store conditionals).
129 * @return Returns any fault due to the write.
130 */
131 template <class T>
132 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
133
134 /** Splits a request in two if it crosses a dcache block. */
135 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
136 RequestPtr &sreqHigh);
137
138 /** Initiate a DTB address translation. */
139 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
140 RequestPtr sreqHigh, uint64_t *res,
141 BaseTLB::Mode mode);
142
143 /** Finish a DTB address translation. */
144 void finishTranslation(WholeTranslationState *state);
145
146 void prefetch(Addr addr, unsigned flags);
147 void writeHint(Addr addr, int size, unsigned flags);
148 Fault copySrcTranslate(Addr src);
149 Fault copy(Addr dest);
150
151 /** @todo: Consider making this private. */
152 public:
153 /** The sequence number of the instruction. */
154 InstSeqNum seqNum;
155
156 enum Status {
157 IqEntry, /// Instruction is in the IQ
158 RobEntry, /// Instruction is in the ROB
159 LsqEntry, /// Instruction is in the LSQ
160 Completed, /// Instruction has completed
161 ResultReady, /// Instruction has its result
162 CanIssue, /// Instruction can issue and execute
163 Issued, /// Instruction has issued
164 Executed, /// Instruction has executed
165 CanCommit, /// Instruction can commit
166 AtCommit, /// Instruction has reached commit
167 Committed, /// Instruction has committed
168 Squashed, /// Instruction is squashed
169 SquashedInIQ, /// Instruction is squashed in the IQ
170 SquashedInLSQ, /// Instruction is squashed in the LSQ
171 SquashedInROB, /// Instruction is squashed in the ROB
172 RecoverInst, /// Is a recover instruction
173 BlockingInst, /// Is a blocking instruction
174 ThreadsyncWait, /// Is a thread synchronization instruction
175 SerializeBefore, /// Needs to serialize on
176 /// instructions ahead of it
177 SerializeAfter, /// Needs to serialize instructions behind it
178 SerializeHandled, /// Serialization has been handled
179 NumStatus
180 };
181
182 /** The status of this BaseDynInst. Several bits can be set. */
183 std::bitset<NumStatus> status;
184
185 /** The thread this instruction is from. */
186 ThreadID threadNumber;
187
188 /** data address space ID, for loads & stores. */
189 short asid;
190
191 /** How many source registers are ready. */
192 unsigned readyRegs;
193
194 /** Pointer to the Impl's CPU object. */
195 ImplCPU *cpu;
196
197 /** Pointer to the thread state. */
198 ImplState *thread;
199
200 /** The kind of fault this instruction has generated. */
201 Fault fault;
202
203 /** Pointer to the data for the memory access. */
204 uint8_t *memData;
205
206 /** The effective virtual address (lds & stores only). */
207 Addr effAddr;
208
209 /** Is the effective virtual address valid. */
210 bool effAddrValid;
211
212 /** The effective physical address. */
213 Addr physEffAddr;
214
215 /** Effective virtual address for a copy source. */
216 Addr copySrcEffAddr;
217
218 /** Effective physical address for a copy source. */
219 Addr copySrcPhysEffAddr;
220
221 /** The memory request flags (from translation). */
222 unsigned memReqFlags;
223
224 union Result {
225 uint64_t integer;
226// float fp;
227 double dbl;
228 };
229
230 /** The result of the instruction; assumes for now that there's only one
231 * destination register.
232 */
233 Result instResult;
234
235 /** Records changes to result? */
236 bool recordResult;
237
238 /** PC of this instruction. */
239 Addr PC;
240
241 /** Micro PC of this instruction. */
242 Addr microPC;
243
244 protected:
245 /** Next non-speculative PC. It is not filled in at fetch, but rather
246 * once the target of the branch is truly known (either decode or
247 * execute).
248 */
249 Addr nextPC;
250
251 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
252 Addr nextNPC;
253
254 /** Next non-speculative micro PC. */
255 Addr nextMicroPC;
256
257 /** Predicted next PC. */
258 Addr predPC;
259
260 /** Predicted next NPC. */
261 Addr predNPC;
262
263 /** Predicted next microPC */
264 Addr predMicroPC;
265
266 /** If this is a branch that was predicted taken */
267 bool predTaken;
268
269 public:
270
271#ifdef DEBUG
272 void dumpSNList();
273#endif
274
275 /** Whether or not the source register is ready.
276 * @todo: Not sure this should be here vs the derived class.
277 */
278 bool _readySrcRegIdx[MaxInstSrcRegs];
279
280 protected:
281 /** Flattened register index of the destination registers of this
282 * instruction.
283 */
284 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
285
286 /** Flattened register index of the source registers of this
287 * instruction.
288 */
289 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
290
291 /** Physical register index of the destination registers of this
292 * instruction.
293 */
294 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
295
296 /** Physical register index of the source registers of this
297 * instruction.
298 */
299 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
300
301 /** Physical register index of the previous producers of the
302 * architected destinations.
303 */
304 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
305
306 public:
307
308 /** Returns the physical register index of the i'th destination
309 * register.
310 */
311 PhysRegIndex renamedDestRegIdx(int idx) const
312 {
313 return _destRegIdx[idx];
314 }
315
316 /** Returns the physical register index of the i'th source register. */
317 PhysRegIndex renamedSrcRegIdx(int idx) const
318 {
319 return _srcRegIdx[idx];
320 }
321
322 /** Returns the flattened register index of the i'th destination
323 * register.
324 */
325 TheISA::RegIndex flattenedDestRegIdx(int idx) const
326 {
327 return _flatDestRegIdx[idx];
328 }
329
330 /** Returns the flattened register index of the i'th source register */
331 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
332 {
333 return _flatSrcRegIdx[idx];
334 }
335
336 /** Returns the physical register index of the previous physical register
337 * that remapped to the same logical register index.
338 */
339 PhysRegIndex prevDestRegIdx(int idx) const
340 {
341 return _prevDestRegIdx[idx];
342 }
343
344 /** Renames a destination register to a physical register. Also records
345 * the previous physical register that the logical register mapped to.
346 */
347 void renameDestReg(int idx,
348 PhysRegIndex renamed_dest,
349 PhysRegIndex previous_rename)
350 {
351 _destRegIdx[idx] = renamed_dest;
352 _prevDestRegIdx[idx] = previous_rename;
353 }
354
355 /** Renames a source logical register to the physical register which
356 * has/will produce that logical register's result.
357 * @todo: add in whether or not the source register is ready.
358 */
359 void renameSrcReg(int idx, PhysRegIndex renamed_src)
360 {
361 _srcRegIdx[idx] = renamed_src;
362 }
363
364 /** Flattens a source architectural register index into a logical index.
365 */
366 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
367 {
368 _flatSrcRegIdx[idx] = flattened_src;
369 }
370
371 /** Flattens a destination architectural register index into a logical
372 * index.
373 */
374 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
375 {
376 _flatDestRegIdx[idx] = flattened_dest;
377 }
378 /** BaseDynInst constructor given a binary instruction.
379 * @param staticInst A StaticInstPtr to the underlying instruction.
380 * @param PC The PC of the instruction.
381 * @param pred_PC The predicted next PC.
382 * @param pred_NPC The predicted next NPC.
383 * @param seq_num The sequence number of the instruction.
384 * @param cpu Pointer to the instruction's CPU.
385 */
386 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
387 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
388 InstSeqNum seq_num, ImplCPU *cpu);
389
390 /** BaseDynInst constructor given a binary instruction.
391 * @param inst The binary instruction.
392 * @param PC The PC of the instruction.
393 * @param pred_PC The predicted next PC.
394 * @param pred_NPC The predicted next NPC.
395 * @param seq_num The sequence number of the instruction.
396 * @param cpu Pointer to the instruction's CPU.
397 */
398 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
399 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
400 InstSeqNum seq_num, ImplCPU *cpu);
401
402 /** BaseDynInst constructor given a StaticInst pointer.
403 * @param _staticInst The StaticInst for this BaseDynInst.
404 */
405 BaseDynInst(StaticInstPtr &_staticInst);
406
407 /** BaseDynInst destructor. */
408 ~BaseDynInst();
409
410 private:
411 /** Function to initialize variables in the constructors. */
412 void initVars();
413
414 public:
415 /** Dumps out contents of this BaseDynInst. */
416 void dump();
417
418 /** Dumps out contents of this BaseDynInst into given string. */
419 void dump(std::string &outstring);
420
421 /** Read this CPU's ID. */
422 int cpuId() { return cpu->cpuId(); }
423
424 /** Read this context's system-wide ID **/
425 int contextId() { return thread->contextId(); }
426
427 /** Returns the fault type. */
428 Fault getFault() { return fault; }
429
430 /** Checks whether or not this instruction has had its branch target
431 * calculated yet. For now it is not utilized and is hacked to be
432 * always false.
433 * @todo: Actually use this instruction.
434 */
435 bool doneTargCalc() { return false; }
436
437 /** Returns the next PC. This could be the speculative next PC if it is
438 * called prior to the actual branch target being calculated.
439 */
440 Addr readNextPC() { return nextPC; }
441
442 /** Returns the next NPC. This could be the speculative next NPC if it is
443 * called prior to the actual branch target being calculated.
444 */
445 Addr readNextNPC()
446 {
447#if ISA_HAS_DELAY_SLOT
448 return nextNPC;
449#else
450 return nextPC + sizeof(TheISA::MachInst);
451#endif
452 }
453
454 Addr readNextMicroPC()
455 {
456 return nextMicroPC;
457 }
458
459 /** Set the predicted target of this current instruction. */
460 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
461 Addr predicted_MicroPC)
462 {
463 predPC = predicted_PC;
464 predNPC = predicted_NPC;
465 predMicroPC = predicted_MicroPC;
466 }
467
468 /** Returns the predicted PC immediately after the branch. */
469 Addr readPredPC() { return predPC; }
470
471 /** Returns the predicted PC two instructions after the branch */
472 Addr readPredNPC() { return predNPC; }
473
474 /** Returns the predicted micro PC after the branch */
475 Addr readPredMicroPC() { return predMicroPC; }
476
477 /** Returns whether the instruction was predicted taken or not. */
478 bool readPredTaken()
479 {
480 return predTaken;
481 }
482
483 void setPredTaken(bool predicted_taken)
484 {
485 predTaken = predicted_taken;
486 }
487
488 /** Returns whether the instruction mispredicted. */
489 bool mispredicted()
490 {
491 return readPredPC() != readNextPC() ||
492 readPredNPC() != readNextNPC() ||
493 readPredMicroPC() != readNextMicroPC();
494 }
495
496 //
497 // Instruction types. Forward checks to StaticInst object.
498 //
499 bool isNop() const { return staticInst->isNop(); }
500 bool isMemRef() const { return staticInst->isMemRef(); }
501 bool isLoad() const { return staticInst->isLoad(); }
502 bool isStore() const { return staticInst->isStore(); }
503 bool isStoreConditional() const
504 { return staticInst->isStoreConditional(); }
505 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
506 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
507 bool isCopy() const { return staticInst->isCopy(); }
508 bool isInteger() const { return staticInst->isInteger(); }
509 bool isFloating() const { return staticInst->isFloating(); }
510 bool isControl() const { return staticInst->isControl(); }
511 bool isCall() const { return staticInst->isCall(); }
512 bool isReturn() const { return staticInst->isReturn(); }
513 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
514 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
515 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
516 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
517 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
518 bool isThreadSync() const { return staticInst->isThreadSync(); }
519 bool isSerializing() const { return staticInst->isSerializing(); }
520 bool isSerializeBefore() const
521 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
522 bool isSerializeAfter() const
523 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
524 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
525 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
526 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
527 bool isQuiesce() const { return staticInst->isQuiesce(); }
528 bool isIprAccess() const { return staticInst->isIprAccess(); }
529 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
530 bool isSyscall() const { return staticInst->isSyscall(); }
531 bool isMacroop() const { return staticInst->isMacroop(); }
532 bool isMicroop() const { return staticInst->isMicroop(); }
533 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
534 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
535 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
536 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
537
538 /** Temporarily sets this instruction as a serialize before instruction. */
539 void setSerializeBefore() { status.set(SerializeBefore); }
540
541 /** Clears the serializeBefore part of this instruction. */
542 void clearSerializeBefore() { status.reset(SerializeBefore); }
543
544 /** Checks if this serializeBefore is only temporarily set. */
545 bool isTempSerializeBefore() { return status[SerializeBefore]; }
546
547 /** Temporarily sets this instruction as a serialize after instruction. */
548 void setSerializeAfter() { status.set(SerializeAfter); }
549
550 /** Clears the serializeAfter part of this instruction.*/
551 void clearSerializeAfter() { status.reset(SerializeAfter); }
552
553 /** Checks if this serializeAfter is only temporarily set. */
554 bool isTempSerializeAfter() { return status[SerializeAfter]; }
555
556 /** Sets the serialization part of this instruction as handled. */
557 void setSerializeHandled() { status.set(SerializeHandled); }
558
559 /** Checks if the serialization part of this instruction has been
560 * handled. This does not apply to the temporary serializing
561 * state; it only applies to this instruction's own permanent
562 * serializing state.
563 */
564 bool isSerializeHandled() { return status[SerializeHandled]; }
565
566 /** Returns the opclass of this instruction. */
567 OpClass opClass() const { return staticInst->opClass(); }
568
569 /** Returns the branch target address. */
570 Addr branchTarget() const { return staticInst->branchTarget(PC); }
571
572 /** Returns the number of source registers. */
573 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
574
575 /** Returns the number of destination registers. */
576 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
577
578 // the following are used to track physical register usage
579 // for machines with separate int & FP reg files
580 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
581 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
582
583 /** Returns the logical register index of the i'th destination register. */
584 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
585
586 /** Returns the logical register index of the i'th source register. */
587 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
588
589 /** Returns the result of an integer instruction. */
590 uint64_t readIntResult() { return instResult.integer; }
591
592 /** Returns the result of a floating point instruction. */
593 float readFloatResult() { return (float)instResult.dbl; }
594
595 /** Returns the result of a floating point (double) instruction. */
596 double readDoubleResult() { return instResult.dbl; }
597
598 /** Records an integer register being set to a value. */
599 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
600 {
601 if (recordResult)
602 instResult.integer = val;
603 }
604
605 /** Records an fp register being set to a value. */
606 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
607 int width)
608 {
609 if (recordResult) {
610 if (width == 32)
611 instResult.dbl = (double)val;
612 else if (width == 64)
613 instResult.dbl = val;
614 else
615 panic("Unsupported width!");
616 }
617 }
618
619 /** Records an fp register being set to a value. */
620 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
621 {
622 if (recordResult)
623 instResult.dbl = (double)val;
624 }
625
626 /** Records an fp register being set to an integer value. */
627 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
628 int width)
629 {
630 if (recordResult)
631 instResult.integer = val;
632 }
633
634 /** Records an fp register being set to an integer value. */
635 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
636 {
637 if (recordResult)
638 instResult.integer = val;
639 }
640
641 /** Records that one of the source registers is ready. */
642 void markSrcRegReady();
643
644 /** Marks a specific register as ready. */
645 void markSrcRegReady(RegIndex src_idx);
646
647 /** Returns if a source register is ready. */
648 bool isReadySrcRegIdx(int idx) const
649 {
650 return this->_readySrcRegIdx[idx];
651 }
652
653 /** Sets this instruction as completed. */
654 void setCompleted() { status.set(Completed); }
655
656 /** Returns whether or not this instruction is completed. */
657 bool isCompleted() const { return status[Completed]; }
658
659 /** Marks the result as ready. */
660 void setResultReady() { status.set(ResultReady); }
661
662 /** Returns whether or not the result is ready. */
663 bool isResultReady() const { return status[ResultReady]; }
664
665 /** Sets this instruction as ready to issue. */
666 void setCanIssue() { status.set(CanIssue); }
667
668 /** Returns whether or not this instruction is ready to issue. */
669 bool readyToIssue() const { return status[CanIssue]; }
670
671 /** Clears this instruction being able to issue. */
672 void clearCanIssue() { status.reset(CanIssue); }
673
674 /** Sets this instruction as issued from the IQ. */
675 void setIssued() { status.set(Issued); }
676
677 /** Returns whether or not this instruction has issued. */
678 bool isIssued() const { return status[Issued]; }
679
680 /** Clears this instruction as being issued. */
681 void clearIssued() { status.reset(Issued); }
682
683 /** Sets this instruction as executed. */
684 void setExecuted() { status.set(Executed); }
685
686 /** Returns whether or not this instruction has executed. */
687 bool isExecuted() const { return status[Executed]; }
688
689 /** Sets this instruction as ready to commit. */
690 void setCanCommit() { status.set(CanCommit); }
691
692 /** Clears this instruction as being ready to commit. */
693 void clearCanCommit() { status.reset(CanCommit); }
694
695 /** Returns whether or not this instruction is ready to commit. */
696 bool readyToCommit() const { return status[CanCommit]; }
697
698 void setAtCommit() { status.set(AtCommit); }
699
700 bool isAtCommit() { return status[AtCommit]; }
701
702 /** Sets this instruction as committed. */
703 void setCommitted() { status.set(Committed); }
704
705 /** Returns whether or not this instruction is committed. */
706 bool isCommitted() const { return status[Committed]; }
707
708 /** Sets this instruction as squashed. */
709 void setSquashed() { status.set(Squashed); }
710
711 /** Returns whether or not this instruction is squashed. */
712 bool isSquashed() const { return status[Squashed]; }
713
714 //Instruction Queue Entry
715 //-----------------------
716 /** Sets this instruction as a entry the IQ. */
717 void setInIQ() { status.set(IqEntry); }
718
719 /** Sets this instruction as a entry the IQ. */
720 void clearInIQ() { status.reset(IqEntry); }
721
722 /** Returns whether or not this instruction has issued. */
723 bool isInIQ() const { return status[IqEntry]; }
724
725 /** Sets this instruction as squashed in the IQ. */
726 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
727
728 /** Returns whether or not this instruction is squashed in the IQ. */
729 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
730
731
732 //Load / Store Queue Functions
733 //-----------------------
734 /** Sets this instruction as a entry the LSQ. */
735 void setInLSQ() { status.set(LsqEntry); }
736
737 /** Sets this instruction as a entry the LSQ. */
738 void removeInLSQ() { status.reset(LsqEntry); }
739
740 /** Returns whether or not this instruction is in the LSQ. */
741 bool isInLSQ() const { return status[LsqEntry]; }
742
743 /** Sets this instruction as squashed in the LSQ. */
744 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
745
746 /** Returns whether or not this instruction is squashed in the LSQ. */
747 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
748
749
750 //Reorder Buffer Functions
751 //-----------------------
752 /** Sets this instruction as a entry the ROB. */
753 void setInROB() { status.set(RobEntry); }
754
755 /** Sets this instruction as a entry the ROB. */
756 void clearInROB() { status.reset(RobEntry); }
757
758 /** Returns whether or not this instruction is in the ROB. */
759 bool isInROB() const { return status[RobEntry]; }
760
761 /** Sets this instruction as squashed in the ROB. */
762 void setSquashedInROB() { status.set(SquashedInROB); }
763
764 /** Returns whether or not this instruction is squashed in the ROB. */
765 bool isSquashedInROB() const { return status[SquashedInROB]; }
766
767 /** Read the PC of this instruction. */
768 const Addr readPC() const { return PC; }
769
770 /**Read the micro PC of this instruction. */
771 const Addr readMicroPC() const { return microPC; }
772
773 /** Set the next PC of this instruction (its actual target). */
774 void setNextPC(Addr val)
775 {
776 nextPC = val;
777 }
778
779 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
780 void setNextNPC(Addr val)
781 {
782#if ISA_HAS_DELAY_SLOT
783 nextNPC = val;
784#endif
785 }
786
787 void setNextMicroPC(Addr val)
788 {
789 nextMicroPC = val;
790 }
791
792 /** Sets the ASID. */
793 void setASID(short addr_space_id) { asid = addr_space_id; }
794
795 /** Sets the thread id. */
796 void setTid(ThreadID tid) { threadNumber = tid; }
797
798 /** Sets the pointer to the thread state. */
799 void setThreadState(ImplState *state) { thread = state; }
800
801 /** Returns the thread context. */
802 ThreadContext *tcBase() { return thread->getTC(); }
803
804 private:
805 /** Instruction effective address.
806 * @todo: Consider if this is necessary or not.
807 */
808 Addr instEffAddr;
809
810 /** Whether or not the effective address calculation is completed.
811 * @todo: Consider if this is necessary or not.
812 */
813 bool eaCalcDone;
814
815 /** Is this instruction's memory access uncacheable. */
816 bool isUncacheable;
817
818 /** Has this instruction generated a memory request. */
819 bool reqMade;
820
821 public:
822 /** Sets the effective address. */
823 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
824
825 /** Returns the effective address. */
826 const Addr &getEA() const { return instEffAddr; }
827
828 /** Returns whether or not the eff. addr. calculation has been completed. */
829 bool doneEACalc() { return eaCalcDone; }
830
831 /** Returns whether or not the eff. addr. source registers are ready. */
832 bool eaSrcsReady();
833
834 /** Whether or not the memory operation is done. */
835 bool memOpDone;
836
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return isUncacheable; }
839
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return reqMade; }
842
843 public:
844 /** Load queue index. */
845 int16_t lqIdx;
846
847 /** Store queue index. */
848 int16_t sqIdx;
849
850 /** Iterator pointing to this BaseDynInst in the list of all insts. */
851 ListIt instListIt;
852
853 /** Returns iterator to this instruction in the list of all insts. */
854 ListIt &getInstListIt() { return instListIt; }
855
856 /** Sets iterator for this instruction in the list of all insts. */
857 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
858
859 public:
860 /** Returns the number of consecutive store conditional failures. */
861 unsigned readStCondFailures()
862 { return thread->storeCondFailures; }
863
864 /** Sets the number of consecutive store conditional failures. */
865 void setStCondFailures(unsigned sc_failures)
866 { thread->storeCondFailures = sc_failures; }
867};
868
869template<class Impl>
870template<class T>
871inline Fault
872BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
873{
874 reqMade = true;
875 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
876 thread->contextId(), threadNumber);
877
878 Request *sreqLow = NULL;
879 Request *sreqHigh = NULL;
880
881 // Only split the request if the ISA supports unaligned accesses.
882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
884 }
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
889 effAddrValid = true;
|
937 }
938
939 return fault;
940}
941
942template<class Impl>
943inline void
944BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
945 RequestPtr &sreqHigh)
946{
947 // Check to see if the request crosses the next level block boundary.
948 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
949 Addr addr = req->getVaddr();
950 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
951 assert(split_addr <= addr || split_addr - addr < block_size);
952
953 // Spans two blocks.
954 if (split_addr > addr) {
955 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
956 }
957}
958
959template<class Impl>
960inline void
961BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
962 RequestPtr sreqHigh, uint64_t *res,
963 BaseTLB::Mode mode)
964{
965 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
966 WholeTranslationState *state =
967 new WholeTranslationState(req, NULL, res, mode);
968
969 // One translation if the request isn't split.
970 DataTranslation<BaseDynInst<Impl> > *trans =
971 new DataTranslation<BaseDynInst<Impl> >(this, state);
972 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
973 } else {
974 WholeTranslationState *state =
975 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
976
977 // Two translations when the request is split.
978 DataTranslation<BaseDynInst<Impl> > *stransLow =
979 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
980 DataTranslation<BaseDynInst<Impl> > *stransHigh =
981 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
982
983 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
984 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
985 }
986}
987
988template<class Impl>
989inline void
990BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
991{
992 fault = state->getFault();
993
994 if (state->isUncacheable())
995 isUncacheable = true;
996
997 if (fault == NoFault) {
998 physEffAddr = state->getPaddr();
999 memReqFlags = state->getFlags();
1000
1001 if (state->mainReq->isCondSwap()) {
1002 assert(state->res);
1003 state->mainReq->setExtraData(*state->res);
1004 }
1005
1006 } else {
1007 state->deleteReqs();
1008 }
1009 delete state;
1010}
1011
1012#endif // __CPU_BASE_DYN_INST_HH__
| 937 }
938
939 return fault;
940}
941
942template<class Impl>
943inline void
944BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
945 RequestPtr &sreqHigh)
946{
947 // Check to see if the request crosses the next level block boundary.
948 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
949 Addr addr = req->getVaddr();
950 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
951 assert(split_addr <= addr || split_addr - addr < block_size);
952
953 // Spans two blocks.
954 if (split_addr > addr) {
955 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
956 }
957}
958
959template<class Impl>
960inline void
961BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
962 RequestPtr sreqHigh, uint64_t *res,
963 BaseTLB::Mode mode)
964{
965 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
966 WholeTranslationState *state =
967 new WholeTranslationState(req, NULL, res, mode);
968
969 // One translation if the request isn't split.
970 DataTranslation<BaseDynInst<Impl> > *trans =
971 new DataTranslation<BaseDynInst<Impl> >(this, state);
972 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
973 } else {
974 WholeTranslationState *state =
975 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
976
977 // Two translations when the request is split.
978 DataTranslation<BaseDynInst<Impl> > *stransLow =
979 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
980 DataTranslation<BaseDynInst<Impl> > *stransHigh =
981 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
982
983 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
984 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
985 }
986}
987
988template<class Impl>
989inline void
990BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
991{
992 fault = state->getFault();
993
994 if (state->isUncacheable())
995 isUncacheable = true;
996
997 if (fault == NoFault) {
998 physEffAddr = state->getPaddr();
999 memReqFlags = state->getFlags();
1000
1001 if (state->mainReq->isCondSwap()) {
1002 assert(state->res);
1003 state->mainReq->setExtraData(*state->res);
1004 }
1005
1006 } else {
1007 state->deleteReqs();
1008 }
1009 delete state;
1010}
1011
1012#endif // __CPU_BASE_DYN_INST_HH__
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