1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/o3/comm.hh"
43#include "cpu/exetrace.hh"
44#include "cpu/inst_seq.hh"
45#include "cpu/op_class.hh"
46#include "cpu/static_inst.hh"
47#include "mem/packet.hh"
48#include "sim/system.hh"
49
50/**
51 * @file
52 * Defines a dynamic instruction context.
53 */
54
55// Forward declaration.
56class StaticInstPtr;
57
58template <class Impl>
59class BaseDynInst : public FastAlloc, public RefCounted
60{
61 public:
62 // Typedef for the CPU.
63 typedef typename Impl::CPUType ImplCPU;
64 typedef typename ImplCPU::ImplState ImplState;
65
66 // Logical register index type.
67 typedef TheISA::RegIndex RegIndex;
68 // Integer register type.
69 typedef TheISA::IntReg IntReg;
70 // Floating point register type.
71 typedef TheISA::FloatReg FloatReg;
72
73 // The DynInstPtr type.
74 typedef typename Impl::DynInstPtr DynInstPtr;
75
76 // The list of instructions iterator type.
77 typedef typename std::list<DynInstPtr>::iterator ListIt;
78
79 enum {
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
82 };
83
84 /** The StaticInst used by this BaseDynInst. */
85 StaticInstPtr staticInst;
86
87 ////////////////////////////////////////////
88 //
89 // INSTRUCTION EXECUTION
90 //
91 ////////////////////////////////////////////
92 /** InstRecord that tracks this instructions. */
93 Trace::InstRecord *traceData;
94
95 /**
96 * Does a read to a given address.
97 * @param addr The address to read.
98 * @param data The read's data is written into this parameter.
99 * @param flags The request's flags.
100 * @return Returns any fault due to the read.
101 */
102 template <class T>
103 Fault read(Addr addr, T &data, unsigned flags);
104
105 /**
106 * Does a write to a given address.
107 * @param data The data to be written.
108 * @param addr The address to write to.
109 * @param flags The request's flags.
110 * @param res The result of the write (for load locked/store conditionals).
111 * @return Returns any fault due to the write.
112 */
113 template <class T>
114 Fault write(T data, Addr addr, unsigned flags,
115 uint64_t *res);
116
117 void prefetch(Addr addr, unsigned flags);
118 void writeHint(Addr addr, int size, unsigned flags);
119 Fault copySrcTranslate(Addr src);
120 Fault copy(Addr dest);
121
122 /** @todo: Consider making this private. */
123 public:
124 /** The sequence number of the instruction. */
125 InstSeqNum seqNum;
126
127 enum Status {
128 IqEntry, /// Instruction is in the IQ
129 RobEntry, /// Instruction is in the ROB
130 LsqEntry, /// Instruction is in the LSQ
131 Completed, /// Instruction has completed
132 ResultReady, /// Instruction has its result
133 CanIssue, /// Instruction can issue and execute
134 Issued, /// Instruction has issued
135 Executed, /// Instruction has executed
136 CanCommit, /// Instruction can commit
137 AtCommit, /// Instruction has reached commit
138 Committed, /// Instruction has committed
139 Squashed, /// Instruction is squashed
140 SquashedInIQ, /// Instruction is squashed in the IQ
141 SquashedInLSQ, /// Instruction is squashed in the LSQ
142 SquashedInROB, /// Instruction is squashed in the ROB
143 RecoverInst, /// Is a recover instruction
144 BlockingInst, /// Is a blocking instruction
145 ThreadsyncWait, /// Is a thread synchronization instruction
146 SerializeBefore, /// Needs to serialize on
147 /// instructions ahead of it
148 SerializeAfter, /// Needs to serialize instructions behind it
149 SerializeHandled, /// Serialization has been handled
150 NumStatus
151 };
152
153 /** The status of this BaseDynInst. Several bits can be set. */
154 std::bitset<NumStatus> status;
155
156 /** The thread this instruction is from. */
157 short threadNumber;
158
159 /** data address space ID, for loads & stores. */
160 short asid;
161
162 /** How many source registers are ready. */
163 unsigned readyRegs;
164
165 /** Pointer to the Impl's CPU object. */
166 ImplCPU *cpu;
167
168 /** Pointer to the thread state. */
169 ImplState *thread;
170
171 /** The kind of fault this instruction has generated. */
172 Fault fault;
173
174 /** Pointer to the data for the memory access. */
175 uint8_t *memData;
176
177 /** The effective virtual address (lds & stores only). */
178 Addr effAddr;
179
180 /** Is the effective virtual address valid. */
181 bool effAddrValid;
182
183 /** The effective physical address. */
184 Addr physEffAddr;
185
186 /** Effective virtual address for a copy source. */
187 Addr copySrcEffAddr;
188
189 /** Effective physical address for a copy source. */
190 Addr copySrcPhysEffAddr;
191
192 /** The memory request flags (from translation). */
193 unsigned memReqFlags;
194
195 union Result {
196 uint64_t integer;
197// float fp;
198 double dbl;
199 };
200
201 /** The result of the instruction; assumes for now that there's only one
202 * destination register.
203 */
204 Result instResult;
205
206 /** Records changes to result? */
207 bool recordResult;
208
209 /** PC of this instruction. */
210 Addr PC;
211
212 protected:
213 /** Next non-speculative PC. It is not filled in at fetch, but rather
214 * once the target of the branch is truly known (either decode or
215 * execute).
216 */
217 Addr nextPC;
218
219 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
220 Addr nextNPC;
221
222 /** Predicted next PC. */
223 Addr predPC;
224
225 /** Predicted next NPC. */
226 Addr predNPC;
227
228 /** If this is a branch that was predicted taken */
229 bool predTaken;
230
231 public:
232
233 /** Count of total number of dynamic instructions. */
234 static int instcount;
235
236#ifdef DEBUG
237 void dumpSNList();
238#endif
239
240 /** Whether or not the source register is ready.
241 * @todo: Not sure this should be here vs the derived class.
242 */
243 bool _readySrcRegIdx[MaxInstSrcRegs];
244
245 protected:
246 /** Flattened register index of the destination registers of this
247 * instruction.
248 */
249 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
250
251 /** Flattened register index of the source registers of this
252 * instruction.
253 */
254 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
255
256 /** Physical register index of the destination registers of this
257 * instruction.
258 */
259 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
260
261 /** Physical register index of the source registers of this
262 * instruction.
263 */
264 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
265
266 /** Physical register index of the previous producers of the
267 * architected destinations.
268 */
269 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
270
271 public:
272
273 /** Returns the physical register index of the i'th destination
274 * register.
275 */
276 PhysRegIndex renamedDestRegIdx(int idx) const
277 {
278 return _destRegIdx[idx];
279 }
280
281 /** Returns the physical register index of the i'th source register. */
282 PhysRegIndex renamedSrcRegIdx(int idx) const
283 {
284 return _srcRegIdx[idx];
285 }
286
287 /** Returns the flattened register index of the i'th destination
288 * register.
289 */
290 TheISA::RegIndex flattenedDestRegIdx(int idx) const
291 {
292 return _flatDestRegIdx[idx];
293 }
294
295 /** Returns the flattened register index of the i'th source register */
296 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
297 {
298 return _flatSrcRegIdx[idx];
299 }
300
301 /** Returns the physical register index of the previous physical register
302 * that remapped to the same logical register index.
303 */
304 PhysRegIndex prevDestRegIdx(int idx) const
305 {
306 return _prevDestRegIdx[idx];
307 }
308
309 /** Renames a destination register to a physical register. Also records
310 * the previous physical register that the logical register mapped to.
311 */
312 void renameDestReg(int idx,
313 PhysRegIndex renamed_dest,
314 PhysRegIndex previous_rename)
315 {
316 _destRegIdx[idx] = renamed_dest;
317 _prevDestRegIdx[idx] = previous_rename;
318 }
319
320 /** Renames a source logical register to the physical register which
321 * has/will produce that logical register's result.
322 * @todo: add in whether or not the source register is ready.
323 */
324 void renameSrcReg(int idx, PhysRegIndex renamed_src)
325 {
326 _srcRegIdx[idx] = renamed_src;
327 }
328
329 /** Flattens a source architectural register index into a logical index.
330 */
331 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
332 {
333 _flatSrcRegIdx[idx] = flattened_src;
334 }
335
336 /** Flattens a destination architectural register index into a logical
337 * index.
338 */
339 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
340 {
341 _flatDestRegIdx[idx] = flattened_dest;
342 }
343
344 /** BaseDynInst constructor given a binary instruction.
345 * @param inst The binary instruction.
346 * @param PC The PC of the instruction.
347 * @param pred_PC The predicted next PC.
348 * @param pred_NPC The predicted next NPC.
349 * @param seq_num The sequence number of the instruction.
350 * @param cpu Pointer to the instruction's CPU.
351 */
352 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC,
353 Addr pred_PC, Addr pred_NPC,
354 InstSeqNum seq_num, ImplCPU *cpu);
355
356 /** BaseDynInst constructor given a StaticInst pointer.
357 * @param _staticInst The StaticInst for this BaseDynInst.
358 */
359 BaseDynInst(StaticInstPtr &_staticInst);
360
361 /** BaseDynInst destructor. */
362 ~BaseDynInst();
363
364 private:
365 /** Function to initialize variables in the constructors. */
366 void initVars();
367
368 public:
369 /** Dumps out contents of this BaseDynInst. */
370 void dump();
371
372 /** Dumps out contents of this BaseDynInst into given string. */
373 void dump(std::string &outstring);
374
375 /** Read this CPU's ID. */
376 int readCpuId() { return cpu->readCpuId(); }
377
378 /** Returns the fault type. */
379 Fault getFault() { return fault; }
380
381 /** Checks whether or not this instruction has had its branch target
382 * calculated yet. For now it is not utilized and is hacked to be
383 * always false.
384 * @todo: Actually use this instruction.
385 */
386 bool doneTargCalc() { return false; }
387
388 /** Returns the next PC. This could be the speculative next PC if it is
389 * called prior to the actual branch target being calculated.
390 */
391 Addr readNextPC() { return nextPC; }
392
393 /** Returns the next NPC. This could be the speculative next NPC if it is
394 * called prior to the actual branch target being calculated.
395 */
396 Addr readNextNPC()
397 {
398#if ISA_HAS_DELAY_SLOT
399 return nextNPC;
400#else
401 return nextPC + sizeof(TheISA::MachInst);
402#endif
403 }
404
405 /** Set the predicted target of this current instruction. */
406 void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
407 {
408 predPC = predicted_PC;
409 predNPC = predicted_NPC;
410 }
411
412 /** Returns the predicted PC immediately after the branch. */
413 Addr readPredPC() { return predPC; }
414
415 /** Returns the predicted PC two instructions after the branch */
416 Addr readPredNPC() { return predNPC; }
417
418 /** Returns whether the instruction was predicted taken or not. */
419 bool readPredTaken()
420 {
421 return predTaken;
422 }
423
424 void setPredTaken(bool predicted_taken)
425 {
426 predTaken = predicted_taken;
427 }
428
429 /** Returns whether the instruction mispredicted. */
430 bool mispredicted()
431 {
432 return readPredPC() != readNextPC() ||
433 readPredNPC() != readNextNPC();
434 }
435
436 //
437 // Instruction types. Forward checks to StaticInst object.
438 //
439 bool isNop() const { return staticInst->isNop(); }
440 bool isMemRef() const { return staticInst->isMemRef(); }
441 bool isLoad() const { return staticInst->isLoad(); }
442 bool isStore() const { return staticInst->isStore(); }
443 bool isStoreConditional() const
444 { return staticInst->isStoreConditional(); }
445 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
446 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
447 bool isCopy() const { return staticInst->isCopy(); }
448 bool isInteger() const { return staticInst->isInteger(); }
449 bool isFloating() const { return staticInst->isFloating(); }
450 bool isControl() const { return staticInst->isControl(); }
451 bool isCall() const { return staticInst->isCall(); }
452 bool isReturn() const { return staticInst->isReturn(); }
453 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
454 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
455 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
456 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
457 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
458 bool isThreadSync() const { return staticInst->isThreadSync(); }
459 bool isSerializing() const { return staticInst->isSerializing(); }
460 bool isSerializeBefore() const
461 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
462 bool isSerializeAfter() const
463 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
464 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
465 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
466 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
467 bool isQuiesce() const { return staticInst->isQuiesce(); }
468 bool isIprAccess() const { return staticInst->isIprAccess(); }
469 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
470
471 /** Temporarily sets this instruction as a serialize before instruction. */
472 void setSerializeBefore() { status.set(SerializeBefore); }
473
474 /** Clears the serializeBefore part of this instruction. */
475 void clearSerializeBefore() { status.reset(SerializeBefore); }
476
477 /** Checks if this serializeBefore is only temporarily set. */
478 bool isTempSerializeBefore() { return status[SerializeBefore]; }
479
480 /** Temporarily sets this instruction as a serialize after instruction. */
481 void setSerializeAfter() { status.set(SerializeAfter); }
482
483 /** Clears the serializeAfter part of this instruction.*/
484 void clearSerializeAfter() { status.reset(SerializeAfter); }
485
486 /** Checks if this serializeAfter is only temporarily set. */
487 bool isTempSerializeAfter() { return status[SerializeAfter]; }
488
489 /** Sets the serialization part of this instruction as handled. */
490 void setSerializeHandled() { status.set(SerializeHandled); }
491
492 /** Checks if the serialization part of this instruction has been
493 * handled. This does not apply to the temporary serializing
494 * state; it only applies to this instruction's own permanent
495 * serializing state.
496 */
497 bool isSerializeHandled() { return status[SerializeHandled]; }
498
499 /** Returns the opclass of this instruction. */
500 OpClass opClass() const { return staticInst->opClass(); }
501
502 /** Returns the branch target address. */
503 Addr branchTarget() const { return staticInst->branchTarget(PC); }
504
505 /** Returns the number of source registers. */
506 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
507
508 /** Returns the number of destination registers. */
509 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
510
511 // the following are used to track physical register usage
512 // for machines with separate int & FP reg files
513 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
514 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
515
516 /** Returns the logical register index of the i'th destination register. */
517 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
518
519 /** Returns the logical register index of the i'th source register. */
520 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
521
522 /** Returns the result of an integer instruction. */
523 uint64_t readIntResult() { return instResult.integer; }
524
525 /** Returns the result of a floating point instruction. */
526 float readFloatResult() { return (float)instResult.dbl; }
527
528 /** Returns the result of a floating point (double) instruction. */
529 double readDoubleResult() { return instResult.dbl; }
530
531 /** Records an integer register being set to a value. */
532 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
533 {
534 if (recordResult)
535 instResult.integer = val;
536 }
537
538 /** Records an fp register being set to a value. */
539 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
540 int width)
541 {
542 if (recordResult) {
543 if (width == 32)
544 instResult.dbl = (double)val;
545 else if (width == 64)
546 instResult.dbl = val;
547 else
548 panic("Unsupported width!");
549 }
550 }
551
552 /** Records an fp register being set to a value. */
553 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
554 {
555 if (recordResult)
556 instResult.dbl = (double)val;
557 }
558
559 /** Records an fp register being set to an integer value. */
560 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
561 int width)
562 {
563 if (recordResult)
564 instResult.integer = val;
565 }
566
567 /** Records an fp register being set to an integer value. */
568 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
569 {
570 if (recordResult)
571 instResult.integer = val;
572 }
573
574 /** Records that one of the source registers is ready. */
575 void markSrcRegReady();
576
577 /** Marks a specific register as ready. */
578 void markSrcRegReady(RegIndex src_idx);
579
580 /** Returns if a source register is ready. */
581 bool isReadySrcRegIdx(int idx) const
582 {
583 return this->_readySrcRegIdx[idx];
584 }
585
586 /** Sets this instruction as completed. */
587 void setCompleted() { status.set(Completed); }
588
589 /** Returns whether or not this instruction is completed. */
590 bool isCompleted() const { return status[Completed]; }
591
592 /** Marks the result as ready. */
593 void setResultReady() { status.set(ResultReady); }
594
595 /** Returns whether or not the result is ready. */
596 bool isResultReady() const { return status[ResultReady]; }
597
598 /** Sets this instruction as ready to issue. */
599 void setCanIssue() { status.set(CanIssue); }
600
601 /** Returns whether or not this instruction is ready to issue. */
602 bool readyToIssue() const { return status[CanIssue]; }
603
604 /** Clears this instruction being able to issue. */
605 void clearCanIssue() { status.reset(CanIssue); }
606
607 /** Sets this instruction as issued from the IQ. */
608 void setIssued() { status.set(Issued); }
609
610 /** Returns whether or not this instruction has issued. */
611 bool isIssued() const { return status[Issued]; }
612
613 /** Clears this instruction as being issued. */
614 void clearIssued() { status.reset(Issued); }
615
616 /** Sets this instruction as executed. */
617 void setExecuted() { status.set(Executed); }
618
619 /** Returns whether or not this instruction has executed. */
620 bool isExecuted() const { return status[Executed]; }
621
622 /** Sets this instruction as ready to commit. */
623 void setCanCommit() { status.set(CanCommit); }
624
625 /** Clears this instruction as being ready to commit. */
626 void clearCanCommit() { status.reset(CanCommit); }
627
628 /** Returns whether or not this instruction is ready to commit. */
629 bool readyToCommit() const { return status[CanCommit]; }
630
631 void setAtCommit() { status.set(AtCommit); }
632
633 bool isAtCommit() { return status[AtCommit]; }
634
635 /** Sets this instruction as committed. */
636 void setCommitted() { status.set(Committed); }
637
638 /** Returns whether or not this instruction is committed. */
639 bool isCommitted() const { return status[Committed]; }
640
641 /** Sets this instruction as squashed. */
642 void setSquashed() { status.set(Squashed); }
643
644 /** Returns whether or not this instruction is squashed. */
645 bool isSquashed() const { return status[Squashed]; }
646
647 //Instruction Queue Entry
648 //-----------------------
649 /** Sets this instruction as a entry the IQ. */
650 void setInIQ() { status.set(IqEntry); }
651
652 /** Sets this instruction as a entry the IQ. */
653 void clearInIQ() { status.reset(IqEntry); }
654
655 /** Returns whether or not this instruction has issued. */
656 bool isInIQ() const { return status[IqEntry]; }
657
658 /** Sets this instruction as squashed in the IQ. */
659 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
660
661 /** Returns whether or not this instruction is squashed in the IQ. */
662 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
663
664
665 //Load / Store Queue Functions
666 //-----------------------
667 /** Sets this instruction as a entry the LSQ. */
668 void setInLSQ() { status.set(LsqEntry); }
669
670 /** Sets this instruction as a entry the LSQ. */
671 void removeInLSQ() { status.reset(LsqEntry); }
672
673 /** Returns whether or not this instruction is in the LSQ. */
674 bool isInLSQ() const { return status[LsqEntry]; }
675
676 /** Sets this instruction as squashed in the LSQ. */
677 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
678
679 /** Returns whether or not this instruction is squashed in the LSQ. */
680 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
681
682
683 //Reorder Buffer Functions
684 //-----------------------
685 /** Sets this instruction as a entry the ROB. */
686 void setInROB() { status.set(RobEntry); }
687
688 /** Sets this instruction as a entry the ROB. */
689 void clearInROB() { status.reset(RobEntry); }
690
691 /** Returns whether or not this instruction is in the ROB. */
692 bool isInROB() const { return status[RobEntry]; }
693
694 /** Sets this instruction as squashed in the ROB. */
695 void setSquashedInROB() { status.set(SquashedInROB); }
696
697 /** Returns whether or not this instruction is squashed in the ROB. */
698 bool isSquashedInROB() const { return status[SquashedInROB]; }
699
700 /** Read the PC of this instruction. */
701 const Addr readPC() const { return PC; }
702
703 /** Set the next PC of this instruction (its actual target). */
704 void setNextPC(uint64_t val)
705 {
706 nextPC = val;
707 }
708
709 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
710 void setNextNPC(uint64_t val)
711 {
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/o3/comm.hh"
43#include "cpu/exetrace.hh"
44#include "cpu/inst_seq.hh"
45#include "cpu/op_class.hh"
46#include "cpu/static_inst.hh"
47#include "mem/packet.hh"
48#include "sim/system.hh"
49
50/**
51 * @file
52 * Defines a dynamic instruction context.
53 */
54
55// Forward declaration.
56class StaticInstPtr;
57
58template <class Impl>
59class BaseDynInst : public FastAlloc, public RefCounted
60{
61 public:
62 // Typedef for the CPU.
63 typedef typename Impl::CPUType ImplCPU;
64 typedef typename ImplCPU::ImplState ImplState;
65
66 // Logical register index type.
67 typedef TheISA::RegIndex RegIndex;
68 // Integer register type.
69 typedef TheISA::IntReg IntReg;
70 // Floating point register type.
71 typedef TheISA::FloatReg FloatReg;
72
73 // The DynInstPtr type.
74 typedef typename Impl::DynInstPtr DynInstPtr;
75
76 // The list of instructions iterator type.
77 typedef typename std::list<DynInstPtr>::iterator ListIt;
78
79 enum {
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
82 };
83
84 /** The StaticInst used by this BaseDynInst. */
85 StaticInstPtr staticInst;
86
87 ////////////////////////////////////////////
88 //
89 // INSTRUCTION EXECUTION
90 //
91 ////////////////////////////////////////////
92 /** InstRecord that tracks this instructions. */
93 Trace::InstRecord *traceData;
94
95 /**
96 * Does a read to a given address.
97 * @param addr The address to read.
98 * @param data The read's data is written into this parameter.
99 * @param flags The request's flags.
100 * @return Returns any fault due to the read.
101 */
102 template <class T>
103 Fault read(Addr addr, T &data, unsigned flags);
104
105 /**
106 * Does a write to a given address.
107 * @param data The data to be written.
108 * @param addr The address to write to.
109 * @param flags The request's flags.
110 * @param res The result of the write (for load locked/store conditionals).
111 * @return Returns any fault due to the write.
112 */
113 template <class T>
114 Fault write(T data, Addr addr, unsigned flags,
115 uint64_t *res);
116
117 void prefetch(Addr addr, unsigned flags);
118 void writeHint(Addr addr, int size, unsigned flags);
119 Fault copySrcTranslate(Addr src);
120 Fault copy(Addr dest);
121
122 /** @todo: Consider making this private. */
123 public:
124 /** The sequence number of the instruction. */
125 InstSeqNum seqNum;
126
127 enum Status {
128 IqEntry, /// Instruction is in the IQ
129 RobEntry, /// Instruction is in the ROB
130 LsqEntry, /// Instruction is in the LSQ
131 Completed, /// Instruction has completed
132 ResultReady, /// Instruction has its result
133 CanIssue, /// Instruction can issue and execute
134 Issued, /// Instruction has issued
135 Executed, /// Instruction has executed
136 CanCommit, /// Instruction can commit
137 AtCommit, /// Instruction has reached commit
138 Committed, /// Instruction has committed
139 Squashed, /// Instruction is squashed
140 SquashedInIQ, /// Instruction is squashed in the IQ
141 SquashedInLSQ, /// Instruction is squashed in the LSQ
142 SquashedInROB, /// Instruction is squashed in the ROB
143 RecoverInst, /// Is a recover instruction
144 BlockingInst, /// Is a blocking instruction
145 ThreadsyncWait, /// Is a thread synchronization instruction
146 SerializeBefore, /// Needs to serialize on
147 /// instructions ahead of it
148 SerializeAfter, /// Needs to serialize instructions behind it
149 SerializeHandled, /// Serialization has been handled
150 NumStatus
151 };
152
153 /** The status of this BaseDynInst. Several bits can be set. */
154 std::bitset<NumStatus> status;
155
156 /** The thread this instruction is from. */
157 short threadNumber;
158
159 /** data address space ID, for loads & stores. */
160 short asid;
161
162 /** How many source registers are ready. */
163 unsigned readyRegs;
164
165 /** Pointer to the Impl's CPU object. */
166 ImplCPU *cpu;
167
168 /** Pointer to the thread state. */
169 ImplState *thread;
170
171 /** The kind of fault this instruction has generated. */
172 Fault fault;
173
174 /** Pointer to the data for the memory access. */
175 uint8_t *memData;
176
177 /** The effective virtual address (lds & stores only). */
178 Addr effAddr;
179
180 /** Is the effective virtual address valid. */
181 bool effAddrValid;
182
183 /** The effective physical address. */
184 Addr physEffAddr;
185
186 /** Effective virtual address for a copy source. */
187 Addr copySrcEffAddr;
188
189 /** Effective physical address for a copy source. */
190 Addr copySrcPhysEffAddr;
191
192 /** The memory request flags (from translation). */
193 unsigned memReqFlags;
194
195 union Result {
196 uint64_t integer;
197// float fp;
198 double dbl;
199 };
200
201 /** The result of the instruction; assumes for now that there's only one
202 * destination register.
203 */
204 Result instResult;
205
206 /** Records changes to result? */
207 bool recordResult;
208
209 /** PC of this instruction. */
210 Addr PC;
211
212 protected:
213 /** Next non-speculative PC. It is not filled in at fetch, but rather
214 * once the target of the branch is truly known (either decode or
215 * execute).
216 */
217 Addr nextPC;
218
219 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
220 Addr nextNPC;
221
222 /** Predicted next PC. */
223 Addr predPC;
224
225 /** Predicted next NPC. */
226 Addr predNPC;
227
228 /** If this is a branch that was predicted taken */
229 bool predTaken;
230
231 public:
232
233 /** Count of total number of dynamic instructions. */
234 static int instcount;
235
236#ifdef DEBUG
237 void dumpSNList();
238#endif
239
240 /** Whether or not the source register is ready.
241 * @todo: Not sure this should be here vs the derived class.
242 */
243 bool _readySrcRegIdx[MaxInstSrcRegs];
244
245 protected:
246 /** Flattened register index of the destination registers of this
247 * instruction.
248 */
249 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
250
251 /** Flattened register index of the source registers of this
252 * instruction.
253 */
254 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
255
256 /** Physical register index of the destination registers of this
257 * instruction.
258 */
259 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
260
261 /** Physical register index of the source registers of this
262 * instruction.
263 */
264 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
265
266 /** Physical register index of the previous producers of the
267 * architected destinations.
268 */
269 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
270
271 public:
272
273 /** Returns the physical register index of the i'th destination
274 * register.
275 */
276 PhysRegIndex renamedDestRegIdx(int idx) const
277 {
278 return _destRegIdx[idx];
279 }
280
281 /** Returns the physical register index of the i'th source register. */
282 PhysRegIndex renamedSrcRegIdx(int idx) const
283 {
284 return _srcRegIdx[idx];
285 }
286
287 /** Returns the flattened register index of the i'th destination
288 * register.
289 */
290 TheISA::RegIndex flattenedDestRegIdx(int idx) const
291 {
292 return _flatDestRegIdx[idx];
293 }
294
295 /** Returns the flattened register index of the i'th source register */
296 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
297 {
298 return _flatSrcRegIdx[idx];
299 }
300
301 /** Returns the physical register index of the previous physical register
302 * that remapped to the same logical register index.
303 */
304 PhysRegIndex prevDestRegIdx(int idx) const
305 {
306 return _prevDestRegIdx[idx];
307 }
308
309 /** Renames a destination register to a physical register. Also records
310 * the previous physical register that the logical register mapped to.
311 */
312 void renameDestReg(int idx,
313 PhysRegIndex renamed_dest,
314 PhysRegIndex previous_rename)
315 {
316 _destRegIdx[idx] = renamed_dest;
317 _prevDestRegIdx[idx] = previous_rename;
318 }
319
320 /** Renames a source logical register to the physical register which
321 * has/will produce that logical register's result.
322 * @todo: add in whether or not the source register is ready.
323 */
324 void renameSrcReg(int idx, PhysRegIndex renamed_src)
325 {
326 _srcRegIdx[idx] = renamed_src;
327 }
328
329 /** Flattens a source architectural register index into a logical index.
330 */
331 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
332 {
333 _flatSrcRegIdx[idx] = flattened_src;
334 }
335
336 /** Flattens a destination architectural register index into a logical
337 * index.
338 */
339 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
340 {
341 _flatDestRegIdx[idx] = flattened_dest;
342 }
343
344 /** BaseDynInst constructor given a binary instruction.
345 * @param inst The binary instruction.
346 * @param PC The PC of the instruction.
347 * @param pred_PC The predicted next PC.
348 * @param pred_NPC The predicted next NPC.
349 * @param seq_num The sequence number of the instruction.
350 * @param cpu Pointer to the instruction's CPU.
351 */
352 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC,
353 Addr pred_PC, Addr pred_NPC,
354 InstSeqNum seq_num, ImplCPU *cpu);
355
356 /** BaseDynInst constructor given a StaticInst pointer.
357 * @param _staticInst The StaticInst for this BaseDynInst.
358 */
359 BaseDynInst(StaticInstPtr &_staticInst);
360
361 /** BaseDynInst destructor. */
362 ~BaseDynInst();
363
364 private:
365 /** Function to initialize variables in the constructors. */
366 void initVars();
367
368 public:
369 /** Dumps out contents of this BaseDynInst. */
370 void dump();
371
372 /** Dumps out contents of this BaseDynInst into given string. */
373 void dump(std::string &outstring);
374
375 /** Read this CPU's ID. */
376 int readCpuId() { return cpu->readCpuId(); }
377
378 /** Returns the fault type. */
379 Fault getFault() { return fault; }
380
381 /** Checks whether or not this instruction has had its branch target
382 * calculated yet. For now it is not utilized and is hacked to be
383 * always false.
384 * @todo: Actually use this instruction.
385 */
386 bool doneTargCalc() { return false; }
387
388 /** Returns the next PC. This could be the speculative next PC if it is
389 * called prior to the actual branch target being calculated.
390 */
391 Addr readNextPC() { return nextPC; }
392
393 /** Returns the next NPC. This could be the speculative next NPC if it is
394 * called prior to the actual branch target being calculated.
395 */
396 Addr readNextNPC()
397 {
398#if ISA_HAS_DELAY_SLOT
399 return nextNPC;
400#else
401 return nextPC + sizeof(TheISA::MachInst);
402#endif
403 }
404
405 /** Set the predicted target of this current instruction. */
406 void setPredTarg(Addr predicted_PC, Addr predicted_NPC)
407 {
408 predPC = predicted_PC;
409 predNPC = predicted_NPC;
410 }
411
412 /** Returns the predicted PC immediately after the branch. */
413 Addr readPredPC() { return predPC; }
414
415 /** Returns the predicted PC two instructions after the branch */
416 Addr readPredNPC() { return predNPC; }
417
418 /** Returns whether the instruction was predicted taken or not. */
419 bool readPredTaken()
420 {
421 return predTaken;
422 }
423
424 void setPredTaken(bool predicted_taken)
425 {
426 predTaken = predicted_taken;
427 }
428
429 /** Returns whether the instruction mispredicted. */
430 bool mispredicted()
431 {
432 return readPredPC() != readNextPC() ||
433 readPredNPC() != readNextNPC();
434 }
435
436 //
437 // Instruction types. Forward checks to StaticInst object.
438 //
439 bool isNop() const { return staticInst->isNop(); }
440 bool isMemRef() const { return staticInst->isMemRef(); }
441 bool isLoad() const { return staticInst->isLoad(); }
442 bool isStore() const { return staticInst->isStore(); }
443 bool isStoreConditional() const
444 { return staticInst->isStoreConditional(); }
445 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
446 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
447 bool isCopy() const { return staticInst->isCopy(); }
448 bool isInteger() const { return staticInst->isInteger(); }
449 bool isFloating() const { return staticInst->isFloating(); }
450 bool isControl() const { return staticInst->isControl(); }
451 bool isCall() const { return staticInst->isCall(); }
452 bool isReturn() const { return staticInst->isReturn(); }
453 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
454 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
455 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
456 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
457 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
458 bool isThreadSync() const { return staticInst->isThreadSync(); }
459 bool isSerializing() const { return staticInst->isSerializing(); }
460 bool isSerializeBefore() const
461 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
462 bool isSerializeAfter() const
463 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
464 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
465 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
466 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
467 bool isQuiesce() const { return staticInst->isQuiesce(); }
468 bool isIprAccess() const { return staticInst->isIprAccess(); }
469 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
470
471 /** Temporarily sets this instruction as a serialize before instruction. */
472 void setSerializeBefore() { status.set(SerializeBefore); }
473
474 /** Clears the serializeBefore part of this instruction. */
475 void clearSerializeBefore() { status.reset(SerializeBefore); }
476
477 /** Checks if this serializeBefore is only temporarily set. */
478 bool isTempSerializeBefore() { return status[SerializeBefore]; }
479
480 /** Temporarily sets this instruction as a serialize after instruction. */
481 void setSerializeAfter() { status.set(SerializeAfter); }
482
483 /** Clears the serializeAfter part of this instruction.*/
484 void clearSerializeAfter() { status.reset(SerializeAfter); }
485
486 /** Checks if this serializeAfter is only temporarily set. */
487 bool isTempSerializeAfter() { return status[SerializeAfter]; }
488
489 /** Sets the serialization part of this instruction as handled. */
490 void setSerializeHandled() { status.set(SerializeHandled); }
491
492 /** Checks if the serialization part of this instruction has been
493 * handled. This does not apply to the temporary serializing
494 * state; it only applies to this instruction's own permanent
495 * serializing state.
496 */
497 bool isSerializeHandled() { return status[SerializeHandled]; }
498
499 /** Returns the opclass of this instruction. */
500 OpClass opClass() const { return staticInst->opClass(); }
501
502 /** Returns the branch target address. */
503 Addr branchTarget() const { return staticInst->branchTarget(PC); }
504
505 /** Returns the number of source registers. */
506 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
507
508 /** Returns the number of destination registers. */
509 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
510
511 // the following are used to track physical register usage
512 // for machines with separate int & FP reg files
513 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
514 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
515
516 /** Returns the logical register index of the i'th destination register. */
517 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
518
519 /** Returns the logical register index of the i'th source register. */
520 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
521
522 /** Returns the result of an integer instruction. */
523 uint64_t readIntResult() { return instResult.integer; }
524
525 /** Returns the result of a floating point instruction. */
526 float readFloatResult() { return (float)instResult.dbl; }
527
528 /** Returns the result of a floating point (double) instruction. */
529 double readDoubleResult() { return instResult.dbl; }
530
531 /** Records an integer register being set to a value. */
532 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
533 {
534 if (recordResult)
535 instResult.integer = val;
536 }
537
538 /** Records an fp register being set to a value. */
539 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
540 int width)
541 {
542 if (recordResult) {
543 if (width == 32)
544 instResult.dbl = (double)val;
545 else if (width == 64)
546 instResult.dbl = val;
547 else
548 panic("Unsupported width!");
549 }
550 }
551
552 /** Records an fp register being set to a value. */
553 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
554 {
555 if (recordResult)
556 instResult.dbl = (double)val;
557 }
558
559 /** Records an fp register being set to an integer value. */
560 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
561 int width)
562 {
563 if (recordResult)
564 instResult.integer = val;
565 }
566
567 /** Records an fp register being set to an integer value. */
568 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
569 {
570 if (recordResult)
571 instResult.integer = val;
572 }
573
574 /** Records that one of the source registers is ready. */
575 void markSrcRegReady();
576
577 /** Marks a specific register as ready. */
578 void markSrcRegReady(RegIndex src_idx);
579
580 /** Returns if a source register is ready. */
581 bool isReadySrcRegIdx(int idx) const
582 {
583 return this->_readySrcRegIdx[idx];
584 }
585
586 /** Sets this instruction as completed. */
587 void setCompleted() { status.set(Completed); }
588
589 /** Returns whether or not this instruction is completed. */
590 bool isCompleted() const { return status[Completed]; }
591
592 /** Marks the result as ready. */
593 void setResultReady() { status.set(ResultReady); }
594
595 /** Returns whether or not the result is ready. */
596 bool isResultReady() const { return status[ResultReady]; }
597
598 /** Sets this instruction as ready to issue. */
599 void setCanIssue() { status.set(CanIssue); }
600
601 /** Returns whether or not this instruction is ready to issue. */
602 bool readyToIssue() const { return status[CanIssue]; }
603
604 /** Clears this instruction being able to issue. */
605 void clearCanIssue() { status.reset(CanIssue); }
606
607 /** Sets this instruction as issued from the IQ. */
608 void setIssued() { status.set(Issued); }
609
610 /** Returns whether or not this instruction has issued. */
611 bool isIssued() const { return status[Issued]; }
612
613 /** Clears this instruction as being issued. */
614 void clearIssued() { status.reset(Issued); }
615
616 /** Sets this instruction as executed. */
617 void setExecuted() { status.set(Executed); }
618
619 /** Returns whether or not this instruction has executed. */
620 bool isExecuted() const { return status[Executed]; }
621
622 /** Sets this instruction as ready to commit. */
623 void setCanCommit() { status.set(CanCommit); }
624
625 /** Clears this instruction as being ready to commit. */
626 void clearCanCommit() { status.reset(CanCommit); }
627
628 /** Returns whether or not this instruction is ready to commit. */
629 bool readyToCommit() const { return status[CanCommit]; }
630
631 void setAtCommit() { status.set(AtCommit); }
632
633 bool isAtCommit() { return status[AtCommit]; }
634
635 /** Sets this instruction as committed. */
636 void setCommitted() { status.set(Committed); }
637
638 /** Returns whether or not this instruction is committed. */
639 bool isCommitted() const { return status[Committed]; }
640
641 /** Sets this instruction as squashed. */
642 void setSquashed() { status.set(Squashed); }
643
644 /** Returns whether or not this instruction is squashed. */
645 bool isSquashed() const { return status[Squashed]; }
646
647 //Instruction Queue Entry
648 //-----------------------
649 /** Sets this instruction as a entry the IQ. */
650 void setInIQ() { status.set(IqEntry); }
651
652 /** Sets this instruction as a entry the IQ. */
653 void clearInIQ() { status.reset(IqEntry); }
654
655 /** Returns whether or not this instruction has issued. */
656 bool isInIQ() const { return status[IqEntry]; }
657
658 /** Sets this instruction as squashed in the IQ. */
659 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
660
661 /** Returns whether or not this instruction is squashed in the IQ. */
662 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
663
664
665 //Load / Store Queue Functions
666 //-----------------------
667 /** Sets this instruction as a entry the LSQ. */
668 void setInLSQ() { status.set(LsqEntry); }
669
670 /** Sets this instruction as a entry the LSQ. */
671 void removeInLSQ() { status.reset(LsqEntry); }
672
673 /** Returns whether or not this instruction is in the LSQ. */
674 bool isInLSQ() const { return status[LsqEntry]; }
675
676 /** Sets this instruction as squashed in the LSQ. */
677 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
678
679 /** Returns whether or not this instruction is squashed in the LSQ. */
680 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
681
682
683 //Reorder Buffer Functions
684 //-----------------------
685 /** Sets this instruction as a entry the ROB. */
686 void setInROB() { status.set(RobEntry); }
687
688 /** Sets this instruction as a entry the ROB. */
689 void clearInROB() { status.reset(RobEntry); }
690
691 /** Returns whether or not this instruction is in the ROB. */
692 bool isInROB() const { return status[RobEntry]; }
693
694 /** Sets this instruction as squashed in the ROB. */
695 void setSquashedInROB() { status.set(SquashedInROB); }
696
697 /** Returns whether or not this instruction is squashed in the ROB. */
698 bool isSquashedInROB() const { return status[SquashedInROB]; }
699
700 /** Read the PC of this instruction. */
701 const Addr readPC() const { return PC; }
702
703 /** Set the next PC of this instruction (its actual target). */
704 void setNextPC(uint64_t val)
705 {
706 nextPC = val;
707 }
708
709 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
710 void setNextNPC(uint64_t val)
711 {
|
713 }
714
715 /** Sets the ASID. */
716 void setASID(short addr_space_id) { asid = addr_space_id; }
717
718 /** Sets the thread id. */
719 void setTid(unsigned tid) { threadNumber = tid; }
720
721 /** Sets the pointer to the thread state. */
722 void setThreadState(ImplState *state) { thread = state; }
723
724 /** Returns the thread context. */
725 ThreadContext *tcBase() { return thread->getTC(); }
726
727 private:
728 /** Instruction effective address.
729 * @todo: Consider if this is necessary or not.
730 */
731 Addr instEffAddr;
732
733 /** Whether or not the effective address calculation is completed.
734 * @todo: Consider if this is necessary or not.
735 */
736 bool eaCalcDone;
737
738 /** Is this instruction's memory access uncacheable. */
739 bool isUncacheable;
740
741 /** Has this instruction generated a memory request. */
742 bool reqMade;
743
744 public:
745 /** Sets the effective address. */
746 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
747
748 /** Returns the effective address. */
749 const Addr &getEA() const { return instEffAddr; }
750
751 /** Returns whether or not the eff. addr. calculation has been completed. */
752 bool doneEACalc() { return eaCalcDone; }
753
754 /** Returns whether or not the eff. addr. source registers are ready. */
755 bool eaSrcsReady();
756
757 /** Whether or not the memory operation is done. */
758 bool memOpDone;
759
760 /** Is this instruction's memory access uncacheable. */
761 bool uncacheable() { return isUncacheable; }
762
763 /** Has this instruction generated a memory request. */
764 bool hasRequest() { return reqMade; }
765
766 public:
767 /** Load queue index. */
768 int16_t lqIdx;
769
770 /** Store queue index. */
771 int16_t sqIdx;
772
773 /** Iterator pointing to this BaseDynInst in the list of all insts. */
774 ListIt instListIt;
775
776 /** Returns iterator to this instruction in the list of all insts. */
777 ListIt &getInstListIt() { return instListIt; }
778
779 /** Sets iterator for this instruction in the list of all insts. */
780 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
781
782 public:
783 /** Returns the number of consecutive store conditional failures. */
784 unsigned readStCondFailures()
785 { return thread->storeCondFailures; }
786
787 /** Sets the number of consecutive store conditional failures. */
788 void setStCondFailures(unsigned sc_failures)
789 { thread->storeCondFailures = sc_failures; }
790};
791
792template<class Impl>
793template<class T>
794inline Fault
795BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
796{
797 reqMade = true;
798 Request *req = new Request();
799 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
800 req->setThreadContext(thread->readCpuId(), threadNumber);
801
802 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
803 TheISA::VMPageSize) {
804 delete req;
805 return TheISA::genAlignmentFault();
806 }
807
808 fault = cpu->translateDataReadReq(req, thread);
809
810 if (req->isUncacheable())
811 isUncacheable = true;
812
813 if (fault == NoFault) {
814 effAddr = req->getVaddr();
815 effAddrValid = true;
816 physEffAddr = req->getPaddr();
817 memReqFlags = req->getFlags();
818
819#if 0
820 if (cpu->system->memctrl->badaddr(physEffAddr)) {
821 fault = TheISA::genMachineCheckFault();
822 data = (T)-1;
823 this->setExecuted();
824 } else {
825 fault = cpu->read(req, data, lqIdx);
826 }
827#else
828 fault = cpu->read(req, data, lqIdx);
829#endif
830 } else {
831 // Return a fixed value to keep simulation deterministic even
832 // along misspeculated paths.
833 data = (T)-1;
834
835 // Commit will have to clean up whatever happened. Set this
836 // instruction as executed.
837 this->setExecuted();
838 delete req;
839 }
840
841 if (traceData) {
842 traceData->setAddr(addr);
843 traceData->setData(data);
844 }
845
846 return fault;
847}
848
849template<class Impl>
850template<class T>
851inline Fault
852BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
853{
854 if (traceData) {
855 traceData->setAddr(addr);
856 traceData->setData(data);
857 }
858
859 reqMade = true;
860 Request *req = new Request();
861 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
862 req->setThreadContext(thread->readCpuId(), threadNumber);
863
864 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
865 TheISA::VMPageSize) {
866 delete req;
867 return TheISA::genAlignmentFault();
868 }
869
870 fault = cpu->translateDataWriteReq(req, thread);
871
872 if (req->isUncacheable())
873 isUncacheable = true;
874
875 if (fault == NoFault) {
876 effAddr = req->getVaddr();
877 effAddrValid = true;
878 physEffAddr = req->getPaddr();
879 memReqFlags = req->getFlags();
880
881 if (req->isCondSwap()) {
882 assert(res);
883 req->setExtraData(*res);
884 }
885#if 0
886 if (cpu->system->memctrl->badaddr(physEffAddr)) {
887 fault = TheISA::genMachineCheckFault();
888 } else {
889 fault = cpu->write(req, data, sqIdx);
890 }
891#else
892 fault = cpu->write(req, data, sqIdx);
893#endif
894 } else {
895 delete req;
896 }
897
898 return fault;
899}
900
901#endif // __CPU_BASE_DYN_INST_HH__
| 715 }
716
717 /** Sets the ASID. */
718 void setASID(short addr_space_id) { asid = addr_space_id; }
719
720 /** Sets the thread id. */
721 void setTid(unsigned tid) { threadNumber = tid; }
722
723 /** Sets the pointer to the thread state. */
724 void setThreadState(ImplState *state) { thread = state; }
725
726 /** Returns the thread context. */
727 ThreadContext *tcBase() { return thread->getTC(); }
728
729 private:
730 /** Instruction effective address.
731 * @todo: Consider if this is necessary or not.
732 */
733 Addr instEffAddr;
734
735 /** Whether or not the effective address calculation is completed.
736 * @todo: Consider if this is necessary or not.
737 */
738 bool eaCalcDone;
739
740 /** Is this instruction's memory access uncacheable. */
741 bool isUncacheable;
742
743 /** Has this instruction generated a memory request. */
744 bool reqMade;
745
746 public:
747 /** Sets the effective address. */
748 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
749
750 /** Returns the effective address. */
751 const Addr &getEA() const { return instEffAddr; }
752
753 /** Returns whether or not the eff. addr. calculation has been completed. */
754 bool doneEACalc() { return eaCalcDone; }
755
756 /** Returns whether or not the eff. addr. source registers are ready. */
757 bool eaSrcsReady();
758
759 /** Whether or not the memory operation is done. */
760 bool memOpDone;
761
762 /** Is this instruction's memory access uncacheable. */
763 bool uncacheable() { return isUncacheable; }
764
765 /** Has this instruction generated a memory request. */
766 bool hasRequest() { return reqMade; }
767
768 public:
769 /** Load queue index. */
770 int16_t lqIdx;
771
772 /** Store queue index. */
773 int16_t sqIdx;
774
775 /** Iterator pointing to this BaseDynInst in the list of all insts. */
776 ListIt instListIt;
777
778 /** Returns iterator to this instruction in the list of all insts. */
779 ListIt &getInstListIt() { return instListIt; }
780
781 /** Sets iterator for this instruction in the list of all insts. */
782 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
783
784 public:
785 /** Returns the number of consecutive store conditional failures. */
786 unsigned readStCondFailures()
787 { return thread->storeCondFailures; }
788
789 /** Sets the number of consecutive store conditional failures. */
790 void setStCondFailures(unsigned sc_failures)
791 { thread->storeCondFailures = sc_failures; }
792};
793
794template<class Impl>
795template<class T>
796inline Fault
797BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
798{
799 reqMade = true;
800 Request *req = new Request();
801 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
802 req->setThreadContext(thread->readCpuId(), threadNumber);
803
804 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
805 TheISA::VMPageSize) {
806 delete req;
807 return TheISA::genAlignmentFault();
808 }
809
810 fault = cpu->translateDataReadReq(req, thread);
811
812 if (req->isUncacheable())
813 isUncacheable = true;
814
815 if (fault == NoFault) {
816 effAddr = req->getVaddr();
817 effAddrValid = true;
818 physEffAddr = req->getPaddr();
819 memReqFlags = req->getFlags();
820
821#if 0
822 if (cpu->system->memctrl->badaddr(physEffAddr)) {
823 fault = TheISA::genMachineCheckFault();
824 data = (T)-1;
825 this->setExecuted();
826 } else {
827 fault = cpu->read(req, data, lqIdx);
828 }
829#else
830 fault = cpu->read(req, data, lqIdx);
831#endif
832 } else {
833 // Return a fixed value to keep simulation deterministic even
834 // along misspeculated paths.
835 data = (T)-1;
836
837 // Commit will have to clean up whatever happened. Set this
838 // instruction as executed.
839 this->setExecuted();
840 delete req;
841 }
842
843 if (traceData) {
844 traceData->setAddr(addr);
845 traceData->setData(data);
846 }
847
848 return fault;
849}
850
851template<class Impl>
852template<class T>
853inline Fault
854BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
855{
856 if (traceData) {
857 traceData->setAddr(addr);
858 traceData->setData(data);
859 }
860
861 reqMade = true;
862 Request *req = new Request();
863 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
864 req->setThreadContext(thread->readCpuId(), threadNumber);
865
866 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
867 TheISA::VMPageSize) {
868 delete req;
869 return TheISA::genAlignmentFault();
870 }
871
872 fault = cpu->translateDataWriteReq(req, thread);
873
874 if (req->isUncacheable())
875 isUncacheable = true;
876
877 if (fault == NoFault) {
878 effAddr = req->getVaddr();
879 effAddrValid = true;
880 physEffAddr = req->getPaddr();
881 memReqFlags = req->getFlags();
882
883 if (req->isCondSwap()) {
884 assert(res);
885 req->setExtraData(*res);
886 }
887#if 0
888 if (cpu->system->memctrl->badaddr(physEffAddr)) {
889 fault = TheISA::genMachineCheckFault();
890 } else {
891 fault = cpu->write(req, data, sqIdx);
892 }
893#else
894 fault = cpu->write(req, data, sqIdx);
895#endif
896 } else {
897 delete req;
898 }
899
900 return fault;
901}
902
903#endif // __CPU_BASE_DYN_INST_HH__
|