1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
|
| 34#include <bitset>
|
34#include <list>
35#include <string>
36
37#include "arch/faults.hh"
38#include "base/fast_alloc.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/inst_seq.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst.hh"
45#include "mem/packet.hh"
46#include "sim/system.hh"
47
48/**
49 * @file
50 * Defines a dynamic instruction context.
51 */
52
53// Forward declaration.
54class StaticInstPtr;
55
56template <class Impl>
57class BaseDynInst : public FastAlloc, public RefCounted
58{
59 public:
60 // Typedef for the CPU.
61 typedef typename Impl::FullCPU FullCPU;
62 typedef typename FullCPU::ImplState ImplState;
63
64 // Binary machine instruction type.
65 typedef TheISA::MachInst MachInst;
66 // Extended machine instruction type
67 typedef TheISA::ExtMachInst ExtMachInst;
68 // Logical register index type.
69 typedef TheISA::RegIndex RegIndex;
70 // Integer register type.
71 typedef TheISA::IntReg IntReg;
72 // Floating point register type.
73 typedef TheISA::FloatReg FloatReg;
74
75 // The DynInstPtr type.
76 typedef typename Impl::DynInstPtr DynInstPtr;
77
78 // The list of instructions iterator type.
79 typedef typename std::list<DynInstPtr>::iterator ListIt;
80
81 enum {
82 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
83 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
84 };
85
86 /** The StaticInst used by this BaseDynInst. */
87 StaticInstPtr staticInst;
88
89 ////////////////////////////////////////////
90 //
91 // INSTRUCTION EXECUTION
92 //
93 ////////////////////////////////////////////
94 /** InstRecord that tracks this instructions. */
95 Trace::InstRecord *traceData;
96
97 /**
98 * Does a read to a given address.
99 * @param addr The address to read.
100 * @param data The read's data is written into this parameter.
101 * @param flags The request's flags.
102 * @return Returns any fault due to the read.
103 */
104 template <class T>
105 Fault read(Addr addr, T &data, unsigned flags);
106
107 /**
108 * Does a write to a given address.
109 * @param data The data to be written.
110 * @param addr The address to write to.
111 * @param flags The request's flags.
112 * @param res The result of the write (for load locked/store conditionals).
113 * @return Returns any fault due to the write.
114 */
115 template <class T>
116 Fault write(T data, Addr addr, unsigned flags,
117 uint64_t *res);
118
119 void prefetch(Addr addr, unsigned flags);
120 void writeHint(Addr addr, int size, unsigned flags);
121 Fault copySrcTranslate(Addr src);
122 Fault copy(Addr dest);
123
124 /** @todo: Consider making this private. */
125 public:
126 /** The sequence number of the instruction. */
127 InstSeqNum seqNum;
128
| 35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/inst_seq.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst.hh"
46#include "mem/packet.hh"
47#include "sim/system.hh"
48
49/**
50 * @file
51 * Defines a dynamic instruction context.
52 */
53
54// Forward declaration.
55class StaticInstPtr;
56
57template <class Impl>
58class BaseDynInst : public FastAlloc, public RefCounted
59{
60 public:
61 // Typedef for the CPU.
62 typedef typename Impl::FullCPU FullCPU;
63 typedef typename FullCPU::ImplState ImplState;
64
65 // Binary machine instruction type.
66 typedef TheISA::MachInst MachInst;
67 // Extended machine instruction type
68 typedef TheISA::ExtMachInst ExtMachInst;
69 // Logical register index type.
70 typedef TheISA::RegIndex RegIndex;
71 // Integer register type.
72 typedef TheISA::IntReg IntReg;
73 // Floating point register type.
74 typedef TheISA::FloatReg FloatReg;
75
76 // The DynInstPtr type.
77 typedef typename Impl::DynInstPtr DynInstPtr;
78
79 // The list of instructions iterator type.
80 typedef typename std::list<DynInstPtr>::iterator ListIt;
81
82 enum {
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
85 };
86
87 /** The StaticInst used by this BaseDynInst. */
88 StaticInstPtr staticInst;
89
90 ////////////////////////////////////////////
91 //
92 // INSTRUCTION EXECUTION
93 //
94 ////////////////////////////////////////////
95 /** InstRecord that tracks this instructions. */
96 Trace::InstRecord *traceData;
97
98 /**
99 * Does a read to a given address.
100 * @param addr The address to read.
101 * @param data The read's data is written into this parameter.
102 * @param flags The request's flags.
103 * @return Returns any fault due to the read.
104 */
105 template <class T>
106 Fault read(Addr addr, T &data, unsigned flags);
107
108 /**
109 * Does a write to a given address.
110 * @param data The data to be written.
111 * @param addr The address to write to.
112 * @param flags The request's flags.
113 * @param res The result of the write (for load locked/store conditionals).
114 * @return Returns any fault due to the write.
115 */
116 template <class T>
117 Fault write(T data, Addr addr, unsigned flags,
118 uint64_t *res);
119
120 void prefetch(Addr addr, unsigned flags);
121 void writeHint(Addr addr, int size, unsigned flags);
122 Fault copySrcTranslate(Addr src);
123 Fault copy(Addr dest);
124
125 /** @todo: Consider making this private. */
126 public:
127 /** The sequence number of the instruction. */
128 InstSeqNum seqNum;
129
|
129 /** Is the instruction in the IQ */
130 bool iqEntry;
| 130 enum Status {
131 IqEntry, /// Instruction is in the IQ
132 RobEntry, /// Instruction is in the ROB
133 LsqEntry, /// Instruction is in the LSQ
134 Completed, /// Instruction has completed
135 ResultReady, /// Instruction has its result
136 CanIssue, /// Instruction can issue and execute
137 Issued, /// Instruction has issued
138 Executed, /// Instruction has executed
139 CanCommit, /// Instruction can commit
140 AtCommit, /// Instruction has reached commit
141 Committed, /// Instruction has committed
142 Squashed, /// Instruction is squashed
143 SquashedInIQ, /// Instruction is squashed in the IQ
144 SquashedInLSQ, /// Instruction is squashed in the LSQ
145 SquashedInROB, /// Instruction is squashed in the ROB
146 RecoverInst, /// Is a recover instruction
147 BlockingInst, /// Is a blocking instruction
148 ThreadsyncWait, /// Is a thread synchronization instruction
149 SerializeBefore, /// Needs to serialize on
150 /// instructions ahead of it
151 SerializeAfter, /// Needs to serialize instructions behind it
152 SerializeHandled, /// Serialization has been handled
153 NumStatus
154 };
|
131
| 155
|
132 /** Is the instruction in the ROB */
133 bool robEntry;
| 156 /** The status of this BaseDynInst. Several bits can be set. */
157 std::bitset<NumStatus> status;
|
134
| 158
|
135 /** Is the instruction in the LSQ */
136 bool lsqEntry;
137
138 /** Is the instruction completed. */
139 bool completed;
140
141 /** Is the instruction's result ready. */
142 bool resultReady;
143
144 /** Can this instruction issue. */
145 bool canIssue;
146
147 /** Has this instruction issued. */
148 bool issued;
149
150 /** Has this instruction executed (or made it through execute) yet. */
151 bool executed;
152
153 /** Can this instruction commit. */
154 bool canCommit;
155
156 /** Is this instruction committed. */
157 bool committed;
158
159 /** Is this instruction squashed. */
160 bool squashed;
161
162 /** Is this instruction squashed in the instruction queue. */
163 bool squashedInIQ;
164
165 /** Is this instruction squashed in the instruction queue. */
166 bool squashedInLSQ;
167
168 /** Is this instruction squashed in the instruction queue. */
169 bool squashedInROB;
170
171 /** Is this a recover instruction. */
172 bool recoverInst;
173
174 /** Is this a thread blocking instruction. */
175 bool blockingInst; /* this inst has called thread_block() */
176
177 /** Is this a thread syncrhonization instruction. */
178 bool threadsyncWait;
179
| |
180 /** The thread this instruction is from. */
181 short threadNumber;
182
183 /** data address space ID, for loads & stores. */
184 short asid;
185
186 /** How many source registers are ready. */
187 unsigned readyRegs;
188
189 /** Pointer to the FullCPU object. */
190 FullCPU *cpu;
191
192 /** Pointer to the thread state. */
193 ImplState *thread;
194
195 /** The kind of fault this instruction has generated. */
196 Fault fault;
197
198 /** The memory request. */
199 Request *req;
200
201 /** Pointer to the data for the memory access. */
202 uint8_t *memData;
203
204 /** The effective virtual address (lds & stores only). */
205 Addr effAddr;
206
207 /** The effective physical address. */
208 Addr physEffAddr;
209
210 /** Effective virtual address for a copy source. */
211 Addr copySrcEffAddr;
212
213 /** Effective physical address for a copy source. */
214 Addr copySrcPhysEffAddr;
215
216 /** The memory request flags (from translation). */
217 unsigned memReqFlags;
218
| 159 /** The thread this instruction is from. */
160 short threadNumber;
161
162 /** data address space ID, for loads & stores. */
163 short asid;
164
165 /** How many source registers are ready. */
166 unsigned readyRegs;
167
168 /** Pointer to the FullCPU object. */
169 FullCPU *cpu;
170
171 /** Pointer to the thread state. */
172 ImplState *thread;
173
174 /** The kind of fault this instruction has generated. */
175 Fault fault;
176
177 /** The memory request. */
178 Request *req;
179
180 /** Pointer to the data for the memory access. */
181 uint8_t *memData;
182
183 /** The effective virtual address (lds & stores only). */
184 Addr effAddr;
185
186 /** The effective physical address. */
187 Addr physEffAddr;
188
189 /** Effective virtual address for a copy source. */
190 Addr copySrcEffAddr;
191
192 /** Effective physical address for a copy source. */
193 Addr copySrcPhysEffAddr;
194
195 /** The memory request flags (from translation). */
196 unsigned memReqFlags;
197
|
219 /** The size of the data to be stored. */
220 int storeSize;
221
222 /** The data to be stored. */
223 IntReg storeData;
224
| |
225 union Result {
226 uint64_t integer;
227 float fp;
228 double dbl;
229 };
230
231 /** The result of the instruction; assumes for now that there's only one
232 * destination register.
233 */
234 Result instResult;
235
236 /** PC of this instruction. */
237 Addr PC;
238
239 /** Next non-speculative PC. It is not filled in at fetch, but rather
240 * once the target of the branch is truly known (either decode or
241 * execute).
242 */
243 Addr nextPC;
244
245 /** Predicted next PC. */
246 Addr predPC;
247
248 /** Count of total number of dynamic instructions. */
249 static int instcount;
250
251#ifdef DEBUG
252 void dumpSNList();
253#endif
254
255 /** Whether or not the source register is ready.
256 * @todo: Not sure this should be here vs the derived class.
257 */
258 bool _readySrcRegIdx[MaxInstSrcRegs];
259
260 public:
261 /** BaseDynInst constructor given a binary instruction.
262 * @param inst The binary instruction.
263 * @param PC The PC of the instruction.
264 * @param pred_PC The predicted next PC.
265 * @param seq_num The sequence number of the instruction.
266 * @param cpu Pointer to the instruction's CPU.
267 */
268 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
269 FullCPU *cpu);
270
271 /** BaseDynInst constructor given a StaticInst pointer.
272 * @param _staticInst The StaticInst for this BaseDynInst.
273 */
274 BaseDynInst(StaticInstPtr &_staticInst);
275
276 /** BaseDynInst destructor. */
277 ~BaseDynInst();
278
279 private:
280 /** Function to initialize variables in the constructors. */
281 void initVars();
282
283 public:
284 /** Dumps out contents of this BaseDynInst. */
285 void dump();
286
287 /** Dumps out contents of this BaseDynInst into given string. */
288 void dump(std::string &outstring);
289
290 /** Returns the fault type. */
291 Fault getFault() { return fault; }
292
293 /** Checks whether or not this instruction has had its branch target
294 * calculated yet. For now it is not utilized and is hacked to be
295 * always false.
296 * @todo: Actually use this instruction.
297 */
298 bool doneTargCalc() { return false; }
299
300 /** Returns the next PC. This could be the speculative next PC if it is
301 * called prior to the actual branch target being calculated.
302 */
303 Addr readNextPC() { return nextPC; }
304
305 /** Set the predicted target of this current instruction. */
306 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
307
308 /** Returns the predicted target of the branch. */
309 Addr readPredTarg() { return predPC; }
310
311 /** Returns whether the instruction was predicted taken or not. */
312 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
313
314 /** Returns whether the instruction mispredicted. */
315 bool mispredicted() { return predPC != nextPC; }
316
317 //
318 // Instruction types. Forward checks to StaticInst object.
319 //
320 bool isNop() const { return staticInst->isNop(); }
321 bool isMemRef() const { return staticInst->isMemRef(); }
322 bool isLoad() const { return staticInst->isLoad(); }
323 bool isStore() const { return staticInst->isStore(); }
324 bool isStoreConditional() const
325 { return staticInst->isStoreConditional(); }
326 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
327 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
328 bool isCopy() const { return staticInst->isCopy(); }
329 bool isInteger() const { return staticInst->isInteger(); }
330 bool isFloating() const { return staticInst->isFloating(); }
331 bool isControl() const { return staticInst->isControl(); }
332 bool isCall() const { return staticInst->isCall(); }
333 bool isReturn() const { return staticInst->isReturn(); }
334 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
335 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
336 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
337 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
338 bool isThreadSync() const { return staticInst->isThreadSync(); }
339 bool isSerializing() const { return staticInst->isSerializing(); }
340 bool isSerializeBefore() const
| 198 union Result {
199 uint64_t integer;
200 float fp;
201 double dbl;
202 };
203
204 /** The result of the instruction; assumes for now that there's only one
205 * destination register.
206 */
207 Result instResult;
208
209 /** PC of this instruction. */
210 Addr PC;
211
212 /** Next non-speculative PC. It is not filled in at fetch, but rather
213 * once the target of the branch is truly known (either decode or
214 * execute).
215 */
216 Addr nextPC;
217
218 /** Predicted next PC. */
219 Addr predPC;
220
221 /** Count of total number of dynamic instructions. */
222 static int instcount;
223
224#ifdef DEBUG
225 void dumpSNList();
226#endif
227
228 /** Whether or not the source register is ready.
229 * @todo: Not sure this should be here vs the derived class.
230 */
231 bool _readySrcRegIdx[MaxInstSrcRegs];
232
233 public:
234 /** BaseDynInst constructor given a binary instruction.
235 * @param inst The binary instruction.
236 * @param PC The PC of the instruction.
237 * @param pred_PC The predicted next PC.
238 * @param seq_num The sequence number of the instruction.
239 * @param cpu Pointer to the instruction's CPU.
240 */
241 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
242 FullCPU *cpu);
243
244 /** BaseDynInst constructor given a StaticInst pointer.
245 * @param _staticInst The StaticInst for this BaseDynInst.
246 */
247 BaseDynInst(StaticInstPtr &_staticInst);
248
249 /** BaseDynInst destructor. */
250 ~BaseDynInst();
251
252 private:
253 /** Function to initialize variables in the constructors. */
254 void initVars();
255
256 public:
257 /** Dumps out contents of this BaseDynInst. */
258 void dump();
259
260 /** Dumps out contents of this BaseDynInst into given string. */
261 void dump(std::string &outstring);
262
263 /** Returns the fault type. */
264 Fault getFault() { return fault; }
265
266 /** Checks whether or not this instruction has had its branch target
267 * calculated yet. For now it is not utilized and is hacked to be
268 * always false.
269 * @todo: Actually use this instruction.
270 */
271 bool doneTargCalc() { return false; }
272
273 /** Returns the next PC. This could be the speculative next PC if it is
274 * called prior to the actual branch target being calculated.
275 */
276 Addr readNextPC() { return nextPC; }
277
278 /** Set the predicted target of this current instruction. */
279 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
280
281 /** Returns the predicted target of the branch. */
282 Addr readPredTarg() { return predPC; }
283
284 /** Returns whether the instruction was predicted taken or not. */
285 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
286
287 /** Returns whether the instruction mispredicted. */
288 bool mispredicted() { return predPC != nextPC; }
289
290 //
291 // Instruction types. Forward checks to StaticInst object.
292 //
293 bool isNop() const { return staticInst->isNop(); }
294 bool isMemRef() const { return staticInst->isMemRef(); }
295 bool isLoad() const { return staticInst->isLoad(); }
296 bool isStore() const { return staticInst->isStore(); }
297 bool isStoreConditional() const
298 { return staticInst->isStoreConditional(); }
299 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
300 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
301 bool isCopy() const { return staticInst->isCopy(); }
302 bool isInteger() const { return staticInst->isInteger(); }
303 bool isFloating() const { return staticInst->isFloating(); }
304 bool isControl() const { return staticInst->isControl(); }
305 bool isCall() const { return staticInst->isCall(); }
306 bool isReturn() const { return staticInst->isReturn(); }
307 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
308 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
309 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
310 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
311 bool isThreadSync() const { return staticInst->isThreadSync(); }
312 bool isSerializing() const { return staticInst->isSerializing(); }
313 bool isSerializeBefore() const
|
341 { return staticInst->isSerializeBefore() || serializeBefore; }
| 314 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
|
342 bool isSerializeAfter() const
| 315 bool isSerializeAfter() const
|
343 { return staticInst->isSerializeAfter() || serializeAfter; }
| 316 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
|
344 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
345 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
346 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
347 bool isQuiesce() const { return staticInst->isQuiesce(); }
348 bool isIprAccess() const { return staticInst->isIprAccess(); }
349 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
350
351 /** Temporarily sets this instruction as a serialize before instruction. */
| 317 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
318 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
319 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
320 bool isQuiesce() const { return staticInst->isQuiesce(); }
321 bool isIprAccess() const { return staticInst->isIprAccess(); }
322 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
323
324 /** Temporarily sets this instruction as a serialize before instruction. */
|
352 void setSerializeBefore() { serializeBefore = true; }
| 325 void setSerializeBefore() { status.set(SerializeBefore); }
|
353
354 /** Clears the serializeBefore part of this instruction. */
| 326
327 /** Clears the serializeBefore part of this instruction. */
|
355 void clearSerializeBefore() { serializeBefore = false; }
| 328 void clearSerializeBefore() { status.reset(SerializeBefore); }
|
356
357 /** Checks if this serializeBefore is only temporarily set. */
| 329
330 /** Checks if this serializeBefore is only temporarily set. */
|
358 bool isTempSerializeBefore() { return serializeBefore; }
| 331 bool isTempSerializeBefore() { return status[SerializeBefore]; }
|
359
| 332
|
360 /** Tracks if instruction has been externally set as serializeBefore. */
361 bool serializeBefore;
362
| |
363 /** Temporarily sets this instruction as a serialize after instruction. */
| 333 /** Temporarily sets this instruction as a serialize after instruction. */
|
364 void setSerializeAfter() { serializeAfter = true; }
| 334 void setSerializeAfter() { status.set(SerializeAfter); }
|
365
366 /** Clears the serializeAfter part of this instruction.*/
| 335
336 /** Clears the serializeAfter part of this instruction.*/
|
367 void clearSerializeAfter() { serializeAfter = false; }
| 337 void clearSerializeAfter() { status.reset(SerializeAfter); }
|
368
369 /** Checks if this serializeAfter is only temporarily set. */
| 338
339 /** Checks if this serializeAfter is only temporarily set. */
|
370 bool isTempSerializeAfter() { return serializeAfter; }
| 340 bool isTempSerializeAfter() { return status[SerializeAfter]; }
|
371
| 341
|
372 /** Tracks if instruction has been externally set as serializeAfter. */
373 bool serializeAfter;
| 342 /** Sets the serialization part of this instruction as handled. */
343 void setSerializeHandled() { status.set(SerializeHandled); }
|
374
375 /** Checks if the serialization part of this instruction has been
376 * handled. This does not apply to the temporary serializing
377 * state; it only applies to this instruction's own permanent
378 * serializing state.
379 */
| 344
345 /** Checks if the serialization part of this instruction has been
346 * handled. This does not apply to the temporary serializing
347 * state; it only applies to this instruction's own permanent
348 * serializing state.
349 */
|
380 bool isSerializeHandled() { return serializeHandled; }
| 350 bool isSerializeHandled() { return status[SerializeHandled]; }
|
381
| 351
|
382 /** Sets the serialization part of this instruction as handled. */
383 void setSerializeHandled() { serializeHandled = true; }
384
385 /** Whether or not the serialization of this instruction has been handled. */
386 bool serializeHandled;
387
| |
388 /** Returns the opclass of this instruction. */
389 OpClass opClass() const { return staticInst->opClass(); }
390
391 /** Returns the branch target address. */
392 Addr branchTarget() const { return staticInst->branchTarget(PC); }
393
394 /** Returns the number of source registers. */
395 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
396
397 /** Returns the number of destination registers. */
398 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
399
400 // the following are used to track physical register usage
401 // for machines with separate int & FP reg files
402 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
403 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
404
405 /** Returns the logical register index of the i'th destination register. */
406 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
407
408 /** Returns the logical register index of the i'th source register. */
409 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
410
411 /** Returns the result of an integer instruction. */
412 uint64_t readIntResult() { return instResult.integer; }
413
414 /** Returns the result of a floating point instruction. */
415 float readFloatResult() { return instResult.fp; }
416
417 /** Returns the result of a floating point (double) instruction. */
418 double readDoubleResult() { return instResult.dbl; }
419
420 /** Records an integer register being set to a value. */
421 void setIntReg(const StaticInst *si, int idx, uint64_t val)
422 {
423 instResult.integer = val;
424 }
425
426 /** Records an fp register being set to a value. */
427 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
428 {
429 if (width == 32)
430 instResult.fp = val;
431 else if (width == 64)
432 instResult.dbl = val;
433 else
434 panic("Unsupported width!");
435 }
436
437 /** Records an fp register being set to a value. */
438 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
439 {
440 instResult.fp = val;
441 }
442
443 /** Records an fp register being set to an integer value. */
444 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
445 {
446 instResult.integer = val;
447 }
448
449 /** Records an fp register being set to an integer value. */
450 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
451 {
452 instResult.integer = val;
453 }
454
455 /** Records that one of the source registers is ready. */
456 void markSrcRegReady();
457
458 /** Marks a specific register as ready. */
459 void markSrcRegReady(RegIndex src_idx);
460
461 /** Returns if a source register is ready. */
462 bool isReadySrcRegIdx(int idx) const
463 {
464 return this->_readySrcRegIdx[idx];
465 }
466
467 /** Sets this instruction as completed. */
| 352 /** Returns the opclass of this instruction. */
353 OpClass opClass() const { return staticInst->opClass(); }
354
355 /** Returns the branch target address. */
356 Addr branchTarget() const { return staticInst->branchTarget(PC); }
357
358 /** Returns the number of source registers. */
359 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
360
361 /** Returns the number of destination registers. */
362 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
363
364 // the following are used to track physical register usage
365 // for machines with separate int & FP reg files
366 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
367 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
368
369 /** Returns the logical register index of the i'th destination register. */
370 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
371
372 /** Returns the logical register index of the i'th source register. */
373 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
374
375 /** Returns the result of an integer instruction. */
376 uint64_t readIntResult() { return instResult.integer; }
377
378 /** Returns the result of a floating point instruction. */
379 float readFloatResult() { return instResult.fp; }
380
381 /** Returns the result of a floating point (double) instruction. */
382 double readDoubleResult() { return instResult.dbl; }
383
384 /** Records an integer register being set to a value. */
385 void setIntReg(const StaticInst *si, int idx, uint64_t val)
386 {
387 instResult.integer = val;
388 }
389
390 /** Records an fp register being set to a value. */
391 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
392 {
393 if (width == 32)
394 instResult.fp = val;
395 else if (width == 64)
396 instResult.dbl = val;
397 else
398 panic("Unsupported width!");
399 }
400
401 /** Records an fp register being set to a value. */
402 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
403 {
404 instResult.fp = val;
405 }
406
407 /** Records an fp register being set to an integer value. */
408 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
409 {
410 instResult.integer = val;
411 }
412
413 /** Records an fp register being set to an integer value. */
414 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
415 {
416 instResult.integer = val;
417 }
418
419 /** Records that one of the source registers is ready. */
420 void markSrcRegReady();
421
422 /** Marks a specific register as ready. */
423 void markSrcRegReady(RegIndex src_idx);
424
425 /** Returns if a source register is ready. */
426 bool isReadySrcRegIdx(int idx) const
427 {
428 return this->_readySrcRegIdx[idx];
429 }
430
431 /** Sets this instruction as completed. */
|
468 void setCompleted() { completed = true; }
| 432 void setCompleted() { status.set(Completed); }
|
469
470 /** Returns whether or not this instruction is completed. */
| 433
434 /** Returns whether or not this instruction is completed. */
|
471 bool isCompleted() const { return completed; }
| 435 bool isCompleted() const { return status[Completed]; }
|
472
| 436
|
473 void setResultReady() { resultReady = true; }
| 437 /** Marks the result as ready. */
438 void setResultReady() { status.set(ResultReady); }
|
474
| 439
|
475 bool isResultReady() const { return resultReady; }
| 440 /** Returns whether or not the result is ready. */
441 bool isResultReady() const { return status[ResultReady]; }
|
476
477 /** Sets this instruction as ready to issue. */
| 442
443 /** Sets this instruction as ready to issue. */
|
478 void setCanIssue() { canIssue = true; }
| 444 void setCanIssue() { status.set(CanIssue); }
|
479
480 /** Returns whether or not this instruction is ready to issue. */
| 445
446 /** Returns whether or not this instruction is ready to issue. */
|
481 bool readyToIssue() const { return canIssue; }
| 447 bool readyToIssue() const { return status[CanIssue]; }
|
482
483 /** Sets this instruction as issued from the IQ. */
| 448
449 /** Sets this instruction as issued from the IQ. */
|
484 void setIssued() { issued = true; }
| 450 void setIssued() { status.set(Issued); }
|
485
486 /** Returns whether or not this instruction has issued. */
| 451
452 /** Returns whether or not this instruction has issued. */
|
487 bool isIssued() const { return issued; }
| 453 bool isIssued() const { return status[Issued]; }
|
488
489 /** Sets this instruction as executed. */
| 454
455 /** Sets this instruction as executed. */
|
490 void setExecuted() { executed = true; }
| 456 void setExecuted() { status.set(Executed); }
|
491
492 /** Returns whether or not this instruction has executed. */
| 457
458 /** Returns whether or not this instruction has executed. */
|
493 bool isExecuted() const { return executed; }
| 459 bool isExecuted() const { return status[Executed]; }
|
494
495 /** Sets this instruction as ready to commit. */
| 460
461 /** Sets this instruction as ready to commit. */
|
496 void setCanCommit() { canCommit = true; }
| 462 void setCanCommit() { status.set(CanCommit); }
|
497
498 /** Clears this instruction as being ready to commit. */
| 463
464 /** Clears this instruction as being ready to commit. */
|
499 void clearCanCommit() { canCommit = false; }
| 465 void clearCanCommit() { status.reset(CanCommit); }
|
500
501 /** Returns whether or not this instruction is ready to commit. */
| 466
467 /** Returns whether or not this instruction is ready to commit. */
|
502 bool readyToCommit() const { return canCommit; }
| 468 bool readyToCommit() const { return status[CanCommit]; }
|
503
| 469
|
| 470 void setAtCommit() { status.set(AtCommit); }
471
472 bool isAtCommit() { return status[AtCommit]; }
473
|
504 /** Sets this instruction as committed. */
| 474 /** Sets this instruction as committed. */
|
505 void setCommitted() { committed = true; }
| 475 void setCommitted() { status.set(Committed); }
|
506
507 /** Returns whether or not this instruction is committed. */
| 476
477 /** Returns whether or not this instruction is committed. */
|
508 bool isCommitted() const { return committed; }
| 478 bool isCommitted() const { return status[Committed]; }
|
509
510 /** Sets this instruction as squashed. */
| 479
480 /** Sets this instruction as squashed. */
|
511 void setSquashed() { squashed = true; }
| 481 void setSquashed() { status.set(Squashed); }
|
512
513 /** Returns whether or not this instruction is squashed. */
| 482
483 /** Returns whether or not this instruction is squashed. */
|
514 bool isSquashed() const { return squashed; }
| 484 bool isSquashed() const { return status[Squashed]; }
|
515
516 //Instruction Queue Entry
517 //-----------------------
518 /** Sets this instruction as a entry the IQ. */
| 485
486 //Instruction Queue Entry
487 //-----------------------
488 /** Sets this instruction as a entry the IQ. */
|
519 void setInIQ() { iqEntry = true; }
| 489 void setInIQ() { status.set(IqEntry); }
|
520
521 /** Sets this instruction as a entry the IQ. */
| 490
491 /** Sets this instruction as a entry the IQ. */
|
522 void removeInIQ() { iqEntry = false; }
| 492 void clearInIQ() { status.reset(IqEntry); }
|
523
| 493
|
| 494 /** Returns whether or not this instruction has issued. */
495 bool isInIQ() const { return status[IqEntry]; }
496
|
524 /** Sets this instruction as squashed in the IQ. */
| 497 /** Sets this instruction as squashed in the IQ. */
|
525 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
| 498 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
|
526
527 /** Returns whether or not this instruction is squashed in the IQ. */
| 499
500 /** Returns whether or not this instruction is squashed in the IQ. */
|
528 bool isSquashedInIQ() const { return squashedInIQ; }
| 501 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
|
529
| 502
|
530 /** Returns whether or not this instruction has issued. */
531 bool isInIQ() const { return iqEntry; }
| |
532
| 503
|
533
| |
534 //Load / Store Queue Functions
535 //-----------------------
536 /** Sets this instruction as a entry the LSQ. */
| 504 //Load / Store Queue Functions
505 //-----------------------
506 /** Sets this instruction as a entry the LSQ. */
|
537 void setInLSQ() { lsqEntry = true; }
| 507 void setInLSQ() { status.set(LsqEntry); }
|
538
539 /** Sets this instruction as a entry the LSQ. */
| 508
509 /** Sets this instruction as a entry the LSQ. */
|
540 void removeInLSQ() { lsqEntry = false; }
| 510 void removeInLSQ() { status.reset(LsqEntry); }
|
541
| 511
|
| 512 /** Returns whether or not this instruction is in the LSQ. */
513 bool isInLSQ() const { return status[LsqEntry]; }
514
|
542 /** Sets this instruction as squashed in the LSQ. */
| 515 /** Sets this instruction as squashed in the LSQ. */
|
543 void setSquashedInLSQ() { squashedInLSQ = true;}
| 516 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
|
544
545 /** Returns whether or not this instruction is squashed in the LSQ. */
| 517
518 /** Returns whether or not this instruction is squashed in the LSQ. */
|
546 bool isSquashedInLSQ() const { return squashedInLSQ; }
| 519 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
|
547
| 520
|
548 /** Returns whether or not this instruction is in the LSQ. */
549 bool isInLSQ() const { return lsqEntry; }
| |
550
| 521
|
551
| |
552 //Reorder Buffer Functions
553 //-----------------------
554 /** Sets this instruction as a entry the ROB. */
| 522 //Reorder Buffer Functions
523 //-----------------------
524 /** Sets this instruction as a entry the ROB. */
|
555 void setInROB() { robEntry = true; }
| 525 void setInROB() { status.set(RobEntry); }
|
556
557 /** Sets this instruction as a entry the ROB. */
| 526
527 /** Sets this instruction as a entry the ROB. */
|
558 void removeInROB() { robEntry = false; }
| 528 void clearInROB() { status.reset(RobEntry); }
|
559
| 529
|
| 530 /** Returns whether or not this instruction is in the ROB. */
531 bool isInROB() const { return status[RobEntry]; }
532
|
560 /** Sets this instruction as squashed in the ROB. */
| 533 /** Sets this instruction as squashed in the ROB. */
|
561 void setSquashedInROB() { squashedInROB = true; }
| 534 void setSquashedInROB() { status.set(SquashedInROB); }
|
562
563 /** Returns whether or not this instruction is squashed in the ROB. */
| 535
536 /** Returns whether or not this instruction is squashed in the ROB. */
|
564 bool isSquashedInROB() const { return squashedInROB; }
| 537 bool isSquashedInROB() const { return status[SquashedInROB]; }
|
565
| 538
|
566 /** Returns whether or not this instruction is in the ROB. */
567 bool isInROB() const { return robEntry; }
568
| |
569 /** Read the PC of this instruction. */
570 const Addr readPC() const { return PC; }
571
572 /** Set the next PC of this instruction (its actual target). */
573 void setNextPC(uint64_t val)
574 {
575 nextPC = val;
576 }
577
578 /** Sets the ASID. */
579 void setASID(short addr_space_id) { asid = addr_space_id; }
580
581 /** Sets the thread id. */
582 void setTid(unsigned tid) { threadNumber = tid; }
583
| 539 /** Read the PC of this instruction. */
540 const Addr readPC() const { return PC; }
541
542 /** Set the next PC of this instruction (its actual target). */
543 void setNextPC(uint64_t val)
544 {
545 nextPC = val;
546 }
547
548 /** Sets the ASID. */
549 void setASID(short addr_space_id) { asid = addr_space_id; }
550
551 /** Sets the thread id. */
552 void setTid(unsigned tid) { threadNumber = tid; }
553
|
| 554 /** Sets the pointer to the thread state. */
|
584 void setThreadState(ImplState *state) { thread = state; }
585
| 555 void setThreadState(ImplState *state) { thread = state; }
556
|
586 /** Returns the thread context.
587 */
| 557 /** Returns the thread context. */
|
588 ThreadContext *tcBase() { return thread->getTC(); }
589
590 private:
591 /** Instruction effective address.
592 * @todo: Consider if this is necessary or not.
593 */
594 Addr instEffAddr;
595
596 /** Whether or not the effective address calculation is completed.
597 * @todo: Consider if this is necessary or not.
598 */
599 bool eaCalcDone;
600
601 public:
602 /** Sets the effective address. */
603 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
604
605 /** Returns the effective address. */
606 const Addr &getEA() const { return instEffAddr; }
607
608 /** Returns whether or not the eff. addr. calculation has been completed. */
609 bool doneEACalc() { return eaCalcDone; }
610
611 /** Returns whether or not the eff. addr. source registers are ready. */
612 bool eaSrcsReady();
613
614 /** Whether or not the memory operation is done. */
615 bool memOpDone;
616
617 public:
618 /** Load queue index. */
619 int16_t lqIdx;
620
621 /** Store queue index. */
622 int16_t sqIdx;
623
| 558 ThreadContext *tcBase() { return thread->getTC(); }
559
560 private:
561 /** Instruction effective address.
562 * @todo: Consider if this is necessary or not.
563 */
564 Addr instEffAddr;
565
566 /** Whether or not the effective address calculation is completed.
567 * @todo: Consider if this is necessary or not.
568 */
569 bool eaCalcDone;
570
571 public:
572 /** Sets the effective address. */
573 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
574
575 /** Returns the effective address. */
576 const Addr &getEA() const { return instEffAddr; }
577
578 /** Returns whether or not the eff. addr. calculation has been completed. */
579 bool doneEACalc() { return eaCalcDone; }
580
581 /** Returns whether or not the eff. addr. source registers are ready. */
582 bool eaSrcsReady();
583
584 /** Whether or not the memory operation is done. */
585 bool memOpDone;
586
587 public:
588 /** Load queue index. */
589 int16_t lqIdx;
590
591 /** Store queue index. */
592 int16_t sqIdx;
593
|
624 bool reachedCommit;
625
| |
626 /** Iterator pointing to this BaseDynInst in the list of all insts. */
627 ListIt instListIt;
628
629 /** Returns iterator to this instruction in the list of all insts. */
630 ListIt &getInstListIt() { return instListIt; }
631
632 /** Sets iterator for this instruction in the list of all insts. */
633 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
634};
635
636template<class Impl>
637template<class T>
638inline Fault
639BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
640{
641 // Sometimes reads will get retried, so they may come through here
642 // twice.
643 if (!req) {
644 req = new Request();
645 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
646 req->setThreadContext(thread->readCpuId(), threadNumber);
647 } else {
648 assert(addr == req->getVaddr());
649 }
650
651 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
652 TheISA::VMPageSize) {
653 return TheISA::genAlignmentFault();
654 }
655
656 fault = cpu->translateDataReadReq(req, thread);
657
658 if (fault == NoFault) {
659 effAddr = req->getVaddr();
660 physEffAddr = req->getPaddr();
661 memReqFlags = req->getFlags();
662
663#if 0
664 if (cpu->system->memctrl->badaddr(physEffAddr)) {
665 fault = TheISA::genMachineCheckFault();
666 data = (T)-1;
667 this->setExecuted();
668 } else {
669 fault = cpu->read(req, data, lqIdx);
670 }
671#else
672 fault = cpu->read(req, data, lqIdx);
673#endif
674 } else {
675 // Return a fixed value to keep simulation deterministic even
676 // along misspeculated paths.
677 data = (T)-1;
678
679 // Commit will have to clean up whatever happened. Set this
680 // instruction as executed.
681 this->setExecuted();
682 }
683
684 if (traceData) {
685 traceData->setAddr(addr);
686 traceData->setData(data);
687 }
688
689 return fault;
690}
691
692template<class Impl>
693template<class T>
694inline Fault
695BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
696{
697 if (traceData) {
698 traceData->setAddr(addr);
699 traceData->setData(data);
700 }
701
702 assert(req == NULL);
703
704 req = new Request();
705 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
706 req->setThreadContext(thread->readCpuId(), threadNumber);
707
708 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
709 TheISA::VMPageSize) {
710 return TheISA::genAlignmentFault();
711 }
712
713 fault = cpu->translateDataWriteReq(req, thread);
714
715 if (fault == NoFault) {
716 effAddr = req->getVaddr();
717 physEffAddr = req->getPaddr();
718 memReqFlags = req->getFlags();
719#if 0
720 if (cpu->system->memctrl->badaddr(physEffAddr)) {
721 fault = TheISA::genMachineCheckFault();
722 } else {
723 fault = cpu->write(req, data, sqIdx);
724 }
725#else
726 fault = cpu->write(req, data, sqIdx);
727#endif
728 }
729
730 if (res) {
731 // always return some result to keep misspeculated paths
732 // (which will ignore faults) deterministic
733 *res = (fault == NoFault) ? req->getScResult() : 0;
734 }
735
736 return fault;
737}
738
739#endif // __CPU_BASE_DYN_INST_HH__
| 594 /** Iterator pointing to this BaseDynInst in the list of all insts. */
595 ListIt instListIt;
596
597 /** Returns iterator to this instruction in the list of all insts. */
598 ListIt &getInstListIt() { return instListIt; }
599
600 /** Sets iterator for this instruction in the list of all insts. */
601 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
602};
603
604template<class Impl>
605template<class T>
606inline Fault
607BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
608{
609 // Sometimes reads will get retried, so they may come through here
610 // twice.
611 if (!req) {
612 req = new Request();
613 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
614 req->setThreadContext(thread->readCpuId(), threadNumber);
615 } else {
616 assert(addr == req->getVaddr());
617 }
618
619 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
620 TheISA::VMPageSize) {
621 return TheISA::genAlignmentFault();
622 }
623
624 fault = cpu->translateDataReadReq(req, thread);
625
626 if (fault == NoFault) {
627 effAddr = req->getVaddr();
628 physEffAddr = req->getPaddr();
629 memReqFlags = req->getFlags();
630
631#if 0
632 if (cpu->system->memctrl->badaddr(physEffAddr)) {
633 fault = TheISA::genMachineCheckFault();
634 data = (T)-1;
635 this->setExecuted();
636 } else {
637 fault = cpu->read(req, data, lqIdx);
638 }
639#else
640 fault = cpu->read(req, data, lqIdx);
641#endif
642 } else {
643 // Return a fixed value to keep simulation deterministic even
644 // along misspeculated paths.
645 data = (T)-1;
646
647 // Commit will have to clean up whatever happened. Set this
648 // instruction as executed.
649 this->setExecuted();
650 }
651
652 if (traceData) {
653 traceData->setAddr(addr);
654 traceData->setData(data);
655 }
656
657 return fault;
658}
659
660template<class Impl>
661template<class T>
662inline Fault
663BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
664{
665 if (traceData) {
666 traceData->setAddr(addr);
667 traceData->setData(data);
668 }
669
670 assert(req == NULL);
671
672 req = new Request();
673 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
674 req->setThreadContext(thread->readCpuId(), threadNumber);
675
676 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
677 TheISA::VMPageSize) {
678 return TheISA::genAlignmentFault();
679 }
680
681 fault = cpu->translateDataWriteReq(req, thread);
682
683 if (fault == NoFault) {
684 effAddr = req->getVaddr();
685 physEffAddr = req->getPaddr();
686 memReqFlags = req->getFlags();
687#if 0
688 if (cpu->system->memctrl->badaddr(physEffAddr)) {
689 fault = TheISA::genMachineCheckFault();
690 } else {
691 fault = cpu->write(req, data, sqIdx);
692 }
693#else
694 fault = cpu->write(req, data, sqIdx);
695#endif
696 }
697
698 if (res) {
699 // always return some result to keep misspeculated paths
700 // (which will ignore faults) deterministic
701 *res = (fault == NoFault) ? req->getScResult() : 0;
702 }
703
704 return fault;
705}
706
707#endif // __CPU_BASE_DYN_INST_HH__
|