1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <list>
35#include <string>
36
37#include "arch/faults.hh"
38#include "base/fast_alloc.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/inst_seq.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst.hh"
45#include "mem/packet.hh"
46#include "sim/system.hh"
47/*
48#include "encumbered/cpu/full/bpred_update.hh"
49#include "encumbered/cpu/full/spec_memory.hh"
50#include "encumbered/cpu/full/spec_state.hh"
51#include "encumbered/mem/functional/main.hh"
52*/
53
54/**
55 * @file
56 * Defines a dynamic instruction context.
57 */
58
59// Forward declaration.
60class StaticInstPtr;
61
62template <class Impl>
63class BaseDynInst : public FastAlloc, public RefCounted
64{
65 public:
66 // Typedef for the CPU.
67 typedef typename Impl::FullCPU FullCPU;
68 typedef typename FullCPU::ImplState ImplState;
69
70 // Binary machine instruction type.
71 typedef TheISA::MachInst MachInst;
72 // Extended machine instruction type
73 typedef TheISA::ExtMachInst ExtMachInst;
74 // Logical register index type.
75 typedef TheISA::RegIndex RegIndex;
76 // Integer register type.
77 typedef TheISA::IntReg IntReg;
78 // Floating point register type.
79 typedef TheISA::FloatReg FloatReg;
80
81 // The DynInstPtr type.
82 typedef typename Impl::DynInstPtr DynInstPtr;
83
84 // The list of instructions iterator type.
85 typedef typename std::list<DynInstPtr>::iterator ListIt;
86
87 enum {
88 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
89 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
90 };
91
92 /** The StaticInst used by this BaseDynInst. */
93 StaticInstPtr staticInst;
94
95 ////////////////////////////////////////////
96 //
97 // INSTRUCTION EXECUTION
98 //
99 ////////////////////////////////////////////
100 /** InstRecord that tracks this instructions. */
101 Trace::InstRecord *traceData;
102
103 /**
104 * Does a read to a given address.
105 * @param addr The address to read.
106 * @param data The read's data is written into this parameter.
107 * @param flags The request's flags.
108 * @return Returns any fault due to the read.
109 */
110 template <class T>
111 Fault read(Addr addr, T &data, unsigned flags);
112
113 /**
114 * Does a write to a given address.
115 * @param data The data to be written.
116 * @param addr The address to write to.
117 * @param flags The request's flags.
118 * @param res The result of the write (for load locked/store conditionals).
119 * @return Returns any fault due to the write.
120 */
121 template <class T>
122 Fault write(T data, Addr addr, unsigned flags,
123 uint64_t *res);
124
125 void prefetch(Addr addr, unsigned flags);
126 void writeHint(Addr addr, int size, unsigned flags);
127 Fault copySrcTranslate(Addr src);
128 Fault copy(Addr dest);
129
130 /** @todo: Consider making this private. */
131 public:
132 /** The sequence number of the instruction. */
133 InstSeqNum seqNum;
134
135 /** Is the instruction in the IQ */
136 bool iqEntry;
137
138 /** Is the instruction in the ROB */
139 bool robEntry;
140
141 /** Is the instruction in the LSQ */
142 bool lsqEntry;
143
144 /** Is the instruction completed. */
145 bool completed;
146
147 /** Is the instruction's result ready. */
148 bool resultReady;
149
150 /** Can this instruction issue. */
151 bool canIssue;
152
153 /** Has this instruction issued. */
154 bool issued;
155
156 /** Has this instruction executed (or made it through execute) yet. */
157 bool executed;
158
159 /** Can this instruction commit. */
160 bool canCommit;
161
162 /** Is this instruction committed. */
163 bool committed;
164
165 /** Is this instruction squashed. */
166 bool squashed;
167
168 /** Is this instruction squashed in the instruction queue. */
169 bool squashedInIQ;
170
171 /** Is this instruction squashed in the instruction queue. */
172 bool squashedInLSQ;
173
174 /** Is this instruction squashed in the instruction queue. */
175 bool squashedInROB;
176
177 /** Is this a recover instruction. */
178 bool recoverInst;
179
180 /** Is this a thread blocking instruction. */
181 bool blockingInst; /* this inst has called thread_block() */
182
183 /** Is this a thread syncrhonization instruction. */
184 bool threadsyncWait;
185
186 /** The thread this instruction is from. */
187 short threadNumber;
188
189 /** data address space ID, for loads & stores. */
190 short asid;
191
192 /** How many source registers are ready. */
193 unsigned readyRegs;
194
195 /** Pointer to the FullCPU object. */
196 FullCPU *cpu;
197
198 /** Pointer to the thread state. */
199 ImplState *thread;
200
201 /** The kind of fault this instruction has generated. */
202 Fault fault;
203
204 /** The memory request. */
205// MemReqPtr req;
206 Request *req;
207// Packet pkt;
208
209 uint8_t *memData;
210
211 /** The effective virtual address (lds & stores only). */
212 Addr effAddr;
213
214 /** The effective physical address. */
215 Addr physEffAddr;
216
217 /** Effective virtual address for a copy source. */
218 Addr copySrcEffAddr;
219
220 /** Effective physical address for a copy source. */
221 Addr copySrcPhysEffAddr;
222
223 /** The memory request flags (from translation). */
224 unsigned memReqFlags;
225
226 /** The size of the data to be stored. */
227 int storeSize;
228
229 /** The data to be stored. */
230 IntReg storeData;
231
232 union Result {
233 uint64_t integer;
234 float fp;
235 double dbl;
236 };
237
238 /** The result of the instruction; assumes for now that there's only one
239 * destination register.
240 */
241 Result instResult;
242
243 /** PC of this instruction. */
244 Addr PC;
245
246 /** Next non-speculative PC. It is not filled in at fetch, but rather
247 * once the target of the branch is truly known (either decode or
248 * execute).
249 */
250 Addr nextPC;
251
252 /** Predicted next PC. */
253 Addr predPC;
254
255 /** Count of total number of dynamic instructions. */
256 static int instcount;
257
258#ifdef DEBUG
259 void dumpSNList();
260#endif
261
262 /** Whether or not the source register is ready.
263 * @todo: Not sure this should be here vs the derived class.
264 */
265 bool _readySrcRegIdx[MaxInstSrcRegs];
266
267 public:
268 /** BaseDynInst constructor given a binary instruction.
269 * @param inst The binary instruction.
270 * @param PC The PC of the instruction.
271 * @param pred_PC The predicted next PC.
272 * @param seq_num The sequence number of the instruction.
273 * @param cpu Pointer to the instruction's CPU.
274 */
275 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
276 FullCPU *cpu);
277
278 /** BaseDynInst constructor given a StaticInst pointer.
279 * @param _staticInst The StaticInst for this BaseDynInst.
280 */
281 BaseDynInst(StaticInstPtr &_staticInst);
282
283 /** BaseDynInst destructor. */
284 ~BaseDynInst();
285
286 private:
287 /** Function to initialize variables in the constructors. */
288 void initVars();
289
290 public:
291 /**
292 * @todo: Make this function work; currently it is a dummy function.
293 * @param fault Last fault.
294 * @param cmd Last command.
295 * @param addr Virtual address of access.
296 * @param p Memory accessed.
297 * @param nbytes Access size.
298 */
299// void
300// trace_mem(Fault fault,
301// MemCmd cmd,
302// Addr addr,
303// void *p,
304// int nbytes);
305
306 /** Dumps out contents of this BaseDynInst. */
307 void dump();
308
309 /** Dumps out contents of this BaseDynInst into given string. */
310 void dump(std::string &outstring);
311
312 /** Returns the fault type. */
313 Fault getFault() { return fault; }
314
315 /** Checks whether or not this instruction has had its branch target
316 * calculated yet. For now it is not utilized and is hacked to be
317 * always false.
318 * @todo: Actually use this instruction.
319 */
320 bool doneTargCalc() { return false; }
321
322 /** Returns the next PC. This could be the speculative next PC if it is
323 * called prior to the actual branch target being calculated.
324 */
325 Addr readNextPC() { return nextPC; }
326
327 /** Set the predicted target of this current instruction. */
328 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
329
330 /** Returns the predicted target of the branch. */
331 Addr readPredTarg() { return predPC; }
332
333 /** Returns whether the instruction was predicted taken or not. */
334 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
335
336 /** Returns whether the instruction mispredicted. */
337 bool mispredicted() { return predPC != nextPC; }
338
339 //
340 // Instruction types. Forward checks to StaticInst object.
341 //
342 bool isNop() const { return staticInst->isNop(); }
343 bool isMemRef() const { return staticInst->isMemRef(); }
344 bool isLoad() const { return staticInst->isLoad(); }
345 bool isStore() const { return staticInst->isStore(); }
346 bool isStoreConditional() const
347 { return staticInst->isStoreConditional(); }
348 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
349 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
350 bool isCopy() const { return staticInst->isCopy(); }
351 bool isInteger() const { return staticInst->isInteger(); }
352 bool isFloating() const { return staticInst->isFloating(); }
353 bool isControl() const { return staticInst->isControl(); }
354 bool isCall() const { return staticInst->isCall(); }
355 bool isReturn() const { return staticInst->isReturn(); }
356 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
357 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
358 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
359 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
360 bool isThreadSync() const { return staticInst->isThreadSync(); }
361 bool isSerializing() const { return staticInst->isSerializing(); }
362 bool isSerializeBefore() const
363 { return staticInst->isSerializeBefore() || serializeBefore; }
364 bool isSerializeAfter() const
365 { return staticInst->isSerializeAfter() || serializeAfter; }
366 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
367 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
368 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
369 bool isQuiesce() const { return staticInst->isQuiesce(); }
370 bool isIprAccess() const { return staticInst->isIprAccess(); }
371 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
372
373 /** Temporarily sets this instruction as a serialize before instruction. */
374 void setSerializeBefore() { serializeBefore = true; }
375
376 /** Clears the serializeBefore part of this instruction. */
377 void clearSerializeBefore() { serializeBefore = false; }
378
379 /** Checks if this serializeBefore is only temporarily set. */
380 bool isTempSerializeBefore() { return serializeBefore; }
381
382 /** Tracks if instruction has been externally set as serializeBefore. */
383 bool serializeBefore;
384
385 /** Temporarily sets this instruction as a serialize after instruction. */
386 void setSerializeAfter() { serializeAfter = true; }
387
388 /** Clears the serializeAfter part of this instruction.*/
389 void clearSerializeAfter() { serializeAfter = false; }
390
391 /** Checks if this serializeAfter is only temporarily set. */
392 bool isTempSerializeAfter() { return serializeAfter; }
393
394 /** Tracks if instruction has been externally set as serializeAfter. */
395 bool serializeAfter;
396
397 /** Checks if the serialization part of this instruction has been
398 * handled. This does not apply to the temporary serializing
399 * state; it only applies to this instruction's own permanent
400 * serializing state.
401 */
402 bool isSerializeHandled() { return serializeHandled; }
403
404 /** Sets the serialization part of this instruction as handled. */
405 void setSerializeHandled() { serializeHandled = true; }
406
407 /** Whether or not the serialization of this instruction has been handled. */
408 bool serializeHandled;
409
410 /** Returns the opclass of this instruction. */
411 OpClass opClass() const { return staticInst->opClass(); }
412
413 /** Returns the branch target address. */
414 Addr branchTarget() const { return staticInst->branchTarget(PC); }
415
416 /** Returns the number of source registers. */
417 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
418
419 /** Returns the number of destination registers. */
420 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
421
422 // the following are used to track physical register usage
423 // for machines with separate int & FP reg files
424 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
425 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
426
427 /** Returns the logical register index of the i'th destination register. */
428 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
429
430 /** Returns the logical register index of the i'th source register. */
431 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
432
433 /** Returns the result of an integer instruction. */
434 uint64_t readIntResult() { return instResult.integer; }
435
436 /** Returns the result of a floating point instruction. */
437 float readFloatResult() { return instResult.fp; }
438
439 /** Returns the result of a floating point (double) instruction. */
440 double readDoubleResult() { return instResult.dbl; }
441
442 void setIntReg(const StaticInst *si, int idx, uint64_t val)
443 {
444 instResult.integer = val;
445 }
446
447 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
448 {
449 if (width == 32)
450 instResult.fp = val;
451 else if (width == 64)
452 instResult.dbl = val;
453 else
454 panic("Unsupported width!");
455 }
456
457 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
458 {
459 instResult.fp = val;
460 }
461
462 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
463 {
464 instResult.integer = val;
465 }
466
467 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
468 {
469 instResult.integer = val;
470 }
471
472 /** Records that one of the source registers is ready. */
473 void markSrcRegReady();
474
475 /** Marks a specific register as ready. */
476 void markSrcRegReady(RegIndex src_idx);
477
478 /** Returns if a source register is ready. */
479 bool isReadySrcRegIdx(int idx) const
480 {
481 return this->_readySrcRegIdx[idx];
482 }
483
484 /** Sets this instruction as completed. */
485 void setCompleted() { completed = true; }
486
487 /** Returns whether or not this instruction is completed. */
488 bool isCompleted() const { return completed; }
489
490 void setResultReady() { resultReady = true; }
491
492 bool isResultReady() const { return resultReady; }
493
494 /** Sets this instruction as ready to issue. */
495 void setCanIssue() { canIssue = true; }
496
497 /** Returns whether or not this instruction is ready to issue. */
498 bool readyToIssue() const { return canIssue; }
499
500 /** Sets this instruction as issued from the IQ. */
501 void setIssued() { issued = true; }
502
503 /** Returns whether or not this instruction has issued. */
504 bool isIssued() const { return issued; }
505
506 /** Sets this instruction as executed. */
507 void setExecuted() { executed = true; }
508
509 /** Returns whether or not this instruction has executed. */
510 bool isExecuted() const { return executed; }
511
512 /** Sets this instruction as ready to commit. */
513 void setCanCommit() { canCommit = true; }
514
515 /** Clears this instruction as being ready to commit. */
516 void clearCanCommit() { canCommit = false; }
517
518 /** Returns whether or not this instruction is ready to commit. */
519 bool readyToCommit() const { return canCommit; }
520
521 /** Sets this instruction as committed. */
522 void setCommitted() { committed = true; }
523
524 /** Returns whether or not this instruction is committed. */
525 bool isCommitted() const { return committed; }
526
527 /** Sets this instruction as squashed. */
528 void setSquashed() { squashed = true; }
529
530 /** Returns whether or not this instruction is squashed. */
531 bool isSquashed() const { return squashed; }
532
533 //Instruction Queue Entry
534 //-----------------------
535 /** Sets this instruction as a entry the IQ. */
536 void setInIQ() { iqEntry = true; }
537
538 /** Sets this instruction as a entry the IQ. */
539 void removeInIQ() { iqEntry = false; }
540
541 /** Sets this instruction as squashed in the IQ. */
542 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
543
544 /** Returns whether or not this instruction is squashed in the IQ. */
545 bool isSquashedInIQ() const { return squashedInIQ; }
546
547 /** Returns whether or not this instruction has issued. */
548 bool isInIQ() const { return iqEntry; }
549
550
551 //Load / Store Queue Functions
552 //-----------------------
553 /** Sets this instruction as a entry the LSQ. */
554 void setInLSQ() { lsqEntry = true; }
555
556 /** Sets this instruction as a entry the LSQ. */
557 void removeInLSQ() { lsqEntry = false; }
558
559 /** Sets this instruction as squashed in the LSQ. */
560 void setSquashedInLSQ() { squashedInLSQ = true;}
561
562 /** Returns whether or not this instruction is squashed in the LSQ. */
563 bool isSquashedInLSQ() const { return squashedInLSQ; }
564
565 /** Returns whether or not this instruction is in the LSQ. */
566 bool isInLSQ() const { return lsqEntry; }
567
568
569 //Reorder Buffer Functions
570 //-----------------------
571 /** Sets this instruction as a entry the ROB. */
572 void setInROB() { robEntry = true; }
573
574 /** Sets this instruction as a entry the ROB. */
575 void removeInROB() { robEntry = false; }
576
577 /** Sets this instruction as squashed in the ROB. */
578 void setSquashedInROB() { squashedInROB = true; }
579
580 /** Returns whether or not this instruction is squashed in the ROB. */
581 bool isSquashedInROB() const { return squashedInROB; }
582
583 /** Returns whether or not this instruction is in the ROB. */
584 bool isInROB() const { return robEntry; }
585
586 /** Read the PC of this instruction. */
587 const Addr readPC() const { return PC; }
588
589 /** Set the next PC of this instruction (its actual target). */
590 void setNextPC(uint64_t val)
591 {
592 nextPC = val;
593// instResult.integer = val;
594 }
595
596 void setASID(short addr_space_id) { asid = addr_space_id; }
597
598 void setThread(unsigned tid) { threadNumber = tid; }
599
600 void setState(ImplState *state) { thread = state; }
601
602 /** Returns the thread context.
603 */
604 ThreadContext *tcBase() { return thread->getTC(); }
605
606 private:
607 /** Instruction effective address.
608 * @todo: Consider if this is necessary or not.
609 */
610 Addr instEffAddr;
611
612 /** Whether or not the effective address calculation is completed.
613 * @todo: Consider if this is necessary or not.
614 */
615 bool eaCalcDone;
616
617 public:
618 /** Sets the effective address. */
619 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
620
621 /** Returns the effective address. */
622 const Addr &getEA() const { return instEffAddr; }
623
624 /** Returns whether or not the eff. addr. calculation has been completed. */
625 bool doneEACalc() { return eaCalcDone; }
626
627 /** Returns whether or not the eff. addr. source registers are ready. */
628 bool eaSrcsReady();
629
630 /** Whether or not the memory operation is done. */
631 bool memOpDone;
632
633 public:
634 /** Load queue index. */
635 int16_t lqIdx;
636
637 /** Store queue index. */
638 int16_t sqIdx;
639
640 bool reachedCommit;
641
642 /** Iterator pointing to this BaseDynInst in the list of all insts. */
643 ListIt instListIt;
644
645 /** Returns iterator to this instruction in the list of all insts. */
646 ListIt &getInstListIt() { return instListIt; }
647
648 /** Sets iterator for this instruction in the list of all insts. */
649 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
650};
651
652template<class Impl>
653template<class T>
654inline Fault
655BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
656{
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <list>
35#include <string>
36
37#include "arch/faults.hh"
38#include "base/fast_alloc.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/inst_seq.hh"
43#include "cpu/op_class.hh"
44#include "cpu/static_inst.hh"
45#include "mem/packet.hh"
46#include "sim/system.hh"
47/*
48#include "encumbered/cpu/full/bpred_update.hh"
49#include "encumbered/cpu/full/spec_memory.hh"
50#include "encumbered/cpu/full/spec_state.hh"
51#include "encumbered/mem/functional/main.hh"
52*/
53
54/**
55 * @file
56 * Defines a dynamic instruction context.
57 */
58
59// Forward declaration.
60class StaticInstPtr;
61
62template <class Impl>
63class BaseDynInst : public FastAlloc, public RefCounted
64{
65 public:
66 // Typedef for the CPU.
67 typedef typename Impl::FullCPU FullCPU;
68 typedef typename FullCPU::ImplState ImplState;
69
70 // Binary machine instruction type.
71 typedef TheISA::MachInst MachInst;
72 // Extended machine instruction type
73 typedef TheISA::ExtMachInst ExtMachInst;
74 // Logical register index type.
75 typedef TheISA::RegIndex RegIndex;
76 // Integer register type.
77 typedef TheISA::IntReg IntReg;
78 // Floating point register type.
79 typedef TheISA::FloatReg FloatReg;
80
81 // The DynInstPtr type.
82 typedef typename Impl::DynInstPtr DynInstPtr;
83
84 // The list of instructions iterator type.
85 typedef typename std::list<DynInstPtr>::iterator ListIt;
86
87 enum {
88 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
89 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
90 };
91
92 /** The StaticInst used by this BaseDynInst. */
93 StaticInstPtr staticInst;
94
95 ////////////////////////////////////////////
96 //
97 // INSTRUCTION EXECUTION
98 //
99 ////////////////////////////////////////////
100 /** InstRecord that tracks this instructions. */
101 Trace::InstRecord *traceData;
102
103 /**
104 * Does a read to a given address.
105 * @param addr The address to read.
106 * @param data The read's data is written into this parameter.
107 * @param flags The request's flags.
108 * @return Returns any fault due to the read.
109 */
110 template <class T>
111 Fault read(Addr addr, T &data, unsigned flags);
112
113 /**
114 * Does a write to a given address.
115 * @param data The data to be written.
116 * @param addr The address to write to.
117 * @param flags The request's flags.
118 * @param res The result of the write (for load locked/store conditionals).
119 * @return Returns any fault due to the write.
120 */
121 template <class T>
122 Fault write(T data, Addr addr, unsigned flags,
123 uint64_t *res);
124
125 void prefetch(Addr addr, unsigned flags);
126 void writeHint(Addr addr, int size, unsigned flags);
127 Fault copySrcTranslate(Addr src);
128 Fault copy(Addr dest);
129
130 /** @todo: Consider making this private. */
131 public:
132 /** The sequence number of the instruction. */
133 InstSeqNum seqNum;
134
135 /** Is the instruction in the IQ */
136 bool iqEntry;
137
138 /** Is the instruction in the ROB */
139 bool robEntry;
140
141 /** Is the instruction in the LSQ */
142 bool lsqEntry;
143
144 /** Is the instruction completed. */
145 bool completed;
146
147 /** Is the instruction's result ready. */
148 bool resultReady;
149
150 /** Can this instruction issue. */
151 bool canIssue;
152
153 /** Has this instruction issued. */
154 bool issued;
155
156 /** Has this instruction executed (or made it through execute) yet. */
157 bool executed;
158
159 /** Can this instruction commit. */
160 bool canCommit;
161
162 /** Is this instruction committed. */
163 bool committed;
164
165 /** Is this instruction squashed. */
166 bool squashed;
167
168 /** Is this instruction squashed in the instruction queue. */
169 bool squashedInIQ;
170
171 /** Is this instruction squashed in the instruction queue. */
172 bool squashedInLSQ;
173
174 /** Is this instruction squashed in the instruction queue. */
175 bool squashedInROB;
176
177 /** Is this a recover instruction. */
178 bool recoverInst;
179
180 /** Is this a thread blocking instruction. */
181 bool blockingInst; /* this inst has called thread_block() */
182
183 /** Is this a thread syncrhonization instruction. */
184 bool threadsyncWait;
185
186 /** The thread this instruction is from. */
187 short threadNumber;
188
189 /** data address space ID, for loads & stores. */
190 short asid;
191
192 /** How many source registers are ready. */
193 unsigned readyRegs;
194
195 /** Pointer to the FullCPU object. */
196 FullCPU *cpu;
197
198 /** Pointer to the thread state. */
199 ImplState *thread;
200
201 /** The kind of fault this instruction has generated. */
202 Fault fault;
203
204 /** The memory request. */
205// MemReqPtr req;
206 Request *req;
207// Packet pkt;
208
209 uint8_t *memData;
210
211 /** The effective virtual address (lds & stores only). */
212 Addr effAddr;
213
214 /** The effective physical address. */
215 Addr physEffAddr;
216
217 /** Effective virtual address for a copy source. */
218 Addr copySrcEffAddr;
219
220 /** Effective physical address for a copy source. */
221 Addr copySrcPhysEffAddr;
222
223 /** The memory request flags (from translation). */
224 unsigned memReqFlags;
225
226 /** The size of the data to be stored. */
227 int storeSize;
228
229 /** The data to be stored. */
230 IntReg storeData;
231
232 union Result {
233 uint64_t integer;
234 float fp;
235 double dbl;
236 };
237
238 /** The result of the instruction; assumes for now that there's only one
239 * destination register.
240 */
241 Result instResult;
242
243 /** PC of this instruction. */
244 Addr PC;
245
246 /** Next non-speculative PC. It is not filled in at fetch, but rather
247 * once the target of the branch is truly known (either decode or
248 * execute).
249 */
250 Addr nextPC;
251
252 /** Predicted next PC. */
253 Addr predPC;
254
255 /** Count of total number of dynamic instructions. */
256 static int instcount;
257
258#ifdef DEBUG
259 void dumpSNList();
260#endif
261
262 /** Whether or not the source register is ready.
263 * @todo: Not sure this should be here vs the derived class.
264 */
265 bool _readySrcRegIdx[MaxInstSrcRegs];
266
267 public:
268 /** BaseDynInst constructor given a binary instruction.
269 * @param inst The binary instruction.
270 * @param PC The PC of the instruction.
271 * @param pred_PC The predicted next PC.
272 * @param seq_num The sequence number of the instruction.
273 * @param cpu Pointer to the instruction's CPU.
274 */
275 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
276 FullCPU *cpu);
277
278 /** BaseDynInst constructor given a StaticInst pointer.
279 * @param _staticInst The StaticInst for this BaseDynInst.
280 */
281 BaseDynInst(StaticInstPtr &_staticInst);
282
283 /** BaseDynInst destructor. */
284 ~BaseDynInst();
285
286 private:
287 /** Function to initialize variables in the constructors. */
288 void initVars();
289
290 public:
291 /**
292 * @todo: Make this function work; currently it is a dummy function.
293 * @param fault Last fault.
294 * @param cmd Last command.
295 * @param addr Virtual address of access.
296 * @param p Memory accessed.
297 * @param nbytes Access size.
298 */
299// void
300// trace_mem(Fault fault,
301// MemCmd cmd,
302// Addr addr,
303// void *p,
304// int nbytes);
305
306 /** Dumps out contents of this BaseDynInst. */
307 void dump();
308
309 /** Dumps out contents of this BaseDynInst into given string. */
310 void dump(std::string &outstring);
311
312 /** Returns the fault type. */
313 Fault getFault() { return fault; }
314
315 /** Checks whether or not this instruction has had its branch target
316 * calculated yet. For now it is not utilized and is hacked to be
317 * always false.
318 * @todo: Actually use this instruction.
319 */
320 bool doneTargCalc() { return false; }
321
322 /** Returns the next PC. This could be the speculative next PC if it is
323 * called prior to the actual branch target being calculated.
324 */
325 Addr readNextPC() { return nextPC; }
326
327 /** Set the predicted target of this current instruction. */
328 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
329
330 /** Returns the predicted target of the branch. */
331 Addr readPredTarg() { return predPC; }
332
333 /** Returns whether the instruction was predicted taken or not. */
334 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
335
336 /** Returns whether the instruction mispredicted. */
337 bool mispredicted() { return predPC != nextPC; }
338
339 //
340 // Instruction types. Forward checks to StaticInst object.
341 //
342 bool isNop() const { return staticInst->isNop(); }
343 bool isMemRef() const { return staticInst->isMemRef(); }
344 bool isLoad() const { return staticInst->isLoad(); }
345 bool isStore() const { return staticInst->isStore(); }
346 bool isStoreConditional() const
347 { return staticInst->isStoreConditional(); }
348 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
349 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
350 bool isCopy() const { return staticInst->isCopy(); }
351 bool isInteger() const { return staticInst->isInteger(); }
352 bool isFloating() const { return staticInst->isFloating(); }
353 bool isControl() const { return staticInst->isControl(); }
354 bool isCall() const { return staticInst->isCall(); }
355 bool isReturn() const { return staticInst->isReturn(); }
356 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
357 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
358 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
359 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
360 bool isThreadSync() const { return staticInst->isThreadSync(); }
361 bool isSerializing() const { return staticInst->isSerializing(); }
362 bool isSerializeBefore() const
363 { return staticInst->isSerializeBefore() || serializeBefore; }
364 bool isSerializeAfter() const
365 { return staticInst->isSerializeAfter() || serializeAfter; }
366 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
367 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
368 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
369 bool isQuiesce() const { return staticInst->isQuiesce(); }
370 bool isIprAccess() const { return staticInst->isIprAccess(); }
371 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
372
373 /** Temporarily sets this instruction as a serialize before instruction. */
374 void setSerializeBefore() { serializeBefore = true; }
375
376 /** Clears the serializeBefore part of this instruction. */
377 void clearSerializeBefore() { serializeBefore = false; }
378
379 /** Checks if this serializeBefore is only temporarily set. */
380 bool isTempSerializeBefore() { return serializeBefore; }
381
382 /** Tracks if instruction has been externally set as serializeBefore. */
383 bool serializeBefore;
384
385 /** Temporarily sets this instruction as a serialize after instruction. */
386 void setSerializeAfter() { serializeAfter = true; }
387
388 /** Clears the serializeAfter part of this instruction.*/
389 void clearSerializeAfter() { serializeAfter = false; }
390
391 /** Checks if this serializeAfter is only temporarily set. */
392 bool isTempSerializeAfter() { return serializeAfter; }
393
394 /** Tracks if instruction has been externally set as serializeAfter. */
395 bool serializeAfter;
396
397 /** Checks if the serialization part of this instruction has been
398 * handled. This does not apply to the temporary serializing
399 * state; it only applies to this instruction's own permanent
400 * serializing state.
401 */
402 bool isSerializeHandled() { return serializeHandled; }
403
404 /** Sets the serialization part of this instruction as handled. */
405 void setSerializeHandled() { serializeHandled = true; }
406
407 /** Whether or not the serialization of this instruction has been handled. */
408 bool serializeHandled;
409
410 /** Returns the opclass of this instruction. */
411 OpClass opClass() const { return staticInst->opClass(); }
412
413 /** Returns the branch target address. */
414 Addr branchTarget() const { return staticInst->branchTarget(PC); }
415
416 /** Returns the number of source registers. */
417 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
418
419 /** Returns the number of destination registers. */
420 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
421
422 // the following are used to track physical register usage
423 // for machines with separate int & FP reg files
424 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
425 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
426
427 /** Returns the logical register index of the i'th destination register. */
428 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
429
430 /** Returns the logical register index of the i'th source register. */
431 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
432
433 /** Returns the result of an integer instruction. */
434 uint64_t readIntResult() { return instResult.integer; }
435
436 /** Returns the result of a floating point instruction. */
437 float readFloatResult() { return instResult.fp; }
438
439 /** Returns the result of a floating point (double) instruction. */
440 double readDoubleResult() { return instResult.dbl; }
441
442 void setIntReg(const StaticInst *si, int idx, uint64_t val)
443 {
444 instResult.integer = val;
445 }
446
447 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
448 {
449 if (width == 32)
450 instResult.fp = val;
451 else if (width == 64)
452 instResult.dbl = val;
453 else
454 panic("Unsupported width!");
455 }
456
457 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
458 {
459 instResult.fp = val;
460 }
461
462 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
463 {
464 instResult.integer = val;
465 }
466
467 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
468 {
469 instResult.integer = val;
470 }
471
472 /** Records that one of the source registers is ready. */
473 void markSrcRegReady();
474
475 /** Marks a specific register as ready. */
476 void markSrcRegReady(RegIndex src_idx);
477
478 /** Returns if a source register is ready. */
479 bool isReadySrcRegIdx(int idx) const
480 {
481 return this->_readySrcRegIdx[idx];
482 }
483
484 /** Sets this instruction as completed. */
485 void setCompleted() { completed = true; }
486
487 /** Returns whether or not this instruction is completed. */
488 bool isCompleted() const { return completed; }
489
490 void setResultReady() { resultReady = true; }
491
492 bool isResultReady() const { return resultReady; }
493
494 /** Sets this instruction as ready to issue. */
495 void setCanIssue() { canIssue = true; }
496
497 /** Returns whether or not this instruction is ready to issue. */
498 bool readyToIssue() const { return canIssue; }
499
500 /** Sets this instruction as issued from the IQ. */
501 void setIssued() { issued = true; }
502
503 /** Returns whether or not this instruction has issued. */
504 bool isIssued() const { return issued; }
505
506 /** Sets this instruction as executed. */
507 void setExecuted() { executed = true; }
508
509 /** Returns whether or not this instruction has executed. */
510 bool isExecuted() const { return executed; }
511
512 /** Sets this instruction as ready to commit. */
513 void setCanCommit() { canCommit = true; }
514
515 /** Clears this instruction as being ready to commit. */
516 void clearCanCommit() { canCommit = false; }
517
518 /** Returns whether or not this instruction is ready to commit. */
519 bool readyToCommit() const { return canCommit; }
520
521 /** Sets this instruction as committed. */
522 void setCommitted() { committed = true; }
523
524 /** Returns whether or not this instruction is committed. */
525 bool isCommitted() const { return committed; }
526
527 /** Sets this instruction as squashed. */
528 void setSquashed() { squashed = true; }
529
530 /** Returns whether or not this instruction is squashed. */
531 bool isSquashed() const { return squashed; }
532
533 //Instruction Queue Entry
534 //-----------------------
535 /** Sets this instruction as a entry the IQ. */
536 void setInIQ() { iqEntry = true; }
537
538 /** Sets this instruction as a entry the IQ. */
539 void removeInIQ() { iqEntry = false; }
540
541 /** Sets this instruction as squashed in the IQ. */
542 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
543
544 /** Returns whether or not this instruction is squashed in the IQ. */
545 bool isSquashedInIQ() const { return squashedInIQ; }
546
547 /** Returns whether or not this instruction has issued. */
548 bool isInIQ() const { return iqEntry; }
549
550
551 //Load / Store Queue Functions
552 //-----------------------
553 /** Sets this instruction as a entry the LSQ. */
554 void setInLSQ() { lsqEntry = true; }
555
556 /** Sets this instruction as a entry the LSQ. */
557 void removeInLSQ() { lsqEntry = false; }
558
559 /** Sets this instruction as squashed in the LSQ. */
560 void setSquashedInLSQ() { squashedInLSQ = true;}
561
562 /** Returns whether or not this instruction is squashed in the LSQ. */
563 bool isSquashedInLSQ() const { return squashedInLSQ; }
564
565 /** Returns whether or not this instruction is in the LSQ. */
566 bool isInLSQ() const { return lsqEntry; }
567
568
569 //Reorder Buffer Functions
570 //-----------------------
571 /** Sets this instruction as a entry the ROB. */
572 void setInROB() { robEntry = true; }
573
574 /** Sets this instruction as a entry the ROB. */
575 void removeInROB() { robEntry = false; }
576
577 /** Sets this instruction as squashed in the ROB. */
578 void setSquashedInROB() { squashedInROB = true; }
579
580 /** Returns whether or not this instruction is squashed in the ROB. */
581 bool isSquashedInROB() const { return squashedInROB; }
582
583 /** Returns whether or not this instruction is in the ROB. */
584 bool isInROB() const { return robEntry; }
585
586 /** Read the PC of this instruction. */
587 const Addr readPC() const { return PC; }
588
589 /** Set the next PC of this instruction (its actual target). */
590 void setNextPC(uint64_t val)
591 {
592 nextPC = val;
593// instResult.integer = val;
594 }
595
596 void setASID(short addr_space_id) { asid = addr_space_id; }
597
598 void setThread(unsigned tid) { threadNumber = tid; }
599
600 void setState(ImplState *state) { thread = state; }
601
602 /** Returns the thread context.
603 */
604 ThreadContext *tcBase() { return thread->getTC(); }
605
606 private:
607 /** Instruction effective address.
608 * @todo: Consider if this is necessary or not.
609 */
610 Addr instEffAddr;
611
612 /** Whether or not the effective address calculation is completed.
613 * @todo: Consider if this is necessary or not.
614 */
615 bool eaCalcDone;
616
617 public:
618 /** Sets the effective address. */
619 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
620
621 /** Returns the effective address. */
622 const Addr &getEA() const { return instEffAddr; }
623
624 /** Returns whether or not the eff. addr. calculation has been completed. */
625 bool doneEACalc() { return eaCalcDone; }
626
627 /** Returns whether or not the eff. addr. source registers are ready. */
628 bool eaSrcsReady();
629
630 /** Whether or not the memory operation is done. */
631 bool memOpDone;
632
633 public:
634 /** Load queue index. */
635 int16_t lqIdx;
636
637 /** Store queue index. */
638 int16_t sqIdx;
639
640 bool reachedCommit;
641
642 /** Iterator pointing to this BaseDynInst in the list of all insts. */
643 ListIt instListIt;
644
645 /** Returns iterator to this instruction in the list of all insts. */
646 ListIt &getInstListIt() { return instListIt; }
647
648 /** Sets iterator for this instruction in the list of all insts. */
649 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
650};
651
652template<class Impl>
653template<class T>
654inline Fault
655BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
656{
|
667 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
668 TheISA::VMPageSize) {
669 return TheISA::genAlignmentFault();
670 }
671
672 fault = cpu->translateDataReadReq(req, thread);
673
674 if (fault == NoFault) {
675 effAddr = req->getVaddr();
676 physEffAddr = req->getPaddr();
677 memReqFlags = req->getFlags();
678
679#if 0
680 if (cpu->system->memctrl->badaddr(physEffAddr)) {
681 fault = TheISA::genMachineCheckFault();
682 data = (T)-1;
683 this->setExecuted();
684 } else {
685 fault = cpu->read(req, data, lqIdx);
686 }
687#else
688 fault = cpu->read(req, data, lqIdx);
689#endif
690 } else {
691 // Return a fixed value to keep simulation deterministic even
692 // along misspeculated paths.
693 data = (T)-1;
694
695 // Commit will have to clean up whatever happened. Set this
696 // instruction as executed.
697 this->setExecuted();
698 }
699
700 if (traceData) {
701 traceData->setAddr(addr);
702 traceData->setData(data);
703 }
704
705 return fault;
706}
707
708template<class Impl>
709template<class T>
710inline Fault
711BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
712{
713 if (traceData) {
714 traceData->setAddr(addr);
715 traceData->setData(data);
716 }
717
| 667 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
668 TheISA::VMPageSize) {
669 return TheISA::genAlignmentFault();
670 }
671
672 fault = cpu->translateDataReadReq(req, thread);
673
674 if (fault == NoFault) {
675 effAddr = req->getVaddr();
676 physEffAddr = req->getPaddr();
677 memReqFlags = req->getFlags();
678
679#if 0
680 if (cpu->system->memctrl->badaddr(physEffAddr)) {
681 fault = TheISA::genMachineCheckFault();
682 data = (T)-1;
683 this->setExecuted();
684 } else {
685 fault = cpu->read(req, data, lqIdx);
686 }
687#else
688 fault = cpu->read(req, data, lqIdx);
689#endif
690 } else {
691 // Return a fixed value to keep simulation deterministic even
692 // along misspeculated paths.
693 data = (T)-1;
694
695 // Commit will have to clean up whatever happened. Set this
696 // instruction as executed.
697 this->setExecuted();
698 }
699
700 if (traceData) {
701 traceData->setAddr(addr);
702 traceData->setData(data);
703 }
704
705 return fault;
706}
707
708template<class Impl>
709template<class T>
710inline Fault
711BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
712{
713 if (traceData) {
714 traceData->setAddr(addr);
715 traceData->setData(data);
716 }
717
|
718 req = new Request();
719 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
720 req->setThreadContext(thread->readCpuId(), threadNumber);
721
722 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
723 TheISA::VMPageSize) {
724 return TheISA::genAlignmentFault();
725 }
726
727 fault = cpu->translateDataWriteReq(req, thread);
728
729 if (fault == NoFault) {
730 effAddr = req->getVaddr();
731 physEffAddr = req->getPaddr();
732 memReqFlags = req->getFlags();
733#if 0
734 if (cpu->system->memctrl->badaddr(physEffAddr)) {
735 fault = TheISA::genMachineCheckFault();
736 } else {
737 fault = cpu->write(req, data, sqIdx);
738 }
739#else
740 fault = cpu->write(req, data, sqIdx);
741#endif
742 }
743
744 if (res) {
745 // always return some result to keep misspeculated paths
746 // (which will ignore faults) deterministic
747 *res = (fault == NoFault) ? req->getScResult() : 0;
748 }
749
750 return fault;
751}
752
753#endif // __CPU_BASE_DYN_INST_HH__
| 720 req = new Request();
721 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
722 req->setThreadContext(thread->readCpuId(), threadNumber);
723
724 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
725 TheISA::VMPageSize) {
726 return TheISA::genAlignmentFault();
727 }
728
729 fault = cpu->translateDataWriteReq(req, thread);
730
731 if (fault == NoFault) {
732 effAddr = req->getVaddr();
733 physEffAddr = req->getPaddr();
734 memReqFlags = req->getFlags();
735#if 0
736 if (cpu->system->memctrl->badaddr(physEffAddr)) {
737 fault = TheISA::genMachineCheckFault();
738 } else {
739 fault = cpu->write(req, data, sqIdx);
740 }
741#else
742 fault = cpu->write(req, data, sqIdx);
743#endif
744 }
745
746 if (res) {
747 // always return some result to keep misspeculated paths
748 // (which will ignore faults) deterministic
749 *res = (fault == NoFault) ? req->getScResult() : 0;
750 }
751
752 return fault;
753}
754
755#endif // __CPU_BASE_DYN_INST_HH__
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