1/*
2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76
77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80 public:
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84 using VecRegContainer = TheISA::VecRegContainer;
85
86 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
87 using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
88 using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 protected:
103 enum Status {
104 IqEntry, /// Instruction is in the IQ
105 RobEntry, /// Instruction is in the ROB
106 LsqEntry, /// Instruction is in the LSQ
107 Completed, /// Instruction has completed
108 ResultReady, /// Instruction has its result
109 CanIssue, /// Instruction can issue and execute
110 Issued, /// Instruction has issued
111 Executed, /// Instruction has executed
112 CanCommit, /// Instruction can commit
113 AtCommit, /// Instruction has reached commit
114 Committed, /// Instruction has committed
115 Squashed, /// Instruction is squashed
116 SquashedInIQ, /// Instruction is squashed in the IQ
117 SquashedInLSQ, /// Instruction is squashed in the LSQ
118 SquashedInROB, /// Instruction is squashed in the ROB
119 RecoverInst, /// Is a recover instruction
120 BlockingInst, /// Is a blocking instruction
121 ThreadsyncWait, /// Is a thread synchronization instruction
122 SerializeBefore, /// Needs to serialize on
123 /// instructions ahead of it
124 SerializeAfter, /// Needs to serialize instructions behind it
125 SerializeHandled, /// Serialization has been handled
126 NumStatus
127 };
128
129 enum Flags {
130 NotAnInst,
131 TranslationStarted,
132 TranslationCompleted,
133 PossibleLoadViolation,
134 HitExternalSnoop,
135 EffAddrValid,
136 RecordResult,
137 Predicate,
| 1/*
2 * Copyright (c) 2011, 2013, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76
77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80 public:
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84 using VecRegContainer = TheISA::VecRegContainer;
85
86 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
87 using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
88 using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 protected:
103 enum Status {
104 IqEntry, /// Instruction is in the IQ
105 RobEntry, /// Instruction is in the ROB
106 LsqEntry, /// Instruction is in the LSQ
107 Completed, /// Instruction has completed
108 ResultReady, /// Instruction has its result
109 CanIssue, /// Instruction can issue and execute
110 Issued, /// Instruction has issued
111 Executed, /// Instruction has executed
112 CanCommit, /// Instruction can commit
113 AtCommit, /// Instruction has reached commit
114 Committed, /// Instruction has committed
115 Squashed, /// Instruction is squashed
116 SquashedInIQ, /// Instruction is squashed in the IQ
117 SquashedInLSQ, /// Instruction is squashed in the LSQ
118 SquashedInROB, /// Instruction is squashed in the ROB
119 RecoverInst, /// Is a recover instruction
120 BlockingInst, /// Is a blocking instruction
121 ThreadsyncWait, /// Is a thread synchronization instruction
122 SerializeBefore, /// Needs to serialize on
123 /// instructions ahead of it
124 SerializeAfter, /// Needs to serialize instructions behind it
125 SerializeHandled, /// Serialization has been handled
126 NumStatus
127 };
128
129 enum Flags {
130 NotAnInst,
131 TranslationStarted,
132 TranslationCompleted,
133 PossibleLoadViolation,
134 HitExternalSnoop,
135 EffAddrValid,
136 RecordResult,
137 Predicate,
|
| 138 MemAccPredicate,
|
138 PredTaken,
139 IsStrictlyOrdered,
140 ReqMade,
141 MemOpDone,
142 MaxFlags
143 };
144
145 public:
146 /** The sequence number of the instruction. */
147 InstSeqNum seqNum;
148
149 /** The StaticInst used by this BaseDynInst. */
150 const StaticInstPtr staticInst;
151
152 /** Pointer to the Impl's CPU object. */
153 ImplCPU *cpu;
154
155 BaseCPU *getCpuPtr() { return cpu; }
156
157 /** Pointer to the thread state. */
158 ImplState *thread;
159
160 /** The kind of fault this instruction has generated. */
161 Fault fault;
162
163 /** InstRecord that tracks this instructions. */
164 Trace::InstRecord *traceData;
165
166 protected:
167 /** The result of the instruction; assumes an instruction can have many
168 * destination registers.
169 */
170 std::queue<InstResult> instResult;
171
172 /** PC state for this instruction. */
173 TheISA::PCState pc;
174
175 /* An amalgamation of a lot of boolean values into one */
176 std::bitset<MaxFlags> instFlags;
177
178 /** The status of this BaseDynInst. Several bits can be set. */
179 std::bitset<NumStatus> status;
180
181 /** Whether or not the source register is ready.
182 * @todo: Not sure this should be here vs the derived class.
183 */
184 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
185
186 public:
187 /** The thread this instruction is from. */
188 ThreadID threadNumber;
189
190 /** Iterator pointing to this BaseDynInst in the list of all insts. */
191 ListIt instListIt;
192
193 ////////////////////// Branch Data ///////////////
194 /** Predicted PC state after this instruction. */
195 TheISA::PCState predPC;
196
197 /** The Macroop if one exists */
198 const StaticInstPtr macroop;
199
200 /** How many source registers are ready. */
201 uint8_t readyRegs;
202
203 public:
204 /////////////////////// Load Store Data //////////////////////
205 /** The effective virtual address (lds & stores only). */
206 Addr effAddr;
207
208 /** The effective physical address. */
209 Addr physEffAddr;
210
211 /** The memory request flags (from translation). */
212 unsigned memReqFlags;
213
214 /** data address space ID, for loads & stores. */
215 short asid;
216
217 /** The size of the request */
218 uint8_t effSize;
219
220 /** Pointer to the data for the memory access. */
221 uint8_t *memData;
222
223 /** Load queue index. */
224 int16_t lqIdx;
225 LQIterator lqIt;
226
227 /** Store queue index. */
228 int16_t sqIdx;
229 SQIterator sqIt;
230
231
232 /////////////////////// TLB Miss //////////////////////
233 /**
234 * Saved memory request (needed when the DTB address translation is
235 * delayed due to a hw page table walk).
236 */
237 LSQRequestPtr savedReq;
238
239 /////////////////////// Checker //////////////////////
240 // Need a copy of main request pointer to verify on writes.
241 RequestPtr reqToVerify;
242
243 protected:
244 /** Flattened register index of the destination registers of this
245 * instruction.
246 */
247 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
248
249 /** Physical register index of the destination registers of this
250 * instruction.
251 */
252 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
253
254 /** Physical register index of the source registers of this
255 * instruction.
256 */
257 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
258
259 /** Physical register index of the previous producers of the
260 * architected destinations.
261 */
262 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
263
264
265 public:
266 /** Records changes to result? */
267 void recordResult(bool f) { instFlags[RecordResult] = f; }
268
269 /** Is the effective virtual address valid. */
270 bool effAddrValid() const { return instFlags[EffAddrValid]; }
271 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
272
273 /** Whether or not the memory operation is done. */
274 bool memOpDone() const { return instFlags[MemOpDone]; }
275 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
276
277 bool notAnInst() const { return instFlags[NotAnInst]; }
278 void setNotAnInst() { instFlags[NotAnInst] = true; }
279
280
281 ////////////////////////////////////////////
282 //
283 // INSTRUCTION EXECUTION
284 //
285 ////////////////////////////////////////////
286
287 void demapPage(Addr vaddr, uint64_t asn)
288 {
289 cpu->demapPage(vaddr, asn);
290 }
291 void demapInstPage(Addr vaddr, uint64_t asn)
292 {
293 cpu->demapPage(vaddr, asn);
294 }
295 void demapDataPage(Addr vaddr, uint64_t asn)
296 {
297 cpu->demapPage(vaddr, asn);
298 }
299
300 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
301
302 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
303 Request::Flags flags, uint64_t *res);
304
305 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
306 AtomicOpFunctor *amo_op);
307
308 /** True if the DTB address translation has started. */
309 bool translationStarted() const { return instFlags[TranslationStarted]; }
310 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
311
312 /** True if the DTB address translation has completed. */
313 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
314 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
315
316 /** True if this address was found to match a previous load and they issued
317 * out of order. If that happend, then it's only a problem if an incoming
318 * snoop invalidate modifies the line, in which case we need to squash.
319 * If nothing modified the line the order doesn't matter.
320 */
321 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
322 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
323
324 /** True if the address hit a external snoop while sitting in the LSQ.
325 * If this is true and a older instruction sees it, this instruction must
326 * reexecute
327 */
328 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
329 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
330
331 /**
332 * Returns true if the DTB address translation is being delayed due to a hw
333 * page table walk.
334 */
335 bool isTranslationDelayed() const
336 {
337 return (translationStarted() && !translationCompleted());
338 }
339
340 public:
341#ifdef DEBUG
342 void dumpSNList();
343#endif
344
345 /** Returns the physical register index of the i'th destination
346 * register.
347 */
348 PhysRegIdPtr renamedDestRegIdx(int idx) const
349 {
350 return _destRegIdx[idx];
351 }
352
353 /** Returns the physical register index of the i'th source register. */
354 PhysRegIdPtr renamedSrcRegIdx(int idx) const
355 {
356 assert(TheISA::MaxInstSrcRegs > idx);
357 return _srcRegIdx[idx];
358 }
359
360 /** Returns the flattened register index of the i'th destination
361 * register.
362 */
363 const RegId& flattenedDestRegIdx(int idx) const
364 {
365 return _flatDestRegIdx[idx];
366 }
367
368 /** Returns the physical register index of the previous physical register
369 * that remapped to the same logical register index.
370 */
371 PhysRegIdPtr prevDestRegIdx(int idx) const
372 {
373 return _prevDestRegIdx[idx];
374 }
375
376 /** Renames a destination register to a physical register. Also records
377 * the previous physical register that the logical register mapped to.
378 */
379 void renameDestReg(int idx,
380 PhysRegIdPtr renamed_dest,
381 PhysRegIdPtr previous_rename)
382 {
383 _destRegIdx[idx] = renamed_dest;
384 _prevDestRegIdx[idx] = previous_rename;
385 }
386
387 /** Renames a source logical register to the physical register which
388 * has/will produce that logical register's result.
389 * @todo: add in whether or not the source register is ready.
390 */
391 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
392 {
393 _srcRegIdx[idx] = renamed_src;
394 }
395
396 /** Flattens a destination architectural register index into a logical
397 * index.
398 */
399 void flattenDestReg(int idx, const RegId& flattened_dest)
400 {
401 _flatDestRegIdx[idx] = flattened_dest;
402 }
403 /** BaseDynInst constructor given a binary instruction.
404 * @param staticInst A StaticInstPtr to the underlying instruction.
405 * @param pc The PC state for the instruction.
406 * @param predPC The predicted next PC state for the instruction.
407 * @param seq_num The sequence number of the instruction.
408 * @param cpu Pointer to the instruction's CPU.
409 */
410 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
411 TheISA::PCState pc, TheISA::PCState predPC,
412 InstSeqNum seq_num, ImplCPU *cpu);
413
414 /** BaseDynInst constructor given a StaticInst pointer.
415 * @param _staticInst The StaticInst for this BaseDynInst.
416 */
417 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
418
419 /** BaseDynInst destructor. */
420 ~BaseDynInst();
421
422 private:
423 /** Function to initialize variables in the constructors. */
424 void initVars();
425
426 public:
427 /** Dumps out contents of this BaseDynInst. */
428 void dump();
429
430 /** Dumps out contents of this BaseDynInst into given string. */
431 void dump(std::string &outstring);
432
433 /** Read this CPU's ID. */
434 int cpuId() const { return cpu->cpuId(); }
435
436 /** Read this CPU's Socket ID. */
437 uint32_t socketId() const { return cpu->socketId(); }
438
439 /** Read this CPU's data requestor ID */
440 MasterID masterId() const { return cpu->dataMasterId(); }
441
442 /** Read this context's system-wide ID **/
443 ContextID contextId() const { return thread->contextId(); }
444
445 /** Returns the fault type. */
446 Fault getFault() const { return fault; }
447 /** TODO: This I added for the LSQRequest side to be able to modify the
448 * fault. There should be a better mechanism in place. */
449 Fault& getFault() { return fault; }
450
451 /** Checks whether or not this instruction has had its branch target
452 * calculated yet. For now it is not utilized and is hacked to be
453 * always false.
454 * @todo: Actually use this instruction.
455 */
456 bool doneTargCalc() { return false; }
457
458 /** Set the predicted target of this current instruction. */
459 void setPredTarg(const TheISA::PCState &_predPC)
460 {
461 predPC = _predPC;
462 }
463
464 const TheISA::PCState &readPredTarg() { return predPC; }
465
466 /** Returns the predicted PC immediately after the branch. */
467 Addr predInstAddr() { return predPC.instAddr(); }
468
469 /** Returns the predicted PC two instructions after the branch */
470 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
471
472 /** Returns the predicted micro PC after the branch */
473 Addr predMicroPC() { return predPC.microPC(); }
474
475 /** Returns whether the instruction was predicted taken or not. */
476 bool readPredTaken()
477 {
478 return instFlags[PredTaken];
479 }
480
481 void setPredTaken(bool predicted_taken)
482 {
483 instFlags[PredTaken] = predicted_taken;
484 }
485
486 /** Returns whether the instruction mispredicted. */
487 bool mispredicted()
488 {
489 TheISA::PCState tempPC = pc;
490 TheISA::advancePC(tempPC, staticInst);
491 return !(tempPC == predPC);
492 }
493
494 //
495 // Instruction types. Forward checks to StaticInst object.
496 //
497 bool isNop() const { return staticInst->isNop(); }
498 bool isMemRef() const { return staticInst->isMemRef(); }
499 bool isLoad() const { return staticInst->isLoad(); }
500 bool isStore() const { return staticInst->isStore(); }
501 bool isAtomic() const { return staticInst->isAtomic(); }
502 bool isStoreConditional() const
503 { return staticInst->isStoreConditional(); }
504 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
505 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
506 bool isInteger() const { return staticInst->isInteger(); }
507 bool isFloating() const { return staticInst->isFloating(); }
508 bool isVector() const { return staticInst->isVector(); }
509 bool isControl() const { return staticInst->isControl(); }
510 bool isCall() const { return staticInst->isCall(); }
511 bool isReturn() const { return staticInst->isReturn(); }
512 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
513 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
514 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
515 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
516 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
517 bool isThreadSync() const { return staticInst->isThreadSync(); }
518 bool isSerializing() const { return staticInst->isSerializing(); }
519 bool isSerializeBefore() const
520 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
521 bool isSerializeAfter() const
522 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
523 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
524 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
525 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
526 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
527 bool isQuiesce() const { return staticInst->isQuiesce(); }
528 bool isIprAccess() const { return staticInst->isIprAccess(); }
529 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
530 bool isSyscall() const { return staticInst->isSyscall(); }
531 bool isMacroop() const { return staticInst->isMacroop(); }
532 bool isMicroop() const { return staticInst->isMicroop(); }
533 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
534 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
535 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
536 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
537
538 /** Temporarily sets this instruction as a serialize before instruction. */
539 void setSerializeBefore() { status.set(SerializeBefore); }
540
541 /** Clears the serializeBefore part of this instruction. */
542 void clearSerializeBefore() { status.reset(SerializeBefore); }
543
544 /** Checks if this serializeBefore is only temporarily set. */
545 bool isTempSerializeBefore() { return status[SerializeBefore]; }
546
547 /** Temporarily sets this instruction as a serialize after instruction. */
548 void setSerializeAfter() { status.set(SerializeAfter); }
549
550 /** Clears the serializeAfter part of this instruction.*/
551 void clearSerializeAfter() { status.reset(SerializeAfter); }
552
553 /** Checks if this serializeAfter is only temporarily set. */
554 bool isTempSerializeAfter() { return status[SerializeAfter]; }
555
556 /** Sets the serialization part of this instruction as handled. */
557 void setSerializeHandled() { status.set(SerializeHandled); }
558
559 /** Checks if the serialization part of this instruction has been
560 * handled. This does not apply to the temporary serializing
561 * state; it only applies to this instruction's own permanent
562 * serializing state.
563 */
564 bool isSerializeHandled() { return status[SerializeHandled]; }
565
566 /** Returns the opclass of this instruction. */
567 OpClass opClass() const { return staticInst->opClass(); }
568
569 /** Returns the branch target address. */
570 TheISA::PCState branchTarget() const
571 { return staticInst->branchTarget(pc); }
572
573 /** Returns the number of source registers. */
574 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
575
576 /** Returns the number of destination registers. */
577 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
578
579 // the following are used to track physical register usage
580 // for machines with separate int & FP reg files
581 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
582 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
583 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
584 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
585 int8_t numVecElemDestRegs() const
586 {
587 return staticInst->numVecElemDestRegs();
588 }
589 int8_t
590 numVecPredDestRegs() const
591 {
592 return staticInst->numVecPredDestRegs();
593 }
594
595 /** Returns the logical register index of the i'th destination register. */
596 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
597
598 /** Returns the logical register index of the i'th source register. */
599 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
600
601 /** Return the size of the instResult queue. */
602 uint8_t resultSize() { return instResult.size(); }
603
604 /** Pops a result off the instResult queue.
605 * If the result stack is empty, return the default value.
606 * */
607 InstResult popResult(InstResult dflt = InstResult())
608 {
609 if (!instResult.empty()) {
610 InstResult t = instResult.front();
611 instResult.pop();
612 return t;
613 }
614 return dflt;
615 }
616
617 /** Pushes a result onto the instResult queue. */
618 /** @{ */
619 /** Scalar result. */
620 template<typename T>
621 void setScalarResult(T&& t)
622 {
623 if (instFlags[RecordResult]) {
624 instResult.push(InstResult(std::forward<T>(t),
625 InstResult::ResultType::Scalar));
626 }
627 }
628
629 /** Full vector result. */
630 template<typename T>
631 void setVecResult(T&& t)
632 {
633 if (instFlags[RecordResult]) {
634 instResult.push(InstResult(std::forward<T>(t),
635 InstResult::ResultType::VecReg));
636 }
637 }
638
639 /** Vector element result. */
640 template<typename T>
641 void setVecElemResult(T&& t)
642 {
643 if (instFlags[RecordResult]) {
644 instResult.push(InstResult(std::forward<T>(t),
645 InstResult::ResultType::VecElem));
646 }
647 }
648
649 /** Predicate result. */
650 template<typename T>
651 void setVecPredResult(T&& t)
652 {
653 if (instFlags[RecordResult]) {
654 instResult.push(InstResult(std::forward<T>(t),
655 InstResult::ResultType::VecPredReg));
656 }
657 }
658 /** @} */
659
660 /** Records an integer register being set to a value. */
661 void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
662 {
663 setScalarResult(val);
664 }
665
666 /** Records a CC register being set to a value. */
667 void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
668 {
669 setScalarResult(val);
670 }
671
672 /** Record a vector register being set to a value */
673 void setVecRegOperand(const StaticInst *si, int idx,
674 const VecRegContainer& val)
675 {
676 setVecResult(val);
677 }
678
679 /** Records an fp register being set to an integer value. */
680 void
681 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
682 {
683 setScalarResult(val);
684 }
685
686 /** Record a vector register being set to a value */
687 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
688 {
689 setVecElemResult(val);
690 }
691
692 /** Record a vector register being set to a value */
693 void setVecPredRegOperand(const StaticInst *si, int idx,
694 const VecPredRegContainer& val)
695 {
696 setVecPredResult(val);
697 }
698
699 /** Records that one of the source registers is ready. */
700 void markSrcRegReady();
701
702 /** Marks a specific register as ready. */
703 void markSrcRegReady(RegIndex src_idx);
704
705 /** Returns if a source register is ready. */
706 bool isReadySrcRegIdx(int idx) const
707 {
708 return this->_readySrcRegIdx[idx];
709 }
710
711 /** Sets this instruction as completed. */
712 void setCompleted() { status.set(Completed); }
713
714 /** Returns whether or not this instruction is completed. */
715 bool isCompleted() const { return status[Completed]; }
716
717 /** Marks the result as ready. */
718 void setResultReady() { status.set(ResultReady); }
719
720 /** Returns whether or not the result is ready. */
721 bool isResultReady() const { return status[ResultReady]; }
722
723 /** Sets this instruction as ready to issue. */
724 void setCanIssue() { status.set(CanIssue); }
725
726 /** Returns whether or not this instruction is ready to issue. */
727 bool readyToIssue() const { return status[CanIssue]; }
728
729 /** Clears this instruction being able to issue. */
730 void clearCanIssue() { status.reset(CanIssue); }
731
732 /** Sets this instruction as issued from the IQ. */
733 void setIssued() { status.set(Issued); }
734
735 /** Returns whether or not this instruction has issued. */
736 bool isIssued() const { return status[Issued]; }
737
738 /** Clears this instruction as being issued. */
739 void clearIssued() { status.reset(Issued); }
740
741 /** Sets this instruction as executed. */
742 void setExecuted() { status.set(Executed); }
743
744 /** Returns whether or not this instruction has executed. */
745 bool isExecuted() const { return status[Executed]; }
746
747 /** Sets this instruction as ready to commit. */
748 void setCanCommit() { status.set(CanCommit); }
749
750 /** Clears this instruction as being ready to commit. */
751 void clearCanCommit() { status.reset(CanCommit); }
752
753 /** Returns whether or not this instruction is ready to commit. */
754 bool readyToCommit() const { return status[CanCommit]; }
755
756 void setAtCommit() { status.set(AtCommit); }
757
758 bool isAtCommit() { return status[AtCommit]; }
759
760 /** Sets this instruction as committed. */
761 void setCommitted() { status.set(Committed); }
762
763 /** Returns whether or not this instruction is committed. */
764 bool isCommitted() const { return status[Committed]; }
765
766 /** Sets this instruction as squashed. */
767 void setSquashed() { status.set(Squashed); }
768
769 /** Returns whether or not this instruction is squashed. */
770 bool isSquashed() const { return status[Squashed]; }
771
772 //Instruction Queue Entry
773 //-----------------------
774 /** Sets this instruction as a entry the IQ. */
775 void setInIQ() { status.set(IqEntry); }
776
777 /** Sets this instruction as a entry the IQ. */
778 void clearInIQ() { status.reset(IqEntry); }
779
780 /** Returns whether or not this instruction has issued. */
781 bool isInIQ() const { return status[IqEntry]; }
782
783 /** Sets this instruction as squashed in the IQ. */
784 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
785
786 /** Returns whether or not this instruction is squashed in the IQ. */
787 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
788
789
790 //Load / Store Queue Functions
791 //-----------------------
792 /** Sets this instruction as a entry the LSQ. */
793 void setInLSQ() { status.set(LsqEntry); }
794
795 /** Sets this instruction as a entry the LSQ. */
796 void removeInLSQ() { status.reset(LsqEntry); }
797
798 /** Returns whether or not this instruction is in the LSQ. */
799 bool isInLSQ() const { return status[LsqEntry]; }
800
801 /** Sets this instruction as squashed in the LSQ. */
802 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
803
804 /** Returns whether or not this instruction is squashed in the LSQ. */
805 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
806
807
808 //Reorder Buffer Functions
809 //-----------------------
810 /** Sets this instruction as a entry the ROB. */
811 void setInROB() { status.set(RobEntry); }
812
813 /** Sets this instruction as a entry the ROB. */
814 void clearInROB() { status.reset(RobEntry); }
815
816 /** Returns whether or not this instruction is in the ROB. */
817 bool isInROB() const { return status[RobEntry]; }
818
819 /** Sets this instruction as squashed in the ROB. */
820 void setSquashedInROB() { status.set(SquashedInROB); }
821
822 /** Returns whether or not this instruction is squashed in the ROB. */
823 bool isSquashedInROB() const { return status[SquashedInROB]; }
824
825 /** Read the PC state of this instruction. */
826 TheISA::PCState pcState() const { return pc; }
827
828 /** Set the PC state of this instruction. */
829 void pcState(const TheISA::PCState &val) { pc = val; }
830
831 /** Read the PC of this instruction. */
832 Addr instAddr() const { return pc.instAddr(); }
833
834 /** Read the PC of the next instruction. */
835 Addr nextInstAddr() const { return pc.nextInstAddr(); }
836
837 /**Read the micro PC of this instruction. */
838 Addr microPC() const { return pc.microPC(); }
839
840 bool readPredicate() const
841 {
842 return instFlags[Predicate];
843 }
844
845 void setPredicate(bool val)
846 {
847 instFlags[Predicate] = val;
848
849 if (traceData) {
850 traceData->setPredicate(val);
851 }
852 }
853
| 139 PredTaken,
140 IsStrictlyOrdered,
141 ReqMade,
142 MemOpDone,
143 MaxFlags
144 };
145
146 public:
147 /** The sequence number of the instruction. */
148 InstSeqNum seqNum;
149
150 /** The StaticInst used by this BaseDynInst. */
151 const StaticInstPtr staticInst;
152
153 /** Pointer to the Impl's CPU object. */
154 ImplCPU *cpu;
155
156 BaseCPU *getCpuPtr() { return cpu; }
157
158 /** Pointer to the thread state. */
159 ImplState *thread;
160
161 /** The kind of fault this instruction has generated. */
162 Fault fault;
163
164 /** InstRecord that tracks this instructions. */
165 Trace::InstRecord *traceData;
166
167 protected:
168 /** The result of the instruction; assumes an instruction can have many
169 * destination registers.
170 */
171 std::queue<InstResult> instResult;
172
173 /** PC state for this instruction. */
174 TheISA::PCState pc;
175
176 /* An amalgamation of a lot of boolean values into one */
177 std::bitset<MaxFlags> instFlags;
178
179 /** The status of this BaseDynInst. Several bits can be set. */
180 std::bitset<NumStatus> status;
181
182 /** Whether or not the source register is ready.
183 * @todo: Not sure this should be here vs the derived class.
184 */
185 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
186
187 public:
188 /** The thread this instruction is from. */
189 ThreadID threadNumber;
190
191 /** Iterator pointing to this BaseDynInst in the list of all insts. */
192 ListIt instListIt;
193
194 ////////////////////// Branch Data ///////////////
195 /** Predicted PC state after this instruction. */
196 TheISA::PCState predPC;
197
198 /** The Macroop if one exists */
199 const StaticInstPtr macroop;
200
201 /** How many source registers are ready. */
202 uint8_t readyRegs;
203
204 public:
205 /////////////////////// Load Store Data //////////////////////
206 /** The effective virtual address (lds & stores only). */
207 Addr effAddr;
208
209 /** The effective physical address. */
210 Addr physEffAddr;
211
212 /** The memory request flags (from translation). */
213 unsigned memReqFlags;
214
215 /** data address space ID, for loads & stores. */
216 short asid;
217
218 /** The size of the request */
219 uint8_t effSize;
220
221 /** Pointer to the data for the memory access. */
222 uint8_t *memData;
223
224 /** Load queue index. */
225 int16_t lqIdx;
226 LQIterator lqIt;
227
228 /** Store queue index. */
229 int16_t sqIdx;
230 SQIterator sqIt;
231
232
233 /////////////////////// TLB Miss //////////////////////
234 /**
235 * Saved memory request (needed when the DTB address translation is
236 * delayed due to a hw page table walk).
237 */
238 LSQRequestPtr savedReq;
239
240 /////////////////////// Checker //////////////////////
241 // Need a copy of main request pointer to verify on writes.
242 RequestPtr reqToVerify;
243
244 protected:
245 /** Flattened register index of the destination registers of this
246 * instruction.
247 */
248 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
249
250 /** Physical register index of the destination registers of this
251 * instruction.
252 */
253 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
254
255 /** Physical register index of the source registers of this
256 * instruction.
257 */
258 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
259
260 /** Physical register index of the previous producers of the
261 * architected destinations.
262 */
263 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
264
265
266 public:
267 /** Records changes to result? */
268 void recordResult(bool f) { instFlags[RecordResult] = f; }
269
270 /** Is the effective virtual address valid. */
271 bool effAddrValid() const { return instFlags[EffAddrValid]; }
272 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
273
274 /** Whether or not the memory operation is done. */
275 bool memOpDone() const { return instFlags[MemOpDone]; }
276 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
277
278 bool notAnInst() const { return instFlags[NotAnInst]; }
279 void setNotAnInst() { instFlags[NotAnInst] = true; }
280
281
282 ////////////////////////////////////////////
283 //
284 // INSTRUCTION EXECUTION
285 //
286 ////////////////////////////////////////////
287
288 void demapPage(Addr vaddr, uint64_t asn)
289 {
290 cpu->demapPage(vaddr, asn);
291 }
292 void demapInstPage(Addr vaddr, uint64_t asn)
293 {
294 cpu->demapPage(vaddr, asn);
295 }
296 void demapDataPage(Addr vaddr, uint64_t asn)
297 {
298 cpu->demapPage(vaddr, asn);
299 }
300
301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302
303 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
304 Request::Flags flags, uint64_t *res);
305
306 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
307 AtomicOpFunctor *amo_op);
308
309 /** True if the DTB address translation has started. */
310 bool translationStarted() const { return instFlags[TranslationStarted]; }
311 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
312
313 /** True if the DTB address translation has completed. */
314 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
315 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
316
317 /** True if this address was found to match a previous load and they issued
318 * out of order. If that happend, then it's only a problem if an incoming
319 * snoop invalidate modifies the line, in which case we need to squash.
320 * If nothing modified the line the order doesn't matter.
321 */
322 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
323 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
324
325 /** True if the address hit a external snoop while sitting in the LSQ.
326 * If this is true and a older instruction sees it, this instruction must
327 * reexecute
328 */
329 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
330 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
331
332 /**
333 * Returns true if the DTB address translation is being delayed due to a hw
334 * page table walk.
335 */
336 bool isTranslationDelayed() const
337 {
338 return (translationStarted() && !translationCompleted());
339 }
340
341 public:
342#ifdef DEBUG
343 void dumpSNList();
344#endif
345
346 /** Returns the physical register index of the i'th destination
347 * register.
348 */
349 PhysRegIdPtr renamedDestRegIdx(int idx) const
350 {
351 return _destRegIdx[idx];
352 }
353
354 /** Returns the physical register index of the i'th source register. */
355 PhysRegIdPtr renamedSrcRegIdx(int idx) const
356 {
357 assert(TheISA::MaxInstSrcRegs > idx);
358 return _srcRegIdx[idx];
359 }
360
361 /** Returns the flattened register index of the i'th destination
362 * register.
363 */
364 const RegId& flattenedDestRegIdx(int idx) const
365 {
366 return _flatDestRegIdx[idx];
367 }
368
369 /** Returns the physical register index of the previous physical register
370 * that remapped to the same logical register index.
371 */
372 PhysRegIdPtr prevDestRegIdx(int idx) const
373 {
374 return _prevDestRegIdx[idx];
375 }
376
377 /** Renames a destination register to a physical register. Also records
378 * the previous physical register that the logical register mapped to.
379 */
380 void renameDestReg(int idx,
381 PhysRegIdPtr renamed_dest,
382 PhysRegIdPtr previous_rename)
383 {
384 _destRegIdx[idx] = renamed_dest;
385 _prevDestRegIdx[idx] = previous_rename;
386 }
387
388 /** Renames a source logical register to the physical register which
389 * has/will produce that logical register's result.
390 * @todo: add in whether or not the source register is ready.
391 */
392 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
393 {
394 _srcRegIdx[idx] = renamed_src;
395 }
396
397 /** Flattens a destination architectural register index into a logical
398 * index.
399 */
400 void flattenDestReg(int idx, const RegId& flattened_dest)
401 {
402 _flatDestRegIdx[idx] = flattened_dest;
403 }
404 /** BaseDynInst constructor given a binary instruction.
405 * @param staticInst A StaticInstPtr to the underlying instruction.
406 * @param pc The PC state for the instruction.
407 * @param predPC The predicted next PC state for the instruction.
408 * @param seq_num The sequence number of the instruction.
409 * @param cpu Pointer to the instruction's CPU.
410 */
411 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
412 TheISA::PCState pc, TheISA::PCState predPC,
413 InstSeqNum seq_num, ImplCPU *cpu);
414
415 /** BaseDynInst constructor given a StaticInst pointer.
416 * @param _staticInst The StaticInst for this BaseDynInst.
417 */
418 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
419
420 /** BaseDynInst destructor. */
421 ~BaseDynInst();
422
423 private:
424 /** Function to initialize variables in the constructors. */
425 void initVars();
426
427 public:
428 /** Dumps out contents of this BaseDynInst. */
429 void dump();
430
431 /** Dumps out contents of this BaseDynInst into given string. */
432 void dump(std::string &outstring);
433
434 /** Read this CPU's ID. */
435 int cpuId() const { return cpu->cpuId(); }
436
437 /** Read this CPU's Socket ID. */
438 uint32_t socketId() const { return cpu->socketId(); }
439
440 /** Read this CPU's data requestor ID */
441 MasterID masterId() const { return cpu->dataMasterId(); }
442
443 /** Read this context's system-wide ID **/
444 ContextID contextId() const { return thread->contextId(); }
445
446 /** Returns the fault type. */
447 Fault getFault() const { return fault; }
448 /** TODO: This I added for the LSQRequest side to be able to modify the
449 * fault. There should be a better mechanism in place. */
450 Fault& getFault() { return fault; }
451
452 /** Checks whether or not this instruction has had its branch target
453 * calculated yet. For now it is not utilized and is hacked to be
454 * always false.
455 * @todo: Actually use this instruction.
456 */
457 bool doneTargCalc() { return false; }
458
459 /** Set the predicted target of this current instruction. */
460 void setPredTarg(const TheISA::PCState &_predPC)
461 {
462 predPC = _predPC;
463 }
464
465 const TheISA::PCState &readPredTarg() { return predPC; }
466
467 /** Returns the predicted PC immediately after the branch. */
468 Addr predInstAddr() { return predPC.instAddr(); }
469
470 /** Returns the predicted PC two instructions after the branch */
471 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
472
473 /** Returns the predicted micro PC after the branch */
474 Addr predMicroPC() { return predPC.microPC(); }
475
476 /** Returns whether the instruction was predicted taken or not. */
477 bool readPredTaken()
478 {
479 return instFlags[PredTaken];
480 }
481
482 void setPredTaken(bool predicted_taken)
483 {
484 instFlags[PredTaken] = predicted_taken;
485 }
486
487 /** Returns whether the instruction mispredicted. */
488 bool mispredicted()
489 {
490 TheISA::PCState tempPC = pc;
491 TheISA::advancePC(tempPC, staticInst);
492 return !(tempPC == predPC);
493 }
494
495 //
496 // Instruction types. Forward checks to StaticInst object.
497 //
498 bool isNop() const { return staticInst->isNop(); }
499 bool isMemRef() const { return staticInst->isMemRef(); }
500 bool isLoad() const { return staticInst->isLoad(); }
501 bool isStore() const { return staticInst->isStore(); }
502 bool isAtomic() const { return staticInst->isAtomic(); }
503 bool isStoreConditional() const
504 { return staticInst->isStoreConditional(); }
505 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
506 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
507 bool isInteger() const { return staticInst->isInteger(); }
508 bool isFloating() const { return staticInst->isFloating(); }
509 bool isVector() const { return staticInst->isVector(); }
510 bool isControl() const { return staticInst->isControl(); }
511 bool isCall() const { return staticInst->isCall(); }
512 bool isReturn() const { return staticInst->isReturn(); }
513 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
514 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
515 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
516 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
517 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
518 bool isThreadSync() const { return staticInst->isThreadSync(); }
519 bool isSerializing() const { return staticInst->isSerializing(); }
520 bool isSerializeBefore() const
521 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
522 bool isSerializeAfter() const
523 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
524 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
525 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
526 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
527 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
528 bool isQuiesce() const { return staticInst->isQuiesce(); }
529 bool isIprAccess() const { return staticInst->isIprAccess(); }
530 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
531 bool isSyscall() const { return staticInst->isSyscall(); }
532 bool isMacroop() const { return staticInst->isMacroop(); }
533 bool isMicroop() const { return staticInst->isMicroop(); }
534 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
535 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
536 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
537 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
538
539 /** Temporarily sets this instruction as a serialize before instruction. */
540 void setSerializeBefore() { status.set(SerializeBefore); }
541
542 /** Clears the serializeBefore part of this instruction. */
543 void clearSerializeBefore() { status.reset(SerializeBefore); }
544
545 /** Checks if this serializeBefore is only temporarily set. */
546 bool isTempSerializeBefore() { return status[SerializeBefore]; }
547
548 /** Temporarily sets this instruction as a serialize after instruction. */
549 void setSerializeAfter() { status.set(SerializeAfter); }
550
551 /** Clears the serializeAfter part of this instruction.*/
552 void clearSerializeAfter() { status.reset(SerializeAfter); }
553
554 /** Checks if this serializeAfter is only temporarily set. */
555 bool isTempSerializeAfter() { return status[SerializeAfter]; }
556
557 /** Sets the serialization part of this instruction as handled. */
558 void setSerializeHandled() { status.set(SerializeHandled); }
559
560 /** Checks if the serialization part of this instruction has been
561 * handled. This does not apply to the temporary serializing
562 * state; it only applies to this instruction's own permanent
563 * serializing state.
564 */
565 bool isSerializeHandled() { return status[SerializeHandled]; }
566
567 /** Returns the opclass of this instruction. */
568 OpClass opClass() const { return staticInst->opClass(); }
569
570 /** Returns the branch target address. */
571 TheISA::PCState branchTarget() const
572 { return staticInst->branchTarget(pc); }
573
574 /** Returns the number of source registers. */
575 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
576
577 /** Returns the number of destination registers. */
578 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
579
580 // the following are used to track physical register usage
581 // for machines with separate int & FP reg files
582 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
583 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
584 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
585 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
586 int8_t numVecElemDestRegs() const
587 {
588 return staticInst->numVecElemDestRegs();
589 }
590 int8_t
591 numVecPredDestRegs() const
592 {
593 return staticInst->numVecPredDestRegs();
594 }
595
596 /** Returns the logical register index of the i'th destination register. */
597 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
598
599 /** Returns the logical register index of the i'th source register. */
600 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
601
602 /** Return the size of the instResult queue. */
603 uint8_t resultSize() { return instResult.size(); }
604
605 /** Pops a result off the instResult queue.
606 * If the result stack is empty, return the default value.
607 * */
608 InstResult popResult(InstResult dflt = InstResult())
609 {
610 if (!instResult.empty()) {
611 InstResult t = instResult.front();
612 instResult.pop();
613 return t;
614 }
615 return dflt;
616 }
617
618 /** Pushes a result onto the instResult queue. */
619 /** @{ */
620 /** Scalar result. */
621 template<typename T>
622 void setScalarResult(T&& t)
623 {
624 if (instFlags[RecordResult]) {
625 instResult.push(InstResult(std::forward<T>(t),
626 InstResult::ResultType::Scalar));
627 }
628 }
629
630 /** Full vector result. */
631 template<typename T>
632 void setVecResult(T&& t)
633 {
634 if (instFlags[RecordResult]) {
635 instResult.push(InstResult(std::forward<T>(t),
636 InstResult::ResultType::VecReg));
637 }
638 }
639
640 /** Vector element result. */
641 template<typename T>
642 void setVecElemResult(T&& t)
643 {
644 if (instFlags[RecordResult]) {
645 instResult.push(InstResult(std::forward<T>(t),
646 InstResult::ResultType::VecElem));
647 }
648 }
649
650 /** Predicate result. */
651 template<typename T>
652 void setVecPredResult(T&& t)
653 {
654 if (instFlags[RecordResult]) {
655 instResult.push(InstResult(std::forward<T>(t),
656 InstResult::ResultType::VecPredReg));
657 }
658 }
659 /** @} */
660
661 /** Records an integer register being set to a value. */
662 void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
663 {
664 setScalarResult(val);
665 }
666
667 /** Records a CC register being set to a value. */
668 void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
669 {
670 setScalarResult(val);
671 }
672
673 /** Record a vector register being set to a value */
674 void setVecRegOperand(const StaticInst *si, int idx,
675 const VecRegContainer& val)
676 {
677 setVecResult(val);
678 }
679
680 /** Records an fp register being set to an integer value. */
681 void
682 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
683 {
684 setScalarResult(val);
685 }
686
687 /** Record a vector register being set to a value */
688 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
689 {
690 setVecElemResult(val);
691 }
692
693 /** Record a vector register being set to a value */
694 void setVecPredRegOperand(const StaticInst *si, int idx,
695 const VecPredRegContainer& val)
696 {
697 setVecPredResult(val);
698 }
699
700 /** Records that one of the source registers is ready. */
701 void markSrcRegReady();
702
703 /** Marks a specific register as ready. */
704 void markSrcRegReady(RegIndex src_idx);
705
706 /** Returns if a source register is ready. */
707 bool isReadySrcRegIdx(int idx) const
708 {
709 return this->_readySrcRegIdx[idx];
710 }
711
712 /** Sets this instruction as completed. */
713 void setCompleted() { status.set(Completed); }
714
715 /** Returns whether or not this instruction is completed. */
716 bool isCompleted() const { return status[Completed]; }
717
718 /** Marks the result as ready. */
719 void setResultReady() { status.set(ResultReady); }
720
721 /** Returns whether or not the result is ready. */
722 bool isResultReady() const { return status[ResultReady]; }
723
724 /** Sets this instruction as ready to issue. */
725 void setCanIssue() { status.set(CanIssue); }
726
727 /** Returns whether or not this instruction is ready to issue. */
728 bool readyToIssue() const { return status[CanIssue]; }
729
730 /** Clears this instruction being able to issue. */
731 void clearCanIssue() { status.reset(CanIssue); }
732
733 /** Sets this instruction as issued from the IQ. */
734 void setIssued() { status.set(Issued); }
735
736 /** Returns whether or not this instruction has issued. */
737 bool isIssued() const { return status[Issued]; }
738
739 /** Clears this instruction as being issued. */
740 void clearIssued() { status.reset(Issued); }
741
742 /** Sets this instruction as executed. */
743 void setExecuted() { status.set(Executed); }
744
745 /** Returns whether or not this instruction has executed. */
746 bool isExecuted() const { return status[Executed]; }
747
748 /** Sets this instruction as ready to commit. */
749 void setCanCommit() { status.set(CanCommit); }
750
751 /** Clears this instruction as being ready to commit. */
752 void clearCanCommit() { status.reset(CanCommit); }
753
754 /** Returns whether or not this instruction is ready to commit. */
755 bool readyToCommit() const { return status[CanCommit]; }
756
757 void setAtCommit() { status.set(AtCommit); }
758
759 bool isAtCommit() { return status[AtCommit]; }
760
761 /** Sets this instruction as committed. */
762 void setCommitted() { status.set(Committed); }
763
764 /** Returns whether or not this instruction is committed. */
765 bool isCommitted() const { return status[Committed]; }
766
767 /** Sets this instruction as squashed. */
768 void setSquashed() { status.set(Squashed); }
769
770 /** Returns whether or not this instruction is squashed. */
771 bool isSquashed() const { return status[Squashed]; }
772
773 //Instruction Queue Entry
774 //-----------------------
775 /** Sets this instruction as a entry the IQ. */
776 void setInIQ() { status.set(IqEntry); }
777
778 /** Sets this instruction as a entry the IQ. */
779 void clearInIQ() { status.reset(IqEntry); }
780
781 /** Returns whether or not this instruction has issued. */
782 bool isInIQ() const { return status[IqEntry]; }
783
784 /** Sets this instruction as squashed in the IQ. */
785 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
786
787 /** Returns whether or not this instruction is squashed in the IQ. */
788 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
789
790
791 //Load / Store Queue Functions
792 //-----------------------
793 /** Sets this instruction as a entry the LSQ. */
794 void setInLSQ() { status.set(LsqEntry); }
795
796 /** Sets this instruction as a entry the LSQ. */
797 void removeInLSQ() { status.reset(LsqEntry); }
798
799 /** Returns whether or not this instruction is in the LSQ. */
800 bool isInLSQ() const { return status[LsqEntry]; }
801
802 /** Sets this instruction as squashed in the LSQ. */
803 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
804
805 /** Returns whether or not this instruction is squashed in the LSQ. */
806 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
807
808
809 //Reorder Buffer Functions
810 //-----------------------
811 /** Sets this instruction as a entry the ROB. */
812 void setInROB() { status.set(RobEntry); }
813
814 /** Sets this instruction as a entry the ROB. */
815 void clearInROB() { status.reset(RobEntry); }
816
817 /** Returns whether or not this instruction is in the ROB. */
818 bool isInROB() const { return status[RobEntry]; }
819
820 /** Sets this instruction as squashed in the ROB. */
821 void setSquashedInROB() { status.set(SquashedInROB); }
822
823 /** Returns whether or not this instruction is squashed in the ROB. */
824 bool isSquashedInROB() const { return status[SquashedInROB]; }
825
826 /** Read the PC state of this instruction. */
827 TheISA::PCState pcState() const { return pc; }
828
829 /** Set the PC state of this instruction. */
830 void pcState(const TheISA::PCState &val) { pc = val; }
831
832 /** Read the PC of this instruction. */
833 Addr instAddr() const { return pc.instAddr(); }
834
835 /** Read the PC of the next instruction. */
836 Addr nextInstAddr() const { return pc.nextInstAddr(); }
837
838 /**Read the micro PC of this instruction. */
839 Addr microPC() const { return pc.microPC(); }
840
841 bool readPredicate() const
842 {
843 return instFlags[Predicate];
844 }
845
846 void setPredicate(bool val)
847 {
848 instFlags[Predicate] = val;
849
850 if (traceData) {
851 traceData->setPredicate(val);
852 }
853 }
854
|
| 855 bool
856 readMemAccPredicate() const
857 {
858 return instFlags[MemAccPredicate];
859 }
860
861 void
862 setMemAccPredicate(bool val)
863 {
864 instFlags[MemAccPredicate] = val;
865 }
866
|
854 /** Sets the ASID. */
855 void setASID(short addr_space_id) { asid = addr_space_id; }
856 short getASID() { return asid; }
857
858 /** Sets the thread id. */
859 void setTid(ThreadID tid) { threadNumber = tid; }
860
861 /** Sets the pointer to the thread state. */
862 void setThreadState(ImplState *state) { thread = state; }
863
864 /** Returns the thread context. */
865 ThreadContext *tcBase() { return thread->getTC(); }
866
867 public:
868 /** Returns whether or not the eff. addr. source registers are ready. */
869 bool eaSrcsReady() const;
870
871 /** Is this instruction's memory access strictly ordered? */
872 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
873 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
874
875 /** Has this instruction generated a memory request. */
876 bool hasRequest() const { return instFlags[ReqMade]; }
877 /** Assert this instruction has generated a memory request. */
878 void setRequest() { instFlags[ReqMade] = true; }
879
880 /** Returns iterator to this instruction in the list of all insts. */
881 ListIt &getInstListIt() { return instListIt; }
882
883 /** Sets iterator for this instruction in the list of all insts. */
884 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
885
886 public:
887 /** Returns the number of consecutive store conditional failures. */
888 unsigned int readStCondFailures() const
889 { return thread->storeCondFailures; }
890
891 /** Sets the number of consecutive store conditional failures. */
892 void setStCondFailures(unsigned int sc_failures)
893 { thread->storeCondFailures = sc_failures; }
894
895 public:
896 // monitor/mwait funtions
897 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
898 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
899 void mwaitAtomic(ThreadContext *tc)
900 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
901 AddressMonitor *getAddrMonitor()
902 { return cpu->getCpuAddrMonitor(threadNumber); }
903};
904
905template<class Impl>
906Fault
907BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
908 Request::Flags flags)
909{
910 return cpu->pushRequest(
911 dynamic_cast<typename DynInstPtr::PtrType>(this),
912 /* ld */ true, nullptr, size, addr, flags, nullptr);
913}
914
915template<class Impl>
916Fault
917BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
918 Request::Flags flags, uint64_t *res)
919{
920 return cpu->pushRequest(
921 dynamic_cast<typename DynInstPtr::PtrType>(this),
922 /* st */ false, data, size, addr, flags, res);
923}
924
925template<class Impl>
926Fault
927BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
928 Request::Flags flags,
929 AtomicOpFunctor *amo_op)
930{
931 // atomic memory instructions do not have data to be written to memory yet
932 // since the atomic operations will be executed directly in cache/memory.
933 // Therefore, its `data` field is nullptr.
934 // Atomic memory requests need to carry their `amo_op` fields to cache/
935 // memory
936 return cpu->pushRequest(
937 dynamic_cast<typename DynInstPtr::PtrType>(this),
938 /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op);
939}
940
941#endif // __CPU_BASE_DYN_INST_HH__
| 867 /** Sets the ASID. */
868 void setASID(short addr_space_id) { asid = addr_space_id; }
869 short getASID() { return asid; }
870
871 /** Sets the thread id. */
872 void setTid(ThreadID tid) { threadNumber = tid; }
873
874 /** Sets the pointer to the thread state. */
875 void setThreadState(ImplState *state) { thread = state; }
876
877 /** Returns the thread context. */
878 ThreadContext *tcBase() { return thread->getTC(); }
879
880 public:
881 /** Returns whether or not the eff. addr. source registers are ready. */
882 bool eaSrcsReady() const;
883
884 /** Is this instruction's memory access strictly ordered? */
885 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
886 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
887
888 /** Has this instruction generated a memory request. */
889 bool hasRequest() const { return instFlags[ReqMade]; }
890 /** Assert this instruction has generated a memory request. */
891 void setRequest() { instFlags[ReqMade] = true; }
892
893 /** Returns iterator to this instruction in the list of all insts. */
894 ListIt &getInstListIt() { return instListIt; }
895
896 /** Sets iterator for this instruction in the list of all insts. */
897 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
898
899 public:
900 /** Returns the number of consecutive store conditional failures. */
901 unsigned int readStCondFailures() const
902 { return thread->storeCondFailures; }
903
904 /** Sets the number of consecutive store conditional failures. */
905 void setStCondFailures(unsigned int sc_failures)
906 { thread->storeCondFailures = sc_failures; }
907
908 public:
909 // monitor/mwait funtions
910 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
911 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
912 void mwaitAtomic(ThreadContext *tc)
913 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
914 AddressMonitor *getAddrMonitor()
915 { return cpu->getCpuAddrMonitor(threadNumber); }
916};
917
918template<class Impl>
919Fault
920BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
921 Request::Flags flags)
922{
923 return cpu->pushRequest(
924 dynamic_cast<typename DynInstPtr::PtrType>(this),
925 /* ld */ true, nullptr, size, addr, flags, nullptr);
926}
927
928template<class Impl>
929Fault
930BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
931 Request::Flags flags, uint64_t *res)
932{
933 return cpu->pushRequest(
934 dynamic_cast<typename DynInstPtr::PtrType>(this),
935 /* st */ false, data, size, addr, flags, res);
936}
937
938template<class Impl>
939Fault
940BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
941 Request::Flags flags,
942 AtomicOpFunctor *amo_op)
943{
944 // atomic memory instructions do not have data to be written to memory yet
945 // since the atomic operations will be executed directly in cache/memory.
946 // Therefore, its `data` field is nullptr.
947 // Atomic memory requests need to carry their `amo_op` fields to cache/
948 // memory
949 return cpu->pushRequest(
950 dynamic_cast<typename DynInstPtr::PtrType>(this),
951 /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op);
952}
953
954#endif // __CPU_BASE_DYN_INST_HH__
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