1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81 public:
82 // Typedef for the CPU.
83 typedef typename Impl::CPUType ImplCPU;
84 typedef typename ImplCPU::ImplState ImplState;
85 using VecRegContainer = TheISA::VecRegContainer;
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 protected:
100 enum Status {
101 IqEntry, /// Instruction is in the IQ
102 RobEntry, /// Instruction is in the ROB
103 LsqEntry, /// Instruction is in the LSQ
104 Completed, /// Instruction has completed
105 ResultReady, /// Instruction has its result
106 CanIssue, /// Instruction can issue and execute
107 Issued, /// Instruction has issued
108 Executed, /// Instruction has executed
109 CanCommit, /// Instruction can commit
110 AtCommit, /// Instruction has reached commit
111 Committed, /// Instruction has committed
112 Squashed, /// Instruction is squashed
113 SquashedInIQ, /// Instruction is squashed in the IQ
114 SquashedInLSQ, /// Instruction is squashed in the LSQ
115 SquashedInROB, /// Instruction is squashed in the ROB
116 RecoverInst, /// Is a recover instruction
117 BlockingInst, /// Is a blocking instruction
118 ThreadsyncWait, /// Is a thread synchronization instruction
119 SerializeBefore, /// Needs to serialize on
120 /// instructions ahead of it
121 SerializeAfter, /// Needs to serialize instructions behind it
122 SerializeHandled, /// Serialization has been handled
123 NumStatus
124 };
125
126 enum Flags {
127 NotAnInst,
128 TranslationStarted,
129 TranslationCompleted,
130 PossibleLoadViolation,
131 HitExternalSnoop,
132 EffAddrValid,
133 RecordResult,
134 Predicate,
135 PredTaken,
136 IsStrictlyOrdered,
137 ReqMade,
138 MemOpDone,
139 MaxFlags
140 };
141
142 public:
143 /** The sequence number of the instruction. */
144 InstSeqNum seqNum;
145
146 /** The StaticInst used by this BaseDynInst. */
147 const StaticInstPtr staticInst;
148
149 /** Pointer to the Impl's CPU object. */
150 ImplCPU *cpu;
151
152 BaseCPU *getCpuPtr() { return cpu; }
153
154 /** Pointer to the thread state. */
155 ImplState *thread;
156
157 /** The kind of fault this instruction has generated. */
158 Fault fault;
159
160 /** InstRecord that tracks this instructions. */
161 Trace::InstRecord *traceData;
162
163 protected:
164 /** The result of the instruction; assumes an instruction can have many
165 * destination registers.
166 */
167 std::queue<InstResult> instResult;
168
169 /** PC state for this instruction. */
170 TheISA::PCState pc;
171
172 /* An amalgamation of a lot of boolean values into one */
173 std::bitset<MaxFlags> instFlags;
174
175 /** The status of this BaseDynInst. Several bits can be set. */
176 std::bitset<NumStatus> status;
177
178 /** Whether or not the source register is ready.
179 * @todo: Not sure this should be here vs the derived class.
180 */
181 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
182
183 public:
184 /** The thread this instruction is from. */
185 ThreadID threadNumber;
186
187 /** Iterator pointing to this BaseDynInst in the list of all insts. */
188 ListIt instListIt;
189
190 ////////////////////// Branch Data ///////////////
191 /** Predicted PC state after this instruction. */
192 TheISA::PCState predPC;
193
194 /** The Macroop if one exists */
195 const StaticInstPtr macroop;
196
197 /** How many source registers are ready. */
198 uint8_t readyRegs;
199
200 public:
201 /////////////////////// Load Store Data //////////////////////
202 /** The effective virtual address (lds & stores only). */
203 Addr effAddr;
204
205 /** The effective physical address. */
206 Addr physEffAddrLow;
207
208 /** The effective physical address
209 * of the second request for a split request
210 */
211 Addr physEffAddrHigh;
212
213 /** The memory request flags (from translation). */
214 unsigned memReqFlags;
215
216 /** data address space ID, for loads & stores. */
217 short asid;
218
219 /** The size of the request */
220 uint8_t effSize;
221
222 /** Pointer to the data for the memory access. */
223 uint8_t *memData;
224
225 /** Load queue index. */
226 int16_t lqIdx;
227
228 /** Store queue index. */
229 int16_t sqIdx;
230
231
232 /////////////////////// TLB Miss //////////////////////
233 /**
234 * Saved memory requests (needed when the DTB address translation is
235 * delayed due to a hw page table walk).
236 */
237 RequestPtr savedReq;
238 RequestPtr savedSreqLow;
239 RequestPtr savedSreqHigh;
240
241 /////////////////////// Checker //////////////////////
242 // Need a copy of main request pointer to verify on writes.
243 RequestPtr reqToVerify;
244
245 protected:
246 /** Flattened register index of the destination registers of this
247 * instruction.
248 */
249 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
250
251 /** Physical register index of the destination registers of this
252 * instruction.
253 */
254 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
255
256 /** Physical register index of the source registers of this
257 * instruction.
258 */
259 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
260
261 /** Physical register index of the previous producers of the
262 * architected destinations.
263 */
264 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
265
266
267 public:
268 /** Records changes to result? */
269 void recordResult(bool f) { instFlags[RecordResult] = f; }
270
271 /** Is the effective virtual address valid. */
272 bool effAddrValid() const { return instFlags[EffAddrValid]; }
273
274 /** Whether or not the memory operation is done. */
275 bool memOpDone() const { return instFlags[MemOpDone]; }
276 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
277
278 bool notAnInst() const { return instFlags[NotAnInst]; }
279 void setNotAnInst() { instFlags[NotAnInst] = true; }
280
281
282 ////////////////////////////////////////////
283 //
284 // INSTRUCTION EXECUTION
285 //
286 ////////////////////////////////////////////
287
288 void demapPage(Addr vaddr, uint64_t asn)
289 {
290 cpu->demapPage(vaddr, asn);
291 }
292 void demapInstPage(Addr vaddr, uint64_t asn)
293 {
294 cpu->demapPage(vaddr, asn);
295 }
296 void demapDataPage(Addr vaddr, uint64_t asn)
297 {
298 cpu->demapPage(vaddr, asn);
299 }
300
301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302
303 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
304 Request::Flags flags, uint64_t *res);
305
306 /** Splits a request in two if it crosses a dcache block. */
307 void splitRequest(const RequestPtr &req, RequestPtr &sreqLow,
308 RequestPtr &sreqHigh);
309
310 /** Initiate a DTB address translation. */
311 void initiateTranslation(const RequestPtr &req, const RequestPtr &sreqLow,
312 const RequestPtr &sreqHigh, uint64_t *res,
313 BaseTLB::Mode mode);
314
315 /** Finish a DTB address translation. */
316 void finishTranslation(WholeTranslationState *state);
317
318 /** True if the DTB address translation has started. */
319 bool translationStarted() const { return instFlags[TranslationStarted]; }
320 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
321
322 /** True if the DTB address translation has completed. */
323 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
324 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
325
326 /** True if this address was found to match a previous load and they issued
327 * out of order. If that happend, then it's only a problem if an incoming
328 * snoop invalidate modifies the line, in which case we need to squash.
329 * If nothing modified the line the order doesn't matter.
330 */
331 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
332 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
333
334 /** True if the address hit a external snoop while sitting in the LSQ.
335 * If this is true and a older instruction sees it, this instruction must
336 * reexecute
337 */
338 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
339 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
340
341 /**
342 * Returns true if the DTB address translation is being delayed due to a hw
343 * page table walk.
344 */
345 bool isTranslationDelayed() const
346 {
347 return (translationStarted() && !translationCompleted());
348 }
349
350 public:
351#ifdef DEBUG
352 void dumpSNList();
353#endif
354
355 /** Returns the physical register index of the i'th destination
356 * register.
357 */
358 PhysRegIdPtr renamedDestRegIdx(int idx) const
359 {
360 return _destRegIdx[idx];
361 }
362
363 /** Returns the physical register index of the i'th source register. */
364 PhysRegIdPtr renamedSrcRegIdx(int idx) const
365 {
366 assert(TheISA::MaxInstSrcRegs > idx);
367 return _srcRegIdx[idx];
368 }
369
370 /** Returns the flattened register index of the i'th destination
371 * register.
372 */
373 const RegId& flattenedDestRegIdx(int idx) const
374 {
375 return _flatDestRegIdx[idx];
376 }
377
378 /** Returns the physical register index of the previous physical register
379 * that remapped to the same logical register index.
380 */
381 PhysRegIdPtr prevDestRegIdx(int idx) const
382 {
383 return _prevDestRegIdx[idx];
384 }
385
386 /** Renames a destination register to a physical register. Also records
387 * the previous physical register that the logical register mapped to.
388 */
389 void renameDestReg(int idx,
390 PhysRegIdPtr renamed_dest,
391 PhysRegIdPtr previous_rename)
392 {
393 _destRegIdx[idx] = renamed_dest;
394 _prevDestRegIdx[idx] = previous_rename;
395 }
396
397 /** Renames a source logical register to the physical register which
398 * has/will produce that logical register's result.
399 * @todo: add in whether or not the source register is ready.
400 */
401 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
402 {
403 _srcRegIdx[idx] = renamed_src;
404 }
405
406 /** Flattens a destination architectural register index into a logical
407 * index.
408 */
409 void flattenDestReg(int idx, const RegId& flattened_dest)
410 {
411 _flatDestRegIdx[idx] = flattened_dest;
412 }
413 /** BaseDynInst constructor given a binary instruction.
414 * @param staticInst A StaticInstPtr to the underlying instruction.
415 * @param pc The PC state for the instruction.
416 * @param predPC The predicted next PC state for the instruction.
417 * @param seq_num The sequence number of the instruction.
418 * @param cpu Pointer to the instruction's CPU.
419 */
420 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
421 TheISA::PCState pc, TheISA::PCState predPC,
422 InstSeqNum seq_num, ImplCPU *cpu);
423
424 /** BaseDynInst constructor given a StaticInst pointer.
425 * @param _staticInst The StaticInst for this BaseDynInst.
426 */
427 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
428
429 /** BaseDynInst destructor. */
430 ~BaseDynInst();
431
432 private:
433 /** Function to initialize variables in the constructors. */
434 void initVars();
435
436 public:
437 /** Dumps out contents of this BaseDynInst. */
438 void dump();
439
440 /** Dumps out contents of this BaseDynInst into given string. */
441 void dump(std::string &outstring);
442
443 /** Read this CPU's ID. */
444 int cpuId() const { return cpu->cpuId(); }
445
446 /** Read this CPU's Socket ID. */
447 uint32_t socketId() const { return cpu->socketId(); }
448
449 /** Read this CPU's data requestor ID */
450 MasterID masterId() const { return cpu->dataMasterId(); }
451
452 /** Read this context's system-wide ID **/
453 ContextID contextId() const { return thread->contextId(); }
454
455 /** Returns the fault type. */
456 Fault getFault() const { return fault; }
457
458 /** Checks whether or not this instruction has had its branch target
459 * calculated yet. For now it is not utilized and is hacked to be
460 * always false.
461 * @todo: Actually use this instruction.
462 */
463 bool doneTargCalc() { return false; }
464
465 /** Set the predicted target of this current instruction. */
466 void setPredTarg(const TheISA::PCState &_predPC)
467 {
468 predPC = _predPC;
469 }
470
471 const TheISA::PCState &readPredTarg() { return predPC; }
472
473 /** Returns the predicted PC immediately after the branch. */
474 Addr predInstAddr() { return predPC.instAddr(); }
475
476 /** Returns the predicted PC two instructions after the branch */
477 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
478
479 /** Returns the predicted micro PC after the branch */
480 Addr predMicroPC() { return predPC.microPC(); }
481
482 /** Returns whether the instruction was predicted taken or not. */
483 bool readPredTaken()
484 {
485 return instFlags[PredTaken];
486 }
487
488 void setPredTaken(bool predicted_taken)
489 {
490 instFlags[PredTaken] = predicted_taken;
491 }
492
493 /** Returns whether the instruction mispredicted. */
494 bool mispredicted()
495 {
496 TheISA::PCState tempPC = pc;
497 TheISA::advancePC(tempPC, staticInst);
498 return !(tempPC == predPC);
499 }
500
501 //
502 // Instruction types. Forward checks to StaticInst object.
503 //
504 bool isNop() const { return staticInst->isNop(); }
505 bool isMemRef() const { return staticInst->isMemRef(); }
506 bool isLoad() const { return staticInst->isLoad(); }
507 bool isStore() const { return staticInst->isStore(); }
508 bool isAtomic() const { return staticInst->isAtomic(); }
509 bool isStoreConditional() const
510 { return staticInst->isStoreConditional(); }
511 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
512 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
513 bool isInteger() const { return staticInst->isInteger(); }
514 bool isFloating() const { return staticInst->isFloating(); }
515 bool isVector() const { return staticInst->isVector(); }
516 bool isControl() const { return staticInst->isControl(); }
517 bool isCall() const { return staticInst->isCall(); }
518 bool isReturn() const { return staticInst->isReturn(); }
519 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
520 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
521 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
522 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
523 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
524 bool isThreadSync() const { return staticInst->isThreadSync(); }
525 bool isSerializing() const { return staticInst->isSerializing(); }
526 bool isSerializeBefore() const
527 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
528 bool isSerializeAfter() const
529 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
530 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
531 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
532 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
533 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
534 bool isQuiesce() const { return staticInst->isQuiesce(); }
535 bool isIprAccess() const { return staticInst->isIprAccess(); }
536 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
537 bool isSyscall() const { return staticInst->isSyscall(); }
538 bool isMacroop() const { return staticInst->isMacroop(); }
539 bool isMicroop() const { return staticInst->isMicroop(); }
540 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
541 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
542 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
543 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
544
545 /** Temporarily sets this instruction as a serialize before instruction. */
546 void setSerializeBefore() { status.set(SerializeBefore); }
547
548 /** Clears the serializeBefore part of this instruction. */
549 void clearSerializeBefore() { status.reset(SerializeBefore); }
550
551 /** Checks if this serializeBefore is only temporarily set. */
552 bool isTempSerializeBefore() { return status[SerializeBefore]; }
553
554 /** Temporarily sets this instruction as a serialize after instruction. */
555 void setSerializeAfter() { status.set(SerializeAfter); }
556
557 /** Clears the serializeAfter part of this instruction.*/
558 void clearSerializeAfter() { status.reset(SerializeAfter); }
559
560 /** Checks if this serializeAfter is only temporarily set. */
561 bool isTempSerializeAfter() { return status[SerializeAfter]; }
562
563 /** Sets the serialization part of this instruction as handled. */
564 void setSerializeHandled() { status.set(SerializeHandled); }
565
566 /** Checks if the serialization part of this instruction has been
567 * handled. This does not apply to the temporary serializing
568 * state; it only applies to this instruction's own permanent
569 * serializing state.
570 */
571 bool isSerializeHandled() { return status[SerializeHandled]; }
572
573 /** Returns the opclass of this instruction. */
574 OpClass opClass() const { return staticInst->opClass(); }
575
576 /** Returns the branch target address. */
577 TheISA::PCState branchTarget() const
578 { return staticInst->branchTarget(pc); }
579
580 /** Returns the number of source registers. */
581 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
582
583 /** Returns the number of destination registers. */
584 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
585
586 // the following are used to track physical register usage
587 // for machines with separate int & FP reg files
588 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
589 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
590 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
591 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
592 int8_t numVecElemDestRegs() const {
593 return staticInst->numVecElemDestRegs();
594 }
595
596 /** Returns the logical register index of the i'th destination register. */
597 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
598
599 /** Returns the logical register index of the i'th source register. */
600 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
601
602 /** Return the size of the instResult queue. */
603 uint8_t resultSize() { return instResult.size(); }
604
605 /** Pops a result off the instResult queue.
606 * If the result stack is empty, return the default value.
607 * */
608 InstResult popResult(InstResult dflt = InstResult())
609 {
610 if (!instResult.empty()) {
611 InstResult t = instResult.front();
612 instResult.pop();
613 return t;
614 }
615 return dflt;
616 }
617
618 /** Pushes a result onto the instResult queue. */
619 /** @{ */
620 /** Scalar result. */
621 template<typename T>
622 void setScalarResult(T&& t)
623 {
624 if (instFlags[RecordResult]) {
625 instResult.push(InstResult(std::forward<T>(t),
626 InstResult::ResultType::Scalar));
627 }
628 }
629
630 /** Full vector result. */
631 template<typename T>
632 void setVecResult(T&& t)
633 {
634 if (instFlags[RecordResult]) {
635 instResult.push(InstResult(std::forward<T>(t),
636 InstResult::ResultType::VecReg));
637 }
638 }
639
640 /** Vector element result. */
641 template<typename T>
642 void setVecElemResult(T&& t)
643 {
644 if (instFlags[RecordResult]) {
645 instResult.push(InstResult(std::forward<T>(t),
646 InstResult::ResultType::VecElem));
647 }
648 }
649 /** @} */
650
651 /** Records an integer register being set to a value. */
| 1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81 public:
82 // Typedef for the CPU.
83 typedef typename Impl::CPUType ImplCPU;
84 typedef typename ImplCPU::ImplState ImplState;
85 using VecRegContainer = TheISA::VecRegContainer;
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 protected:
100 enum Status {
101 IqEntry, /// Instruction is in the IQ
102 RobEntry, /// Instruction is in the ROB
103 LsqEntry, /// Instruction is in the LSQ
104 Completed, /// Instruction has completed
105 ResultReady, /// Instruction has its result
106 CanIssue, /// Instruction can issue and execute
107 Issued, /// Instruction has issued
108 Executed, /// Instruction has executed
109 CanCommit, /// Instruction can commit
110 AtCommit, /// Instruction has reached commit
111 Committed, /// Instruction has committed
112 Squashed, /// Instruction is squashed
113 SquashedInIQ, /// Instruction is squashed in the IQ
114 SquashedInLSQ, /// Instruction is squashed in the LSQ
115 SquashedInROB, /// Instruction is squashed in the ROB
116 RecoverInst, /// Is a recover instruction
117 BlockingInst, /// Is a blocking instruction
118 ThreadsyncWait, /// Is a thread synchronization instruction
119 SerializeBefore, /// Needs to serialize on
120 /// instructions ahead of it
121 SerializeAfter, /// Needs to serialize instructions behind it
122 SerializeHandled, /// Serialization has been handled
123 NumStatus
124 };
125
126 enum Flags {
127 NotAnInst,
128 TranslationStarted,
129 TranslationCompleted,
130 PossibleLoadViolation,
131 HitExternalSnoop,
132 EffAddrValid,
133 RecordResult,
134 Predicate,
135 PredTaken,
136 IsStrictlyOrdered,
137 ReqMade,
138 MemOpDone,
139 MaxFlags
140 };
141
142 public:
143 /** The sequence number of the instruction. */
144 InstSeqNum seqNum;
145
146 /** The StaticInst used by this BaseDynInst. */
147 const StaticInstPtr staticInst;
148
149 /** Pointer to the Impl's CPU object. */
150 ImplCPU *cpu;
151
152 BaseCPU *getCpuPtr() { return cpu; }
153
154 /** Pointer to the thread state. */
155 ImplState *thread;
156
157 /** The kind of fault this instruction has generated. */
158 Fault fault;
159
160 /** InstRecord that tracks this instructions. */
161 Trace::InstRecord *traceData;
162
163 protected:
164 /** The result of the instruction; assumes an instruction can have many
165 * destination registers.
166 */
167 std::queue<InstResult> instResult;
168
169 /** PC state for this instruction. */
170 TheISA::PCState pc;
171
172 /* An amalgamation of a lot of boolean values into one */
173 std::bitset<MaxFlags> instFlags;
174
175 /** The status of this BaseDynInst. Several bits can be set. */
176 std::bitset<NumStatus> status;
177
178 /** Whether or not the source register is ready.
179 * @todo: Not sure this should be here vs the derived class.
180 */
181 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
182
183 public:
184 /** The thread this instruction is from. */
185 ThreadID threadNumber;
186
187 /** Iterator pointing to this BaseDynInst in the list of all insts. */
188 ListIt instListIt;
189
190 ////////////////////// Branch Data ///////////////
191 /** Predicted PC state after this instruction. */
192 TheISA::PCState predPC;
193
194 /** The Macroop if one exists */
195 const StaticInstPtr macroop;
196
197 /** How many source registers are ready. */
198 uint8_t readyRegs;
199
200 public:
201 /////////////////////// Load Store Data //////////////////////
202 /** The effective virtual address (lds & stores only). */
203 Addr effAddr;
204
205 /** The effective physical address. */
206 Addr physEffAddrLow;
207
208 /** The effective physical address
209 * of the second request for a split request
210 */
211 Addr physEffAddrHigh;
212
213 /** The memory request flags (from translation). */
214 unsigned memReqFlags;
215
216 /** data address space ID, for loads & stores. */
217 short asid;
218
219 /** The size of the request */
220 uint8_t effSize;
221
222 /** Pointer to the data for the memory access. */
223 uint8_t *memData;
224
225 /** Load queue index. */
226 int16_t lqIdx;
227
228 /** Store queue index. */
229 int16_t sqIdx;
230
231
232 /////////////////////// TLB Miss //////////////////////
233 /**
234 * Saved memory requests (needed when the DTB address translation is
235 * delayed due to a hw page table walk).
236 */
237 RequestPtr savedReq;
238 RequestPtr savedSreqLow;
239 RequestPtr savedSreqHigh;
240
241 /////////////////////// Checker //////////////////////
242 // Need a copy of main request pointer to verify on writes.
243 RequestPtr reqToVerify;
244
245 protected:
246 /** Flattened register index of the destination registers of this
247 * instruction.
248 */
249 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
250
251 /** Physical register index of the destination registers of this
252 * instruction.
253 */
254 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
255
256 /** Physical register index of the source registers of this
257 * instruction.
258 */
259 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
260
261 /** Physical register index of the previous producers of the
262 * architected destinations.
263 */
264 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
265
266
267 public:
268 /** Records changes to result? */
269 void recordResult(bool f) { instFlags[RecordResult] = f; }
270
271 /** Is the effective virtual address valid. */
272 bool effAddrValid() const { return instFlags[EffAddrValid]; }
273
274 /** Whether or not the memory operation is done. */
275 bool memOpDone() const { return instFlags[MemOpDone]; }
276 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
277
278 bool notAnInst() const { return instFlags[NotAnInst]; }
279 void setNotAnInst() { instFlags[NotAnInst] = true; }
280
281
282 ////////////////////////////////////////////
283 //
284 // INSTRUCTION EXECUTION
285 //
286 ////////////////////////////////////////////
287
288 void demapPage(Addr vaddr, uint64_t asn)
289 {
290 cpu->demapPage(vaddr, asn);
291 }
292 void demapInstPage(Addr vaddr, uint64_t asn)
293 {
294 cpu->demapPage(vaddr, asn);
295 }
296 void demapDataPage(Addr vaddr, uint64_t asn)
297 {
298 cpu->demapPage(vaddr, asn);
299 }
300
301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302
303 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
304 Request::Flags flags, uint64_t *res);
305
306 /** Splits a request in two if it crosses a dcache block. */
307 void splitRequest(const RequestPtr &req, RequestPtr &sreqLow,
308 RequestPtr &sreqHigh);
309
310 /** Initiate a DTB address translation. */
311 void initiateTranslation(const RequestPtr &req, const RequestPtr &sreqLow,
312 const RequestPtr &sreqHigh, uint64_t *res,
313 BaseTLB::Mode mode);
314
315 /** Finish a DTB address translation. */
316 void finishTranslation(WholeTranslationState *state);
317
318 /** True if the DTB address translation has started. */
319 bool translationStarted() const { return instFlags[TranslationStarted]; }
320 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
321
322 /** True if the DTB address translation has completed. */
323 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
324 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
325
326 /** True if this address was found to match a previous load and they issued
327 * out of order. If that happend, then it's only a problem if an incoming
328 * snoop invalidate modifies the line, in which case we need to squash.
329 * If nothing modified the line the order doesn't matter.
330 */
331 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
332 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
333
334 /** True if the address hit a external snoop while sitting in the LSQ.
335 * If this is true and a older instruction sees it, this instruction must
336 * reexecute
337 */
338 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
339 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
340
341 /**
342 * Returns true if the DTB address translation is being delayed due to a hw
343 * page table walk.
344 */
345 bool isTranslationDelayed() const
346 {
347 return (translationStarted() && !translationCompleted());
348 }
349
350 public:
351#ifdef DEBUG
352 void dumpSNList();
353#endif
354
355 /** Returns the physical register index of the i'th destination
356 * register.
357 */
358 PhysRegIdPtr renamedDestRegIdx(int idx) const
359 {
360 return _destRegIdx[idx];
361 }
362
363 /** Returns the physical register index of the i'th source register. */
364 PhysRegIdPtr renamedSrcRegIdx(int idx) const
365 {
366 assert(TheISA::MaxInstSrcRegs > idx);
367 return _srcRegIdx[idx];
368 }
369
370 /** Returns the flattened register index of the i'th destination
371 * register.
372 */
373 const RegId& flattenedDestRegIdx(int idx) const
374 {
375 return _flatDestRegIdx[idx];
376 }
377
378 /** Returns the physical register index of the previous physical register
379 * that remapped to the same logical register index.
380 */
381 PhysRegIdPtr prevDestRegIdx(int idx) const
382 {
383 return _prevDestRegIdx[idx];
384 }
385
386 /** Renames a destination register to a physical register. Also records
387 * the previous physical register that the logical register mapped to.
388 */
389 void renameDestReg(int idx,
390 PhysRegIdPtr renamed_dest,
391 PhysRegIdPtr previous_rename)
392 {
393 _destRegIdx[idx] = renamed_dest;
394 _prevDestRegIdx[idx] = previous_rename;
395 }
396
397 /** Renames a source logical register to the physical register which
398 * has/will produce that logical register's result.
399 * @todo: add in whether or not the source register is ready.
400 */
401 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
402 {
403 _srcRegIdx[idx] = renamed_src;
404 }
405
406 /** Flattens a destination architectural register index into a logical
407 * index.
408 */
409 void flattenDestReg(int idx, const RegId& flattened_dest)
410 {
411 _flatDestRegIdx[idx] = flattened_dest;
412 }
413 /** BaseDynInst constructor given a binary instruction.
414 * @param staticInst A StaticInstPtr to the underlying instruction.
415 * @param pc The PC state for the instruction.
416 * @param predPC The predicted next PC state for the instruction.
417 * @param seq_num The sequence number of the instruction.
418 * @param cpu Pointer to the instruction's CPU.
419 */
420 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
421 TheISA::PCState pc, TheISA::PCState predPC,
422 InstSeqNum seq_num, ImplCPU *cpu);
423
424 /** BaseDynInst constructor given a StaticInst pointer.
425 * @param _staticInst The StaticInst for this BaseDynInst.
426 */
427 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
428
429 /** BaseDynInst destructor. */
430 ~BaseDynInst();
431
432 private:
433 /** Function to initialize variables in the constructors. */
434 void initVars();
435
436 public:
437 /** Dumps out contents of this BaseDynInst. */
438 void dump();
439
440 /** Dumps out contents of this BaseDynInst into given string. */
441 void dump(std::string &outstring);
442
443 /** Read this CPU's ID. */
444 int cpuId() const { return cpu->cpuId(); }
445
446 /** Read this CPU's Socket ID. */
447 uint32_t socketId() const { return cpu->socketId(); }
448
449 /** Read this CPU's data requestor ID */
450 MasterID masterId() const { return cpu->dataMasterId(); }
451
452 /** Read this context's system-wide ID **/
453 ContextID contextId() const { return thread->contextId(); }
454
455 /** Returns the fault type. */
456 Fault getFault() const { return fault; }
457
458 /** Checks whether or not this instruction has had its branch target
459 * calculated yet. For now it is not utilized and is hacked to be
460 * always false.
461 * @todo: Actually use this instruction.
462 */
463 bool doneTargCalc() { return false; }
464
465 /** Set the predicted target of this current instruction. */
466 void setPredTarg(const TheISA::PCState &_predPC)
467 {
468 predPC = _predPC;
469 }
470
471 const TheISA::PCState &readPredTarg() { return predPC; }
472
473 /** Returns the predicted PC immediately after the branch. */
474 Addr predInstAddr() { return predPC.instAddr(); }
475
476 /** Returns the predicted PC two instructions after the branch */
477 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
478
479 /** Returns the predicted micro PC after the branch */
480 Addr predMicroPC() { return predPC.microPC(); }
481
482 /** Returns whether the instruction was predicted taken or not. */
483 bool readPredTaken()
484 {
485 return instFlags[PredTaken];
486 }
487
488 void setPredTaken(bool predicted_taken)
489 {
490 instFlags[PredTaken] = predicted_taken;
491 }
492
493 /** Returns whether the instruction mispredicted. */
494 bool mispredicted()
495 {
496 TheISA::PCState tempPC = pc;
497 TheISA::advancePC(tempPC, staticInst);
498 return !(tempPC == predPC);
499 }
500
501 //
502 // Instruction types. Forward checks to StaticInst object.
503 //
504 bool isNop() const { return staticInst->isNop(); }
505 bool isMemRef() const { return staticInst->isMemRef(); }
506 bool isLoad() const { return staticInst->isLoad(); }
507 bool isStore() const { return staticInst->isStore(); }
508 bool isAtomic() const { return staticInst->isAtomic(); }
509 bool isStoreConditional() const
510 { return staticInst->isStoreConditional(); }
511 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
512 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
513 bool isInteger() const { return staticInst->isInteger(); }
514 bool isFloating() const { return staticInst->isFloating(); }
515 bool isVector() const { return staticInst->isVector(); }
516 bool isControl() const { return staticInst->isControl(); }
517 bool isCall() const { return staticInst->isCall(); }
518 bool isReturn() const { return staticInst->isReturn(); }
519 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
520 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
521 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
522 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
523 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
524 bool isThreadSync() const { return staticInst->isThreadSync(); }
525 bool isSerializing() const { return staticInst->isSerializing(); }
526 bool isSerializeBefore() const
527 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
528 bool isSerializeAfter() const
529 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
530 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
531 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
532 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
533 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
534 bool isQuiesce() const { return staticInst->isQuiesce(); }
535 bool isIprAccess() const { return staticInst->isIprAccess(); }
536 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
537 bool isSyscall() const { return staticInst->isSyscall(); }
538 bool isMacroop() const { return staticInst->isMacroop(); }
539 bool isMicroop() const { return staticInst->isMicroop(); }
540 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
541 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
542 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
543 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
544
545 /** Temporarily sets this instruction as a serialize before instruction. */
546 void setSerializeBefore() { status.set(SerializeBefore); }
547
548 /** Clears the serializeBefore part of this instruction. */
549 void clearSerializeBefore() { status.reset(SerializeBefore); }
550
551 /** Checks if this serializeBefore is only temporarily set. */
552 bool isTempSerializeBefore() { return status[SerializeBefore]; }
553
554 /** Temporarily sets this instruction as a serialize after instruction. */
555 void setSerializeAfter() { status.set(SerializeAfter); }
556
557 /** Clears the serializeAfter part of this instruction.*/
558 void clearSerializeAfter() { status.reset(SerializeAfter); }
559
560 /** Checks if this serializeAfter is only temporarily set. */
561 bool isTempSerializeAfter() { return status[SerializeAfter]; }
562
563 /** Sets the serialization part of this instruction as handled. */
564 void setSerializeHandled() { status.set(SerializeHandled); }
565
566 /** Checks if the serialization part of this instruction has been
567 * handled. This does not apply to the temporary serializing
568 * state; it only applies to this instruction's own permanent
569 * serializing state.
570 */
571 bool isSerializeHandled() { return status[SerializeHandled]; }
572
573 /** Returns the opclass of this instruction. */
574 OpClass opClass() const { return staticInst->opClass(); }
575
576 /** Returns the branch target address. */
577 TheISA::PCState branchTarget() const
578 { return staticInst->branchTarget(pc); }
579
580 /** Returns the number of source registers. */
581 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
582
583 /** Returns the number of destination registers. */
584 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
585
586 // the following are used to track physical register usage
587 // for machines with separate int & FP reg files
588 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
589 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
590 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
591 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
592 int8_t numVecElemDestRegs() const {
593 return staticInst->numVecElemDestRegs();
594 }
595
596 /** Returns the logical register index of the i'th destination register. */
597 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
598
599 /** Returns the logical register index of the i'th source register. */
600 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
601
602 /** Return the size of the instResult queue. */
603 uint8_t resultSize() { return instResult.size(); }
604
605 /** Pops a result off the instResult queue.
606 * If the result stack is empty, return the default value.
607 * */
608 InstResult popResult(InstResult dflt = InstResult())
609 {
610 if (!instResult.empty()) {
611 InstResult t = instResult.front();
612 instResult.pop();
613 return t;
614 }
615 return dflt;
616 }
617
618 /** Pushes a result onto the instResult queue. */
619 /** @{ */
620 /** Scalar result. */
621 template<typename T>
622 void setScalarResult(T&& t)
623 {
624 if (instFlags[RecordResult]) {
625 instResult.push(InstResult(std::forward<T>(t),
626 InstResult::ResultType::Scalar));
627 }
628 }
629
630 /** Full vector result. */
631 template<typename T>
632 void setVecResult(T&& t)
633 {
634 if (instFlags[RecordResult]) {
635 instResult.push(InstResult(std::forward<T>(t),
636 InstResult::ResultType::VecReg));
637 }
638 }
639
640 /** Vector element result. */
641 template<typename T>
642 void setVecElemResult(T&& t)
643 {
644 if (instFlags[RecordResult]) {
645 instResult.push(InstResult(std::forward<T>(t),
646 InstResult::ResultType::VecElem));
647 }
648 }
649 /** @} */
650
651 /** Records an integer register being set to a value. */
|
673 {
674 setScalarResult(val);
675 }
676
677 /** Record a vector register being set to a value */
678 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
679 {
680 setVecElemResult(val);
681 }
682
683 /** Records that one of the source registers is ready. */
684 void markSrcRegReady();
685
686 /** Marks a specific register as ready. */
687 void markSrcRegReady(RegIndex src_idx);
688
689 /** Returns if a source register is ready. */
690 bool isReadySrcRegIdx(int idx) const
691 {
692 return this->_readySrcRegIdx[idx];
693 }
694
695 /** Sets this instruction as completed. */
696 void setCompleted() { status.set(Completed); }
697
698 /** Returns whether or not this instruction is completed. */
699 bool isCompleted() const { return status[Completed]; }
700
701 /** Marks the result as ready. */
702 void setResultReady() { status.set(ResultReady); }
703
704 /** Returns whether or not the result is ready. */
705 bool isResultReady() const { return status[ResultReady]; }
706
707 /** Sets this instruction as ready to issue. */
708 void setCanIssue() { status.set(CanIssue); }
709
710 /** Returns whether or not this instruction is ready to issue. */
711 bool readyToIssue() const { return status[CanIssue]; }
712
713 /** Clears this instruction being able to issue. */
714 void clearCanIssue() { status.reset(CanIssue); }
715
716 /** Sets this instruction as issued from the IQ. */
717 void setIssued() { status.set(Issued); }
718
719 /** Returns whether or not this instruction has issued. */
720 bool isIssued() const { return status[Issued]; }
721
722 /** Clears this instruction as being issued. */
723 void clearIssued() { status.reset(Issued); }
724
725 /** Sets this instruction as executed. */
726 void setExecuted() { status.set(Executed); }
727
728 /** Returns whether or not this instruction has executed. */
729 bool isExecuted() const { return status[Executed]; }
730
731 /** Sets this instruction as ready to commit. */
732 void setCanCommit() { status.set(CanCommit); }
733
734 /** Clears this instruction as being ready to commit. */
735 void clearCanCommit() { status.reset(CanCommit); }
736
737 /** Returns whether or not this instruction is ready to commit. */
738 bool readyToCommit() const { return status[CanCommit]; }
739
740 void setAtCommit() { status.set(AtCommit); }
741
742 bool isAtCommit() { return status[AtCommit]; }
743
744 /** Sets this instruction as committed. */
745 void setCommitted() { status.set(Committed); }
746
747 /** Returns whether or not this instruction is committed. */
748 bool isCommitted() const { return status[Committed]; }
749
750 /** Sets this instruction as squashed. */
751 void setSquashed() { status.set(Squashed); }
752
753 /** Returns whether or not this instruction is squashed. */
754 bool isSquashed() const { return status[Squashed]; }
755
756 //Instruction Queue Entry
757 //-----------------------
758 /** Sets this instruction as a entry the IQ. */
759 void setInIQ() { status.set(IqEntry); }
760
761 /** Sets this instruction as a entry the IQ. */
762 void clearInIQ() { status.reset(IqEntry); }
763
764 /** Returns whether or not this instruction has issued. */
765 bool isInIQ() const { return status[IqEntry]; }
766
767 /** Sets this instruction as squashed in the IQ. */
768 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
769
770 /** Returns whether or not this instruction is squashed in the IQ. */
771 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
772
773
774 //Load / Store Queue Functions
775 //-----------------------
776 /** Sets this instruction as a entry the LSQ. */
777 void setInLSQ() { status.set(LsqEntry); }
778
779 /** Sets this instruction as a entry the LSQ. */
780 void removeInLSQ() { status.reset(LsqEntry); }
781
782 /** Returns whether or not this instruction is in the LSQ. */
783 bool isInLSQ() const { return status[LsqEntry]; }
784
785 /** Sets this instruction as squashed in the LSQ. */
786 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
787
788 /** Returns whether or not this instruction is squashed in the LSQ. */
789 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
790
791
792 //Reorder Buffer Functions
793 //-----------------------
794 /** Sets this instruction as a entry the ROB. */
795 void setInROB() { status.set(RobEntry); }
796
797 /** Sets this instruction as a entry the ROB. */
798 void clearInROB() { status.reset(RobEntry); }
799
800 /** Returns whether or not this instruction is in the ROB. */
801 bool isInROB() const { return status[RobEntry]; }
802
803 /** Sets this instruction as squashed in the ROB. */
804 void setSquashedInROB() { status.set(SquashedInROB); }
805
806 /** Returns whether or not this instruction is squashed in the ROB. */
807 bool isSquashedInROB() const { return status[SquashedInROB]; }
808
809 /** Read the PC state of this instruction. */
810 TheISA::PCState pcState() const { return pc; }
811
812 /** Set the PC state of this instruction. */
813 void pcState(const TheISA::PCState &val) { pc = val; }
814
815 /** Read the PC of this instruction. */
816 Addr instAddr() const { return pc.instAddr(); }
817
818 /** Read the PC of the next instruction. */
819 Addr nextInstAddr() const { return pc.nextInstAddr(); }
820
821 /**Read the micro PC of this instruction. */
822 Addr microPC() const { return pc.microPC(); }
823
824 bool readPredicate() const
825 {
826 return instFlags[Predicate];
827 }
828
829 void setPredicate(bool val)
830 {
831 instFlags[Predicate] = val;
832
833 if (traceData) {
834 traceData->setPredicate(val);
835 }
836 }
837
838 /** Sets the ASID. */
839 void setASID(short addr_space_id) { asid = addr_space_id; }
840
841 /** Sets the thread id. */
842 void setTid(ThreadID tid) { threadNumber = tid; }
843
844 /** Sets the pointer to the thread state. */
845 void setThreadState(ImplState *state) { thread = state; }
846
847 /** Returns the thread context. */
848 ThreadContext *tcBase() { return thread->getTC(); }
849
850 public:
851 /** Returns whether or not the eff. addr. source registers are ready. */
852 bool eaSrcsReady() const;
853
854 /** Is this instruction's memory access strictly ordered? */
855 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
856
857 /** Has this instruction generated a memory request. */
858 bool hasRequest() const { return instFlags[ReqMade]; }
859
860 /** Returns iterator to this instruction in the list of all insts. */
861 ListIt &getInstListIt() { return instListIt; }
862
863 /** Sets iterator for this instruction in the list of all insts. */
864 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
865
866 public:
867 /** Returns the number of consecutive store conditional failures. */
868 unsigned int readStCondFailures() const
869 { return thread->storeCondFailures; }
870
871 /** Sets the number of consecutive store conditional failures. */
872 void setStCondFailures(unsigned int sc_failures)
873 { thread->storeCondFailures = sc_failures; }
874
875 public:
876 // monitor/mwait funtions
877 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
878 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
879 void mwaitAtomic(ThreadContext *tc)
880 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
881 AddressMonitor *getAddrMonitor()
882 { return cpu->getCpuAddrMonitor(threadNumber); }
883};
884
885template<class Impl>
886Fault
887BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
888 Request::Flags flags)
889{
890 instFlags[ReqMade] = true;
891 RequestPtr req = NULL;
892 RequestPtr sreqLow = NULL;
893 RequestPtr sreqHigh = NULL;
894
895 if (instFlags[ReqMade] && translationStarted()) {
896 req = savedReq;
897 sreqLow = savedSreqLow;
898 sreqHigh = savedSreqHigh;
899 } else {
900 req = std::make_shared<Request>(
901 asid, addr, size, flags, masterId(),
902 this->pc.instAddr(), thread->contextId());
903
904 req->taskId(cpu->taskId());
905
906 // Only split the request if the ISA supports unaligned accesses.
907 if (TheISA::HasUnalignedMemAcc) {
908 splitRequest(req, sreqLow, sreqHigh);
909 }
910 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
911 }
912
913 if (translationCompleted()) {
914 if (fault == NoFault) {
915 effAddr = req->getVaddr();
916 effSize = size;
917 instFlags[EffAddrValid] = true;
918
919 if (cpu->checker) {
920 reqToVerify = std::make_shared<Request>(*req);
921 }
922 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
923 } else {
924 // Commit will have to clean up whatever happened. Set this
925 // instruction as executed.
926 this->setExecuted();
927 }
928 }
929
930 if (traceData)
931 traceData->setMem(addr, size, flags);
932
933 return fault;
934}
935
936template<class Impl>
937Fault
938BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
939 Request::Flags flags, uint64_t *res)
940{
941 if (traceData)
942 traceData->setMem(addr, size, flags);
943
944 instFlags[ReqMade] = true;
945 RequestPtr req = NULL;
946 RequestPtr sreqLow = NULL;
947 RequestPtr sreqHigh = NULL;
948
949 if (instFlags[ReqMade] && translationStarted()) {
950 req = savedReq;
951 sreqLow = savedSreqLow;
952 sreqHigh = savedSreqHigh;
953 } else {
954 req = std::make_shared<Request>(
955 asid, addr, size, flags, masterId(),
956 this->pc.instAddr(), thread->contextId());
957
958 req->taskId(cpu->taskId());
959
960 // Only split the request if the ISA supports unaligned accesses.
961 if (TheISA::HasUnalignedMemAcc) {
962 splitRequest(req, sreqLow, sreqHigh);
963 }
964 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
965 }
966
967 if (fault == NoFault && translationCompleted()) {
968 effAddr = req->getVaddr();
969 effSize = size;
970 instFlags[EffAddrValid] = true;
971
972 if (cpu->checker) {
973 reqToVerify = std::make_shared<Request>(*req);
974 }
975 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
976 }
977
978 return fault;
979}
980
981template<class Impl>
982inline void
983BaseDynInst<Impl>::splitRequest(const RequestPtr &req, RequestPtr &sreqLow,
984 RequestPtr &sreqHigh)
985{
986 // Check to see if the request crosses the next level block boundary.
987 unsigned block_size = cpu->cacheLineSize();
988 Addr addr = req->getVaddr();
989 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
990 assert(split_addr <= addr || split_addr - addr < block_size);
991
992 // Spans two blocks.
993 if (split_addr > addr) {
994 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
995 }
996}
997
998template<class Impl>
999inline void
1000BaseDynInst<Impl>::initiateTranslation(const RequestPtr &req,
1001 const RequestPtr &sreqLow,
1002 const RequestPtr &sreqHigh,
1003 uint64_t *res,
1004 BaseTLB::Mode mode)
1005{
1006 translationStarted(true);
1007
1008 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1009 WholeTranslationState *state =
1010 new WholeTranslationState(req, NULL, res, mode);
1011
1012 // One translation if the request isn't split.
1013 DataTranslation<BaseDynInstPtr> *trans =
1014 new DataTranslation<BaseDynInstPtr>(this, state);
1015
1016 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1017
1018 if (!translationCompleted()) {
1019 // The translation isn't yet complete, so we can't possibly have a
1020 // fault. Overwrite any existing fault we might have from a previous
1021 // execution of this instruction (e.g. an uncachable load that
1022 // couldn't execute because it wasn't at the head of the ROB).
1023 fault = NoFault;
1024
1025 // Save memory requests.
1026 savedReq = state->mainReq;
1027 savedSreqLow = state->sreqLow;
1028 savedSreqHigh = state->sreqHigh;
1029 }
1030 } else {
1031 WholeTranslationState *state =
1032 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1033
1034 // Two translations when the request is split.
1035 DataTranslation<BaseDynInstPtr> *stransLow =
1036 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1037 DataTranslation<BaseDynInstPtr> *stransHigh =
1038 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1039
1040 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1041 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1042
1043 if (!translationCompleted()) {
1044 // The translation isn't yet complete, so we can't possibly have a
1045 // fault. Overwrite any existing fault we might have from a previous
1046 // execution of this instruction (e.g. an uncachable load that
1047 // couldn't execute because it wasn't at the head of the ROB).
1048 fault = NoFault;
1049
1050 // Save memory requests.
1051 savedReq = state->mainReq;
1052 savedSreqLow = state->sreqLow;
1053 savedSreqHigh = state->sreqHigh;
1054 }
1055 }
1056}
1057
1058template<class Impl>
1059inline void
1060BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1061{
1062 fault = state->getFault();
1063
1064 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1065
1066 if (fault == NoFault) {
1067 // save Paddr for a single req
1068 physEffAddrLow = state->getPaddr();
1069
1070 // case for the request that has been split
1071 if (state->isSplit) {
1072 physEffAddrLow = state->sreqLow->getPaddr();
1073 physEffAddrHigh = state->sreqHigh->getPaddr();
1074 }
1075
1076 memReqFlags = state->getFlags();
1077
1078 if (state->mainReq->isCondSwap()) {
1079 assert(state->res);
1080 state->mainReq->setExtraData(*state->res);
1081 }
1082
1083 } else {
1084 state->deleteReqs();
1085 }
1086 delete state;
1087
1088 translationCompleted(true);
1089}
1090
1091#endif // __CPU_BASE_DYN_INST_HH__
| 673 {
674 setScalarResult(val);
675 }
676
677 /** Record a vector register being set to a value */
678 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
679 {
680 setVecElemResult(val);
681 }
682
683 /** Records that one of the source registers is ready. */
684 void markSrcRegReady();
685
686 /** Marks a specific register as ready. */
687 void markSrcRegReady(RegIndex src_idx);
688
689 /** Returns if a source register is ready. */
690 bool isReadySrcRegIdx(int idx) const
691 {
692 return this->_readySrcRegIdx[idx];
693 }
694
695 /** Sets this instruction as completed. */
696 void setCompleted() { status.set(Completed); }
697
698 /** Returns whether or not this instruction is completed. */
699 bool isCompleted() const { return status[Completed]; }
700
701 /** Marks the result as ready. */
702 void setResultReady() { status.set(ResultReady); }
703
704 /** Returns whether or not the result is ready. */
705 bool isResultReady() const { return status[ResultReady]; }
706
707 /** Sets this instruction as ready to issue. */
708 void setCanIssue() { status.set(CanIssue); }
709
710 /** Returns whether or not this instruction is ready to issue. */
711 bool readyToIssue() const { return status[CanIssue]; }
712
713 /** Clears this instruction being able to issue. */
714 void clearCanIssue() { status.reset(CanIssue); }
715
716 /** Sets this instruction as issued from the IQ. */
717 void setIssued() { status.set(Issued); }
718
719 /** Returns whether or not this instruction has issued. */
720 bool isIssued() const { return status[Issued]; }
721
722 /** Clears this instruction as being issued. */
723 void clearIssued() { status.reset(Issued); }
724
725 /** Sets this instruction as executed. */
726 void setExecuted() { status.set(Executed); }
727
728 /** Returns whether or not this instruction has executed. */
729 bool isExecuted() const { return status[Executed]; }
730
731 /** Sets this instruction as ready to commit. */
732 void setCanCommit() { status.set(CanCommit); }
733
734 /** Clears this instruction as being ready to commit. */
735 void clearCanCommit() { status.reset(CanCommit); }
736
737 /** Returns whether or not this instruction is ready to commit. */
738 bool readyToCommit() const { return status[CanCommit]; }
739
740 void setAtCommit() { status.set(AtCommit); }
741
742 bool isAtCommit() { return status[AtCommit]; }
743
744 /** Sets this instruction as committed. */
745 void setCommitted() { status.set(Committed); }
746
747 /** Returns whether or not this instruction is committed. */
748 bool isCommitted() const { return status[Committed]; }
749
750 /** Sets this instruction as squashed. */
751 void setSquashed() { status.set(Squashed); }
752
753 /** Returns whether or not this instruction is squashed. */
754 bool isSquashed() const { return status[Squashed]; }
755
756 //Instruction Queue Entry
757 //-----------------------
758 /** Sets this instruction as a entry the IQ. */
759 void setInIQ() { status.set(IqEntry); }
760
761 /** Sets this instruction as a entry the IQ. */
762 void clearInIQ() { status.reset(IqEntry); }
763
764 /** Returns whether or not this instruction has issued. */
765 bool isInIQ() const { return status[IqEntry]; }
766
767 /** Sets this instruction as squashed in the IQ. */
768 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
769
770 /** Returns whether or not this instruction is squashed in the IQ. */
771 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
772
773
774 //Load / Store Queue Functions
775 //-----------------------
776 /** Sets this instruction as a entry the LSQ. */
777 void setInLSQ() { status.set(LsqEntry); }
778
779 /** Sets this instruction as a entry the LSQ. */
780 void removeInLSQ() { status.reset(LsqEntry); }
781
782 /** Returns whether or not this instruction is in the LSQ. */
783 bool isInLSQ() const { return status[LsqEntry]; }
784
785 /** Sets this instruction as squashed in the LSQ. */
786 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
787
788 /** Returns whether or not this instruction is squashed in the LSQ. */
789 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
790
791
792 //Reorder Buffer Functions
793 //-----------------------
794 /** Sets this instruction as a entry the ROB. */
795 void setInROB() { status.set(RobEntry); }
796
797 /** Sets this instruction as a entry the ROB. */
798 void clearInROB() { status.reset(RobEntry); }
799
800 /** Returns whether or not this instruction is in the ROB. */
801 bool isInROB() const { return status[RobEntry]; }
802
803 /** Sets this instruction as squashed in the ROB. */
804 void setSquashedInROB() { status.set(SquashedInROB); }
805
806 /** Returns whether or not this instruction is squashed in the ROB. */
807 bool isSquashedInROB() const { return status[SquashedInROB]; }
808
809 /** Read the PC state of this instruction. */
810 TheISA::PCState pcState() const { return pc; }
811
812 /** Set the PC state of this instruction. */
813 void pcState(const TheISA::PCState &val) { pc = val; }
814
815 /** Read the PC of this instruction. */
816 Addr instAddr() const { return pc.instAddr(); }
817
818 /** Read the PC of the next instruction. */
819 Addr nextInstAddr() const { return pc.nextInstAddr(); }
820
821 /**Read the micro PC of this instruction. */
822 Addr microPC() const { return pc.microPC(); }
823
824 bool readPredicate() const
825 {
826 return instFlags[Predicate];
827 }
828
829 void setPredicate(bool val)
830 {
831 instFlags[Predicate] = val;
832
833 if (traceData) {
834 traceData->setPredicate(val);
835 }
836 }
837
838 /** Sets the ASID. */
839 void setASID(short addr_space_id) { asid = addr_space_id; }
840
841 /** Sets the thread id. */
842 void setTid(ThreadID tid) { threadNumber = tid; }
843
844 /** Sets the pointer to the thread state. */
845 void setThreadState(ImplState *state) { thread = state; }
846
847 /** Returns the thread context. */
848 ThreadContext *tcBase() { return thread->getTC(); }
849
850 public:
851 /** Returns whether or not the eff. addr. source registers are ready. */
852 bool eaSrcsReady() const;
853
854 /** Is this instruction's memory access strictly ordered? */
855 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
856
857 /** Has this instruction generated a memory request. */
858 bool hasRequest() const { return instFlags[ReqMade]; }
859
860 /** Returns iterator to this instruction in the list of all insts. */
861 ListIt &getInstListIt() { return instListIt; }
862
863 /** Sets iterator for this instruction in the list of all insts. */
864 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
865
866 public:
867 /** Returns the number of consecutive store conditional failures. */
868 unsigned int readStCondFailures() const
869 { return thread->storeCondFailures; }
870
871 /** Sets the number of consecutive store conditional failures. */
872 void setStCondFailures(unsigned int sc_failures)
873 { thread->storeCondFailures = sc_failures; }
874
875 public:
876 // monitor/mwait funtions
877 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
878 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
879 void mwaitAtomic(ThreadContext *tc)
880 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
881 AddressMonitor *getAddrMonitor()
882 { return cpu->getCpuAddrMonitor(threadNumber); }
883};
884
885template<class Impl>
886Fault
887BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
888 Request::Flags flags)
889{
890 instFlags[ReqMade] = true;
891 RequestPtr req = NULL;
892 RequestPtr sreqLow = NULL;
893 RequestPtr sreqHigh = NULL;
894
895 if (instFlags[ReqMade] && translationStarted()) {
896 req = savedReq;
897 sreqLow = savedSreqLow;
898 sreqHigh = savedSreqHigh;
899 } else {
900 req = std::make_shared<Request>(
901 asid, addr, size, flags, masterId(),
902 this->pc.instAddr(), thread->contextId());
903
904 req->taskId(cpu->taskId());
905
906 // Only split the request if the ISA supports unaligned accesses.
907 if (TheISA::HasUnalignedMemAcc) {
908 splitRequest(req, sreqLow, sreqHigh);
909 }
910 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
911 }
912
913 if (translationCompleted()) {
914 if (fault == NoFault) {
915 effAddr = req->getVaddr();
916 effSize = size;
917 instFlags[EffAddrValid] = true;
918
919 if (cpu->checker) {
920 reqToVerify = std::make_shared<Request>(*req);
921 }
922 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
923 } else {
924 // Commit will have to clean up whatever happened. Set this
925 // instruction as executed.
926 this->setExecuted();
927 }
928 }
929
930 if (traceData)
931 traceData->setMem(addr, size, flags);
932
933 return fault;
934}
935
936template<class Impl>
937Fault
938BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
939 Request::Flags flags, uint64_t *res)
940{
941 if (traceData)
942 traceData->setMem(addr, size, flags);
943
944 instFlags[ReqMade] = true;
945 RequestPtr req = NULL;
946 RequestPtr sreqLow = NULL;
947 RequestPtr sreqHigh = NULL;
948
949 if (instFlags[ReqMade] && translationStarted()) {
950 req = savedReq;
951 sreqLow = savedSreqLow;
952 sreqHigh = savedSreqHigh;
953 } else {
954 req = std::make_shared<Request>(
955 asid, addr, size, flags, masterId(),
956 this->pc.instAddr(), thread->contextId());
957
958 req->taskId(cpu->taskId());
959
960 // Only split the request if the ISA supports unaligned accesses.
961 if (TheISA::HasUnalignedMemAcc) {
962 splitRequest(req, sreqLow, sreqHigh);
963 }
964 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
965 }
966
967 if (fault == NoFault && translationCompleted()) {
968 effAddr = req->getVaddr();
969 effSize = size;
970 instFlags[EffAddrValid] = true;
971
972 if (cpu->checker) {
973 reqToVerify = std::make_shared<Request>(*req);
974 }
975 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
976 }
977
978 return fault;
979}
980
981template<class Impl>
982inline void
983BaseDynInst<Impl>::splitRequest(const RequestPtr &req, RequestPtr &sreqLow,
984 RequestPtr &sreqHigh)
985{
986 // Check to see if the request crosses the next level block boundary.
987 unsigned block_size = cpu->cacheLineSize();
988 Addr addr = req->getVaddr();
989 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
990 assert(split_addr <= addr || split_addr - addr < block_size);
991
992 // Spans two blocks.
993 if (split_addr > addr) {
994 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
995 }
996}
997
998template<class Impl>
999inline void
1000BaseDynInst<Impl>::initiateTranslation(const RequestPtr &req,
1001 const RequestPtr &sreqLow,
1002 const RequestPtr &sreqHigh,
1003 uint64_t *res,
1004 BaseTLB::Mode mode)
1005{
1006 translationStarted(true);
1007
1008 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1009 WholeTranslationState *state =
1010 new WholeTranslationState(req, NULL, res, mode);
1011
1012 // One translation if the request isn't split.
1013 DataTranslation<BaseDynInstPtr> *trans =
1014 new DataTranslation<BaseDynInstPtr>(this, state);
1015
1016 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1017
1018 if (!translationCompleted()) {
1019 // The translation isn't yet complete, so we can't possibly have a
1020 // fault. Overwrite any existing fault we might have from a previous
1021 // execution of this instruction (e.g. an uncachable load that
1022 // couldn't execute because it wasn't at the head of the ROB).
1023 fault = NoFault;
1024
1025 // Save memory requests.
1026 savedReq = state->mainReq;
1027 savedSreqLow = state->sreqLow;
1028 savedSreqHigh = state->sreqHigh;
1029 }
1030 } else {
1031 WholeTranslationState *state =
1032 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1033
1034 // Two translations when the request is split.
1035 DataTranslation<BaseDynInstPtr> *stransLow =
1036 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1037 DataTranslation<BaseDynInstPtr> *stransHigh =
1038 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1039
1040 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1041 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1042
1043 if (!translationCompleted()) {
1044 // The translation isn't yet complete, so we can't possibly have a
1045 // fault. Overwrite any existing fault we might have from a previous
1046 // execution of this instruction (e.g. an uncachable load that
1047 // couldn't execute because it wasn't at the head of the ROB).
1048 fault = NoFault;
1049
1050 // Save memory requests.
1051 savedReq = state->mainReq;
1052 savedSreqLow = state->sreqLow;
1053 savedSreqHigh = state->sreqHigh;
1054 }
1055 }
1056}
1057
1058template<class Impl>
1059inline void
1060BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1061{
1062 fault = state->getFault();
1063
1064 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1065
1066 if (fault == NoFault) {
1067 // save Paddr for a single req
1068 physEffAddrLow = state->getPaddr();
1069
1070 // case for the request that has been split
1071 if (state->isSplit) {
1072 physEffAddrLow = state->sreqLow->getPaddr();
1073 physEffAddrHigh = state->sreqHigh->getPaddr();
1074 }
1075
1076 memReqFlags = state->getFlags();
1077
1078 if (state->mainReq->isCondSwap()) {
1079 assert(state->res);
1080 state->mainReq->setExtraData(*state->res);
1081 }
1082
1083 } else {
1084 state->deleteReqs();
1085 }
1086 delete state;
1087
1088 translationCompleted(true);
1089}
1090
1091#endif // __CPU_BASE_DYN_INST_HH__
|