1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81 public:
82 // Typedef for the CPU.
83 typedef typename Impl::CPUType ImplCPU;
84 typedef typename ImplCPU::ImplState ImplState;
85 using VecRegContainer = TheISA::VecRegContainer;
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 protected:
100 enum Status {
101 IqEntry, /// Instruction is in the IQ
102 RobEntry, /// Instruction is in the ROB
103 LsqEntry, /// Instruction is in the LSQ
104 Completed, /// Instruction has completed
105 ResultReady, /// Instruction has its result
106 CanIssue, /// Instruction can issue and execute
107 Issued, /// Instruction has issued
108 Executed, /// Instruction has executed
109 CanCommit, /// Instruction can commit
110 AtCommit, /// Instruction has reached commit
111 Committed, /// Instruction has committed
112 Squashed, /// Instruction is squashed
113 SquashedInIQ, /// Instruction is squashed in the IQ
114 SquashedInLSQ, /// Instruction is squashed in the LSQ
115 SquashedInROB, /// Instruction is squashed in the ROB
116 RecoverInst, /// Is a recover instruction
117 BlockingInst, /// Is a blocking instruction
118 ThreadsyncWait, /// Is a thread synchronization instruction
119 SerializeBefore, /// Needs to serialize on
120 /// instructions ahead of it
121 SerializeAfter, /// Needs to serialize instructions behind it
122 SerializeHandled, /// Serialization has been handled
123 NumStatus
124 };
125
126 enum Flags {
| 1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81 public:
82 // Typedef for the CPU.
83 typedef typename Impl::CPUType ImplCPU;
84 typedef typename ImplCPU::ImplState ImplState;
85 using VecRegContainer = TheISA::VecRegContainer;
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 protected:
100 enum Status {
101 IqEntry, /// Instruction is in the IQ
102 RobEntry, /// Instruction is in the ROB
103 LsqEntry, /// Instruction is in the LSQ
104 Completed, /// Instruction has completed
105 ResultReady, /// Instruction has its result
106 CanIssue, /// Instruction can issue and execute
107 Issued, /// Instruction has issued
108 Executed, /// Instruction has executed
109 CanCommit, /// Instruction can commit
110 AtCommit, /// Instruction has reached commit
111 Committed, /// Instruction has committed
112 Squashed, /// Instruction is squashed
113 SquashedInIQ, /// Instruction is squashed in the IQ
114 SquashedInLSQ, /// Instruction is squashed in the LSQ
115 SquashedInROB, /// Instruction is squashed in the ROB
116 RecoverInst, /// Is a recover instruction
117 BlockingInst, /// Is a blocking instruction
118 ThreadsyncWait, /// Is a thread synchronization instruction
119 SerializeBefore, /// Needs to serialize on
120 /// instructions ahead of it
121 SerializeAfter, /// Needs to serialize instructions behind it
122 SerializeHandled, /// Serialization has been handled
123 NumStatus
124 };
125
126 enum Flags {
|
278 ////////////////////////////////////////////
279 //
280 // INSTRUCTION EXECUTION
281 //
282 ////////////////////////////////////////////
283
284 void demapPage(Addr vaddr, uint64_t asn)
285 {
286 cpu->demapPage(vaddr, asn);
287 }
288 void demapInstPage(Addr vaddr, uint64_t asn)
289 {
290 cpu->demapPage(vaddr, asn);
291 }
292 void demapDataPage(Addr vaddr, uint64_t asn)
293 {
294 cpu->demapPage(vaddr, asn);
295 }
296
297 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
298
299 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
300 Request::Flags flags, uint64_t *res);
301
302 /** Splits a request in two if it crosses a dcache block. */
303 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
304 RequestPtr &sreqHigh);
305
306 /** Initiate a DTB address translation. */
307 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
308 RequestPtr sreqHigh, uint64_t *res,
309 BaseTLB::Mode mode);
310
311 /** Finish a DTB address translation. */
312 void finishTranslation(WholeTranslationState *state);
313
314 /** True if the DTB address translation has started. */
315 bool translationStarted() const { return instFlags[TranslationStarted]; }
316 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
317
318 /** True if the DTB address translation has completed. */
319 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
320 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
321
322 /** True if this address was found to match a previous load and they issued
323 * out of order. If that happend, then it's only a problem if an incoming
324 * snoop invalidate modifies the line, in which case we need to squash.
325 * If nothing modified the line the order doesn't matter.
326 */
327 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
328 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
329
330 /** True if the address hit a external snoop while sitting in the LSQ.
331 * If this is true and a older instruction sees it, this instruction must
332 * reexecute
333 */
334 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
335 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
336
337 /**
338 * Returns true if the DTB address translation is being delayed due to a hw
339 * page table walk.
340 */
341 bool isTranslationDelayed() const
342 {
343 return (translationStarted() && !translationCompleted());
344 }
345
346 public:
347#ifdef DEBUG
348 void dumpSNList();
349#endif
350
351 /** Returns the physical register index of the i'th destination
352 * register.
353 */
354 PhysRegIdPtr renamedDestRegIdx(int idx) const
355 {
356 return _destRegIdx[idx];
357 }
358
359 /** Returns the physical register index of the i'th source register. */
360 PhysRegIdPtr renamedSrcRegIdx(int idx) const
361 {
362 assert(TheISA::MaxInstSrcRegs > idx);
363 return _srcRegIdx[idx];
364 }
365
366 /** Returns the flattened register index of the i'th destination
367 * register.
368 */
369 const RegId& flattenedDestRegIdx(int idx) const
370 {
371 return _flatDestRegIdx[idx];
372 }
373
374 /** Returns the physical register index of the previous physical register
375 * that remapped to the same logical register index.
376 */
377 PhysRegIdPtr prevDestRegIdx(int idx) const
378 {
379 return _prevDestRegIdx[idx];
380 }
381
382 /** Renames a destination register to a physical register. Also records
383 * the previous physical register that the logical register mapped to.
384 */
385 void renameDestReg(int idx,
386 PhysRegIdPtr renamed_dest,
387 PhysRegIdPtr previous_rename)
388 {
389 _destRegIdx[idx] = renamed_dest;
390 _prevDestRegIdx[idx] = previous_rename;
391 }
392
393 /** Renames a source logical register to the physical register which
394 * has/will produce that logical register's result.
395 * @todo: add in whether or not the source register is ready.
396 */
397 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
398 {
399 _srcRegIdx[idx] = renamed_src;
400 }
401
402 /** Flattens a destination architectural register index into a logical
403 * index.
404 */
405 void flattenDestReg(int idx, const RegId& flattened_dest)
406 {
407 _flatDestRegIdx[idx] = flattened_dest;
408 }
409 /** BaseDynInst constructor given a binary instruction.
410 * @param staticInst A StaticInstPtr to the underlying instruction.
411 * @param pc The PC state for the instruction.
412 * @param predPC The predicted next PC state for the instruction.
413 * @param seq_num The sequence number of the instruction.
414 * @param cpu Pointer to the instruction's CPU.
415 */
416 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
417 TheISA::PCState pc, TheISA::PCState predPC,
418 InstSeqNum seq_num, ImplCPU *cpu);
419
420 /** BaseDynInst constructor given a StaticInst pointer.
421 * @param _staticInst The StaticInst for this BaseDynInst.
422 */
423 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
424
425 /** BaseDynInst destructor. */
426 ~BaseDynInst();
427
428 private:
429 /** Function to initialize variables in the constructors. */
430 void initVars();
431
432 public:
433 /** Dumps out contents of this BaseDynInst. */
434 void dump();
435
436 /** Dumps out contents of this BaseDynInst into given string. */
437 void dump(std::string &outstring);
438
439 /** Read this CPU's ID. */
440 int cpuId() const { return cpu->cpuId(); }
441
442 /** Read this CPU's Socket ID. */
443 uint32_t socketId() const { return cpu->socketId(); }
444
445 /** Read this CPU's data requestor ID */
446 MasterID masterId() const { return cpu->dataMasterId(); }
447
448 /** Read this context's system-wide ID **/
449 ContextID contextId() const { return thread->contextId(); }
450
451 /** Returns the fault type. */
452 Fault getFault() const { return fault; }
453
454 /** Checks whether or not this instruction has had its branch target
455 * calculated yet. For now it is not utilized and is hacked to be
456 * always false.
457 * @todo: Actually use this instruction.
458 */
459 bool doneTargCalc() { return false; }
460
461 /** Set the predicted target of this current instruction. */
462 void setPredTarg(const TheISA::PCState &_predPC)
463 {
464 predPC = _predPC;
465 }
466
467 const TheISA::PCState &readPredTarg() { return predPC; }
468
469 /** Returns the predicted PC immediately after the branch. */
470 Addr predInstAddr() { return predPC.instAddr(); }
471
472 /** Returns the predicted PC two instructions after the branch */
473 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
474
475 /** Returns the predicted micro PC after the branch */
476 Addr predMicroPC() { return predPC.microPC(); }
477
478 /** Returns whether the instruction was predicted taken or not. */
479 bool readPredTaken()
480 {
481 return instFlags[PredTaken];
482 }
483
484 void setPredTaken(bool predicted_taken)
485 {
486 instFlags[PredTaken] = predicted_taken;
487 }
488
489 /** Returns whether the instruction mispredicted. */
490 bool mispredicted()
491 {
492 TheISA::PCState tempPC = pc;
493 TheISA::advancePC(tempPC, staticInst);
494 return !(tempPC == predPC);
495 }
496
497 //
498 // Instruction types. Forward checks to StaticInst object.
499 //
500 bool isNop() const { return staticInst->isNop(); }
501 bool isMemRef() const { return staticInst->isMemRef(); }
502 bool isLoad() const { return staticInst->isLoad(); }
503 bool isStore() const { return staticInst->isStore(); }
504 bool isStoreConditional() const
505 { return staticInst->isStoreConditional(); }
506 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
507 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
508 bool isInteger() const { return staticInst->isInteger(); }
509 bool isFloating() const { return staticInst->isFloating(); }
510 bool isVector() const { return staticInst->isVector(); }
511 bool isControl() const { return staticInst->isControl(); }
512 bool isCall() const { return staticInst->isCall(); }
513 bool isReturn() const { return staticInst->isReturn(); }
514 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
515 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
516 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
517 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
518 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
519 bool isThreadSync() const { return staticInst->isThreadSync(); }
520 bool isSerializing() const { return staticInst->isSerializing(); }
521 bool isSerializeBefore() const
522 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
523 bool isSerializeAfter() const
524 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
525 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
526 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
527 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
528 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
529 bool isQuiesce() const { return staticInst->isQuiesce(); }
530 bool isIprAccess() const { return staticInst->isIprAccess(); }
531 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
532 bool isSyscall() const { return staticInst->isSyscall(); }
533 bool isMacroop() const { return staticInst->isMacroop(); }
534 bool isMicroop() const { return staticInst->isMicroop(); }
535 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
536 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
537 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
538 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
539
540 /** Temporarily sets this instruction as a serialize before instruction. */
541 void setSerializeBefore() { status.set(SerializeBefore); }
542
543 /** Clears the serializeBefore part of this instruction. */
544 void clearSerializeBefore() { status.reset(SerializeBefore); }
545
546 /** Checks if this serializeBefore is only temporarily set. */
547 bool isTempSerializeBefore() { return status[SerializeBefore]; }
548
549 /** Temporarily sets this instruction as a serialize after instruction. */
550 void setSerializeAfter() { status.set(SerializeAfter); }
551
552 /** Clears the serializeAfter part of this instruction.*/
553 void clearSerializeAfter() { status.reset(SerializeAfter); }
554
555 /** Checks if this serializeAfter is only temporarily set. */
556 bool isTempSerializeAfter() { return status[SerializeAfter]; }
557
558 /** Sets the serialization part of this instruction as handled. */
559 void setSerializeHandled() { status.set(SerializeHandled); }
560
561 /** Checks if the serialization part of this instruction has been
562 * handled. This does not apply to the temporary serializing
563 * state; it only applies to this instruction's own permanent
564 * serializing state.
565 */
566 bool isSerializeHandled() { return status[SerializeHandled]; }
567
568 /** Returns the opclass of this instruction. */
569 OpClass opClass() const { return staticInst->opClass(); }
570
571 /** Returns the branch target address. */
572 TheISA::PCState branchTarget() const
573 { return staticInst->branchTarget(pc); }
574
575 /** Returns the number of source registers. */
576 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
577
578 /** Returns the number of destination registers. */
579 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
580
581 // the following are used to track physical register usage
582 // for machines with separate int & FP reg files
583 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
584 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
585 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
586 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
587 int8_t numVecElemDestRegs() const {
588 return staticInst->numVecElemDestRegs();
589 }
590
591 /** Returns the logical register index of the i'th destination register. */
592 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
593
594 /** Returns the logical register index of the i'th source register. */
595 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
596
597 /** Return the size of the instResult queue. */
598 uint8_t resultSize() { return instResult.size(); }
599
600 /** Pops a result off the instResult queue.
601 * If the result stack is empty, return the default value.
602 * */
603 InstResult popResult(InstResult dflt = InstResult())
604 {
605 if (!instResult.empty()) {
606 InstResult t = instResult.front();
607 instResult.pop();
608 return t;
609 }
610 return dflt;
611 }
612
613 /** Pushes a result onto the instResult queue. */
614 /** @{ */
615 /** Scalar result. */
616 template<typename T>
617 void setScalarResult(T&& t)
618 {
619 if (instFlags[RecordResult]) {
620 instResult.push(InstResult(std::forward<T>(t),
621 InstResult::ResultType::Scalar));
622 }
623 }
624
625 /** Full vector result. */
626 template<typename T>
627 void setVecResult(T&& t)
628 {
629 if (instFlags[RecordResult]) {
630 instResult.push(InstResult(std::forward<T>(t),
631 InstResult::ResultType::VecReg));
632 }
633 }
634
635 /** Vector element result. */
636 template<typename T>
637 void setVecElemResult(T&& t)
638 {
639 if (instFlags[RecordResult]) {
640 instResult.push(InstResult(std::forward<T>(t),
641 InstResult::ResultType::VecElem));
642 }
643 }
644 /** @} */
645
646 /** Records an integer register being set to a value. */
647 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
648 {
649 setScalarResult(val);
650 }
651
652 /** Records a CC register being set to a value. */
653 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
654 {
655 setScalarResult(val);
656 }
657
658 /** Records an fp register being set to a value. */
659 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
660 {
661 setScalarResult(val);
662 }
663
664 /** Record a vector register being set to a value */
665 void setVecRegOperand(const StaticInst *si, int idx,
666 const VecRegContainer& val)
667 {
668 setVecResult(val);
669 }
670
671 /** Records an fp register being set to an integer value. */
672 void
673 setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
674 {
675 setScalarResult(val);
676 }
677
678 /** Record a vector register being set to a value */
679 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
680 {
681 setVecElemResult(val);
682 }
683
684 /** Records that one of the source registers is ready. */
685 void markSrcRegReady();
686
687 /** Marks a specific register as ready. */
688 void markSrcRegReady(RegIndex src_idx);
689
690 /** Returns if a source register is ready. */
691 bool isReadySrcRegIdx(int idx) const
692 {
693 return this->_readySrcRegIdx[idx];
694 }
695
696 /** Sets this instruction as completed. */
697 void setCompleted() { status.set(Completed); }
698
699 /** Returns whether or not this instruction is completed. */
700 bool isCompleted() const { return status[Completed]; }
701
702 /** Marks the result as ready. */
703 void setResultReady() { status.set(ResultReady); }
704
705 /** Returns whether or not the result is ready. */
706 bool isResultReady() const { return status[ResultReady]; }
707
708 /** Sets this instruction as ready to issue. */
709 void setCanIssue() { status.set(CanIssue); }
710
711 /** Returns whether or not this instruction is ready to issue. */
712 bool readyToIssue() const { return status[CanIssue]; }
713
714 /** Clears this instruction being able to issue. */
715 void clearCanIssue() { status.reset(CanIssue); }
716
717 /** Sets this instruction as issued from the IQ. */
718 void setIssued() { status.set(Issued); }
719
720 /** Returns whether or not this instruction has issued. */
721 bool isIssued() const { return status[Issued]; }
722
723 /** Clears this instruction as being issued. */
724 void clearIssued() { status.reset(Issued); }
725
726 /** Sets this instruction as executed. */
727 void setExecuted() { status.set(Executed); }
728
729 /** Returns whether or not this instruction has executed. */
730 bool isExecuted() const { return status[Executed]; }
731
732 /** Sets this instruction as ready to commit. */
733 void setCanCommit() { status.set(CanCommit); }
734
735 /** Clears this instruction as being ready to commit. */
736 void clearCanCommit() { status.reset(CanCommit); }
737
738 /** Returns whether or not this instruction is ready to commit. */
739 bool readyToCommit() const { return status[CanCommit]; }
740
741 void setAtCommit() { status.set(AtCommit); }
742
743 bool isAtCommit() { return status[AtCommit]; }
744
745 /** Sets this instruction as committed. */
746 void setCommitted() { status.set(Committed); }
747
748 /** Returns whether or not this instruction is committed. */
749 bool isCommitted() const { return status[Committed]; }
750
751 /** Sets this instruction as squashed. */
752 void setSquashed() { status.set(Squashed); }
753
754 /** Returns whether or not this instruction is squashed. */
755 bool isSquashed() const { return status[Squashed]; }
756
757 //Instruction Queue Entry
758 //-----------------------
759 /** Sets this instruction as a entry the IQ. */
760 void setInIQ() { status.set(IqEntry); }
761
762 /** Sets this instruction as a entry the IQ. */
763 void clearInIQ() { status.reset(IqEntry); }
764
765 /** Returns whether or not this instruction has issued. */
766 bool isInIQ() const { return status[IqEntry]; }
767
768 /** Sets this instruction as squashed in the IQ. */
769 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
770
771 /** Returns whether or not this instruction is squashed in the IQ. */
772 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
773
774
775 //Load / Store Queue Functions
776 //-----------------------
777 /** Sets this instruction as a entry the LSQ. */
778 void setInLSQ() { status.set(LsqEntry); }
779
780 /** Sets this instruction as a entry the LSQ. */
781 void removeInLSQ() { status.reset(LsqEntry); }
782
783 /** Returns whether or not this instruction is in the LSQ. */
784 bool isInLSQ() const { return status[LsqEntry]; }
785
786 /** Sets this instruction as squashed in the LSQ. */
787 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
788
789 /** Returns whether or not this instruction is squashed in the LSQ. */
790 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
791
792
793 //Reorder Buffer Functions
794 //-----------------------
795 /** Sets this instruction as a entry the ROB. */
796 void setInROB() { status.set(RobEntry); }
797
798 /** Sets this instruction as a entry the ROB. */
799 void clearInROB() { status.reset(RobEntry); }
800
801 /** Returns whether or not this instruction is in the ROB. */
802 bool isInROB() const { return status[RobEntry]; }
803
804 /** Sets this instruction as squashed in the ROB. */
805 void setSquashedInROB() { status.set(SquashedInROB); }
806
807 /** Returns whether or not this instruction is squashed in the ROB. */
808 bool isSquashedInROB() const { return status[SquashedInROB]; }
809
810 /** Read the PC state of this instruction. */
811 TheISA::PCState pcState() const { return pc; }
812
813 /** Set the PC state of this instruction. */
814 void pcState(const TheISA::PCState &val) { pc = val; }
815
816 /** Read the PC of this instruction. */
817 Addr instAddr() const { return pc.instAddr(); }
818
819 /** Read the PC of the next instruction. */
820 Addr nextInstAddr() const { return pc.nextInstAddr(); }
821
822 /**Read the micro PC of this instruction. */
823 Addr microPC() const { return pc.microPC(); }
824
825 bool readPredicate()
826 {
827 return instFlags[Predicate];
828 }
829
830 void setPredicate(bool val)
831 {
832 instFlags[Predicate] = val;
833
834 if (traceData) {
835 traceData->setPredicate(val);
836 }
837 }
838
839 /** Sets the ASID. */
840 void setASID(short addr_space_id) { asid = addr_space_id; }
841
842 /** Sets the thread id. */
843 void setTid(ThreadID tid) { threadNumber = tid; }
844
845 /** Sets the pointer to the thread state. */
846 void setThreadState(ImplState *state) { thread = state; }
847
848 /** Returns the thread context. */
849 ThreadContext *tcBase() { return thread->getTC(); }
850
851 public:
852 /** Returns whether or not the eff. addr. source registers are ready. */
853 bool eaSrcsReady();
854
855 /** Is this instruction's memory access strictly ordered? */
856 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
857
858 /** Has this instruction generated a memory request. */
859 bool hasRequest() { return instFlags[ReqMade]; }
860
861 /** Returns iterator to this instruction in the list of all insts. */
862 ListIt &getInstListIt() { return instListIt; }
863
864 /** Sets iterator for this instruction in the list of all insts. */
865 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
866
867 public:
868 /** Returns the number of consecutive store conditional failures. */
869 unsigned int readStCondFailures() const
870 { return thread->storeCondFailures; }
871
872 /** Sets the number of consecutive store conditional failures. */
873 void setStCondFailures(unsigned int sc_failures)
874 { thread->storeCondFailures = sc_failures; }
875
876 public:
877 // monitor/mwait funtions
878 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
879 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
880 void mwaitAtomic(ThreadContext *tc)
881 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
882 AddressMonitor *getAddrMonitor()
883 { return cpu->getCpuAddrMonitor(threadNumber); }
884};
885
886template<class Impl>
887Fault
888BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
889 Request::Flags flags)
890{
891 instFlags[ReqMade] = true;
892 Request *req = NULL;
893 Request *sreqLow = NULL;
894 Request *sreqHigh = NULL;
895
896 if (instFlags[ReqMade] && translationStarted()) {
897 req = savedReq;
898 sreqLow = savedSreqLow;
899 sreqHigh = savedSreqHigh;
900 } else {
901 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
902 thread->contextId());
903
904 req->taskId(cpu->taskId());
905
906 // Only split the request if the ISA supports unaligned accesses.
907 if (TheISA::HasUnalignedMemAcc) {
908 splitRequest(req, sreqLow, sreqHigh);
909 }
910 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
911 }
912
913 if (translationCompleted()) {
914 if (fault == NoFault) {
915 effAddr = req->getVaddr();
916 effSize = size;
917 instFlags[EffAddrValid] = true;
918
919 if (cpu->checker) {
920 if (reqToVerify != NULL) {
921 delete reqToVerify;
922 }
923 reqToVerify = new Request(*req);
924 }
925 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
926 } else {
927 // Commit will have to clean up whatever happened. Set this
928 // instruction as executed.
929 this->setExecuted();
930 }
931 }
932
933 if (traceData)
934 traceData->setMem(addr, size, flags);
935
936 return fault;
937}
938
939template<class Impl>
940Fault
941BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
942 Request::Flags flags, uint64_t *res)
943{
944 if (traceData)
945 traceData->setMem(addr, size, flags);
946
947 instFlags[ReqMade] = true;
948 Request *req = NULL;
949 Request *sreqLow = NULL;
950 Request *sreqHigh = NULL;
951
952 if (instFlags[ReqMade] && translationStarted()) {
953 req = savedReq;
954 sreqLow = savedSreqLow;
955 sreqHigh = savedSreqHigh;
956 } else {
957 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
958 thread->contextId());
959
960 req->taskId(cpu->taskId());
961
962 // Only split the request if the ISA supports unaligned accesses.
963 if (TheISA::HasUnalignedMemAcc) {
964 splitRequest(req, sreqLow, sreqHigh);
965 }
966 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
967 }
968
969 if (fault == NoFault && translationCompleted()) {
970 effAddr = req->getVaddr();
971 effSize = size;
972 instFlags[EffAddrValid] = true;
973
974 if (cpu->checker) {
975 if (reqToVerify != NULL) {
976 delete reqToVerify;
977 }
978 reqToVerify = new Request(*req);
979 }
980 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
981 }
982
983 return fault;
984}
985
986template<class Impl>
987inline void
988BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
989 RequestPtr &sreqHigh)
990{
991 // Check to see if the request crosses the next level block boundary.
992 unsigned block_size = cpu->cacheLineSize();
993 Addr addr = req->getVaddr();
994 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
995 assert(split_addr <= addr || split_addr - addr < block_size);
996
997 // Spans two blocks.
998 if (split_addr > addr) {
999 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1000 }
1001}
1002
1003template<class Impl>
1004inline void
1005BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1006 RequestPtr sreqHigh, uint64_t *res,
1007 BaseTLB::Mode mode)
1008{
1009 translationStarted(true);
1010
1011 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, NULL, res, mode);
1014
1015 // One translation if the request isn't split.
1016 DataTranslation<BaseDynInstPtr> *trans =
1017 new DataTranslation<BaseDynInstPtr>(this, state);
1018
1019 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1020
1021 if (!translationCompleted()) {
1022 // The translation isn't yet complete, so we can't possibly have a
1023 // fault. Overwrite any existing fault we might have from a previous
1024 // execution of this instruction (e.g. an uncachable load that
1025 // couldn't execute because it wasn't at the head of the ROB).
1026 fault = NoFault;
1027
1028 // Save memory requests.
1029 savedReq = state->mainReq;
1030 savedSreqLow = state->sreqLow;
1031 savedSreqHigh = state->sreqHigh;
1032 }
1033 } else {
1034 WholeTranslationState *state =
1035 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1036
1037 // Two translations when the request is split.
1038 DataTranslation<BaseDynInstPtr> *stransLow =
1039 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1040 DataTranslation<BaseDynInstPtr> *stransHigh =
1041 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1042
1043 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1044 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1045
1046 if (!translationCompleted()) {
1047 // The translation isn't yet complete, so we can't possibly have a
1048 // fault. Overwrite any existing fault we might have from a previous
1049 // execution of this instruction (e.g. an uncachable load that
1050 // couldn't execute because it wasn't at the head of the ROB).
1051 fault = NoFault;
1052
1053 // Save memory requests.
1054 savedReq = state->mainReq;
1055 savedSreqLow = state->sreqLow;
1056 savedSreqHigh = state->sreqHigh;
1057 }
1058 }
1059}
1060
1061template<class Impl>
1062inline void
1063BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1064{
1065 fault = state->getFault();
1066
1067 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1068
1069 if (fault == NoFault) {
1070 // save Paddr for a single req
1071 physEffAddrLow = state->getPaddr();
1072
1073 // case for the request that has been split
1074 if (state->isSplit) {
1075 physEffAddrLow = state->sreqLow->getPaddr();
1076 physEffAddrHigh = state->sreqHigh->getPaddr();
1077 }
1078
1079 memReqFlags = state->getFlags();
1080
1081 if (state->mainReq->isCondSwap()) {
1082 assert(state->res);
1083 state->mainReq->setExtraData(*state->res);
1084 }
1085
1086 } else {
1087 state->deleteReqs();
1088 }
1089 delete state;
1090
1091 translationCompleted(true);
1092}
1093
1094#endif // __CPU_BASE_DYN_INST_HH__
| 282 ////////////////////////////////////////////
283 //
284 // INSTRUCTION EXECUTION
285 //
286 ////////////////////////////////////////////
287
288 void demapPage(Addr vaddr, uint64_t asn)
289 {
290 cpu->demapPage(vaddr, asn);
291 }
292 void demapInstPage(Addr vaddr, uint64_t asn)
293 {
294 cpu->demapPage(vaddr, asn);
295 }
296 void demapDataPage(Addr vaddr, uint64_t asn)
297 {
298 cpu->demapPage(vaddr, asn);
299 }
300
301 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302
303 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
304 Request::Flags flags, uint64_t *res);
305
306 /** Splits a request in two if it crosses a dcache block. */
307 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
308 RequestPtr &sreqHigh);
309
310 /** Initiate a DTB address translation. */
311 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
312 RequestPtr sreqHigh, uint64_t *res,
313 BaseTLB::Mode mode);
314
315 /** Finish a DTB address translation. */
316 void finishTranslation(WholeTranslationState *state);
317
318 /** True if the DTB address translation has started. */
319 bool translationStarted() const { return instFlags[TranslationStarted]; }
320 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
321
322 /** True if the DTB address translation has completed. */
323 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
324 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
325
326 /** True if this address was found to match a previous load and they issued
327 * out of order. If that happend, then it's only a problem if an incoming
328 * snoop invalidate modifies the line, in which case we need to squash.
329 * If nothing modified the line the order doesn't matter.
330 */
331 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
332 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
333
334 /** True if the address hit a external snoop while sitting in the LSQ.
335 * If this is true and a older instruction sees it, this instruction must
336 * reexecute
337 */
338 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
339 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
340
341 /**
342 * Returns true if the DTB address translation is being delayed due to a hw
343 * page table walk.
344 */
345 bool isTranslationDelayed() const
346 {
347 return (translationStarted() && !translationCompleted());
348 }
349
350 public:
351#ifdef DEBUG
352 void dumpSNList();
353#endif
354
355 /** Returns the physical register index of the i'th destination
356 * register.
357 */
358 PhysRegIdPtr renamedDestRegIdx(int idx) const
359 {
360 return _destRegIdx[idx];
361 }
362
363 /** Returns the physical register index of the i'th source register. */
364 PhysRegIdPtr renamedSrcRegIdx(int idx) const
365 {
366 assert(TheISA::MaxInstSrcRegs > idx);
367 return _srcRegIdx[idx];
368 }
369
370 /** Returns the flattened register index of the i'th destination
371 * register.
372 */
373 const RegId& flattenedDestRegIdx(int idx) const
374 {
375 return _flatDestRegIdx[idx];
376 }
377
378 /** Returns the physical register index of the previous physical register
379 * that remapped to the same logical register index.
380 */
381 PhysRegIdPtr prevDestRegIdx(int idx) const
382 {
383 return _prevDestRegIdx[idx];
384 }
385
386 /** Renames a destination register to a physical register. Also records
387 * the previous physical register that the logical register mapped to.
388 */
389 void renameDestReg(int idx,
390 PhysRegIdPtr renamed_dest,
391 PhysRegIdPtr previous_rename)
392 {
393 _destRegIdx[idx] = renamed_dest;
394 _prevDestRegIdx[idx] = previous_rename;
395 }
396
397 /** Renames a source logical register to the physical register which
398 * has/will produce that logical register's result.
399 * @todo: add in whether or not the source register is ready.
400 */
401 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
402 {
403 _srcRegIdx[idx] = renamed_src;
404 }
405
406 /** Flattens a destination architectural register index into a logical
407 * index.
408 */
409 void flattenDestReg(int idx, const RegId& flattened_dest)
410 {
411 _flatDestRegIdx[idx] = flattened_dest;
412 }
413 /** BaseDynInst constructor given a binary instruction.
414 * @param staticInst A StaticInstPtr to the underlying instruction.
415 * @param pc The PC state for the instruction.
416 * @param predPC The predicted next PC state for the instruction.
417 * @param seq_num The sequence number of the instruction.
418 * @param cpu Pointer to the instruction's CPU.
419 */
420 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
421 TheISA::PCState pc, TheISA::PCState predPC,
422 InstSeqNum seq_num, ImplCPU *cpu);
423
424 /** BaseDynInst constructor given a StaticInst pointer.
425 * @param _staticInst The StaticInst for this BaseDynInst.
426 */
427 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
428
429 /** BaseDynInst destructor. */
430 ~BaseDynInst();
431
432 private:
433 /** Function to initialize variables in the constructors. */
434 void initVars();
435
436 public:
437 /** Dumps out contents of this BaseDynInst. */
438 void dump();
439
440 /** Dumps out contents of this BaseDynInst into given string. */
441 void dump(std::string &outstring);
442
443 /** Read this CPU's ID. */
444 int cpuId() const { return cpu->cpuId(); }
445
446 /** Read this CPU's Socket ID. */
447 uint32_t socketId() const { return cpu->socketId(); }
448
449 /** Read this CPU's data requestor ID */
450 MasterID masterId() const { return cpu->dataMasterId(); }
451
452 /** Read this context's system-wide ID **/
453 ContextID contextId() const { return thread->contextId(); }
454
455 /** Returns the fault type. */
456 Fault getFault() const { return fault; }
457
458 /** Checks whether or not this instruction has had its branch target
459 * calculated yet. For now it is not utilized and is hacked to be
460 * always false.
461 * @todo: Actually use this instruction.
462 */
463 bool doneTargCalc() { return false; }
464
465 /** Set the predicted target of this current instruction. */
466 void setPredTarg(const TheISA::PCState &_predPC)
467 {
468 predPC = _predPC;
469 }
470
471 const TheISA::PCState &readPredTarg() { return predPC; }
472
473 /** Returns the predicted PC immediately after the branch. */
474 Addr predInstAddr() { return predPC.instAddr(); }
475
476 /** Returns the predicted PC two instructions after the branch */
477 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
478
479 /** Returns the predicted micro PC after the branch */
480 Addr predMicroPC() { return predPC.microPC(); }
481
482 /** Returns whether the instruction was predicted taken or not. */
483 bool readPredTaken()
484 {
485 return instFlags[PredTaken];
486 }
487
488 void setPredTaken(bool predicted_taken)
489 {
490 instFlags[PredTaken] = predicted_taken;
491 }
492
493 /** Returns whether the instruction mispredicted. */
494 bool mispredicted()
495 {
496 TheISA::PCState tempPC = pc;
497 TheISA::advancePC(tempPC, staticInst);
498 return !(tempPC == predPC);
499 }
500
501 //
502 // Instruction types. Forward checks to StaticInst object.
503 //
504 bool isNop() const { return staticInst->isNop(); }
505 bool isMemRef() const { return staticInst->isMemRef(); }
506 bool isLoad() const { return staticInst->isLoad(); }
507 bool isStore() const { return staticInst->isStore(); }
508 bool isStoreConditional() const
509 { return staticInst->isStoreConditional(); }
510 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
511 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
512 bool isInteger() const { return staticInst->isInteger(); }
513 bool isFloating() const { return staticInst->isFloating(); }
514 bool isVector() const { return staticInst->isVector(); }
515 bool isControl() const { return staticInst->isControl(); }
516 bool isCall() const { return staticInst->isCall(); }
517 bool isReturn() const { return staticInst->isReturn(); }
518 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
519 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
520 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
521 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
522 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
523 bool isThreadSync() const { return staticInst->isThreadSync(); }
524 bool isSerializing() const { return staticInst->isSerializing(); }
525 bool isSerializeBefore() const
526 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
527 bool isSerializeAfter() const
528 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
529 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
530 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
531 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
532 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
533 bool isQuiesce() const { return staticInst->isQuiesce(); }
534 bool isIprAccess() const { return staticInst->isIprAccess(); }
535 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
536 bool isSyscall() const { return staticInst->isSyscall(); }
537 bool isMacroop() const { return staticInst->isMacroop(); }
538 bool isMicroop() const { return staticInst->isMicroop(); }
539 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
540 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
541 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
542 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
543
544 /** Temporarily sets this instruction as a serialize before instruction. */
545 void setSerializeBefore() { status.set(SerializeBefore); }
546
547 /** Clears the serializeBefore part of this instruction. */
548 void clearSerializeBefore() { status.reset(SerializeBefore); }
549
550 /** Checks if this serializeBefore is only temporarily set. */
551 bool isTempSerializeBefore() { return status[SerializeBefore]; }
552
553 /** Temporarily sets this instruction as a serialize after instruction. */
554 void setSerializeAfter() { status.set(SerializeAfter); }
555
556 /** Clears the serializeAfter part of this instruction.*/
557 void clearSerializeAfter() { status.reset(SerializeAfter); }
558
559 /** Checks if this serializeAfter is only temporarily set. */
560 bool isTempSerializeAfter() { return status[SerializeAfter]; }
561
562 /** Sets the serialization part of this instruction as handled. */
563 void setSerializeHandled() { status.set(SerializeHandled); }
564
565 /** Checks if the serialization part of this instruction has been
566 * handled. This does not apply to the temporary serializing
567 * state; it only applies to this instruction's own permanent
568 * serializing state.
569 */
570 bool isSerializeHandled() { return status[SerializeHandled]; }
571
572 /** Returns the opclass of this instruction. */
573 OpClass opClass() const { return staticInst->opClass(); }
574
575 /** Returns the branch target address. */
576 TheISA::PCState branchTarget() const
577 { return staticInst->branchTarget(pc); }
578
579 /** Returns the number of source registers. */
580 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
581
582 /** Returns the number of destination registers. */
583 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
584
585 // the following are used to track physical register usage
586 // for machines with separate int & FP reg files
587 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
588 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
589 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
590 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
591 int8_t numVecElemDestRegs() const {
592 return staticInst->numVecElemDestRegs();
593 }
594
595 /** Returns the logical register index of the i'th destination register. */
596 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
597
598 /** Returns the logical register index of the i'th source register. */
599 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
600
601 /** Return the size of the instResult queue. */
602 uint8_t resultSize() { return instResult.size(); }
603
604 /** Pops a result off the instResult queue.
605 * If the result stack is empty, return the default value.
606 * */
607 InstResult popResult(InstResult dflt = InstResult())
608 {
609 if (!instResult.empty()) {
610 InstResult t = instResult.front();
611 instResult.pop();
612 return t;
613 }
614 return dflt;
615 }
616
617 /** Pushes a result onto the instResult queue. */
618 /** @{ */
619 /** Scalar result. */
620 template<typename T>
621 void setScalarResult(T&& t)
622 {
623 if (instFlags[RecordResult]) {
624 instResult.push(InstResult(std::forward<T>(t),
625 InstResult::ResultType::Scalar));
626 }
627 }
628
629 /** Full vector result. */
630 template<typename T>
631 void setVecResult(T&& t)
632 {
633 if (instFlags[RecordResult]) {
634 instResult.push(InstResult(std::forward<T>(t),
635 InstResult::ResultType::VecReg));
636 }
637 }
638
639 /** Vector element result. */
640 template<typename T>
641 void setVecElemResult(T&& t)
642 {
643 if (instFlags[RecordResult]) {
644 instResult.push(InstResult(std::forward<T>(t),
645 InstResult::ResultType::VecElem));
646 }
647 }
648 /** @} */
649
650 /** Records an integer register being set to a value. */
651 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
652 {
653 setScalarResult(val);
654 }
655
656 /** Records a CC register being set to a value. */
657 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
658 {
659 setScalarResult(val);
660 }
661
662 /** Records an fp register being set to a value. */
663 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
664 {
665 setScalarResult(val);
666 }
667
668 /** Record a vector register being set to a value */
669 void setVecRegOperand(const StaticInst *si, int idx,
670 const VecRegContainer& val)
671 {
672 setVecResult(val);
673 }
674
675 /** Records an fp register being set to an integer value. */
676 void
677 setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
678 {
679 setScalarResult(val);
680 }
681
682 /** Record a vector register being set to a value */
683 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
684 {
685 setVecElemResult(val);
686 }
687
688 /** Records that one of the source registers is ready. */
689 void markSrcRegReady();
690
691 /** Marks a specific register as ready. */
692 void markSrcRegReady(RegIndex src_idx);
693
694 /** Returns if a source register is ready. */
695 bool isReadySrcRegIdx(int idx) const
696 {
697 return this->_readySrcRegIdx[idx];
698 }
699
700 /** Sets this instruction as completed. */
701 void setCompleted() { status.set(Completed); }
702
703 /** Returns whether or not this instruction is completed. */
704 bool isCompleted() const { return status[Completed]; }
705
706 /** Marks the result as ready. */
707 void setResultReady() { status.set(ResultReady); }
708
709 /** Returns whether or not the result is ready. */
710 bool isResultReady() const { return status[ResultReady]; }
711
712 /** Sets this instruction as ready to issue. */
713 void setCanIssue() { status.set(CanIssue); }
714
715 /** Returns whether or not this instruction is ready to issue. */
716 bool readyToIssue() const { return status[CanIssue]; }
717
718 /** Clears this instruction being able to issue. */
719 void clearCanIssue() { status.reset(CanIssue); }
720
721 /** Sets this instruction as issued from the IQ. */
722 void setIssued() { status.set(Issued); }
723
724 /** Returns whether or not this instruction has issued. */
725 bool isIssued() const { return status[Issued]; }
726
727 /** Clears this instruction as being issued. */
728 void clearIssued() { status.reset(Issued); }
729
730 /** Sets this instruction as executed. */
731 void setExecuted() { status.set(Executed); }
732
733 /** Returns whether or not this instruction has executed. */
734 bool isExecuted() const { return status[Executed]; }
735
736 /** Sets this instruction as ready to commit. */
737 void setCanCommit() { status.set(CanCommit); }
738
739 /** Clears this instruction as being ready to commit. */
740 void clearCanCommit() { status.reset(CanCommit); }
741
742 /** Returns whether or not this instruction is ready to commit. */
743 bool readyToCommit() const { return status[CanCommit]; }
744
745 void setAtCommit() { status.set(AtCommit); }
746
747 bool isAtCommit() { return status[AtCommit]; }
748
749 /** Sets this instruction as committed. */
750 void setCommitted() { status.set(Committed); }
751
752 /** Returns whether or not this instruction is committed. */
753 bool isCommitted() const { return status[Committed]; }
754
755 /** Sets this instruction as squashed. */
756 void setSquashed() { status.set(Squashed); }
757
758 /** Returns whether or not this instruction is squashed. */
759 bool isSquashed() const { return status[Squashed]; }
760
761 //Instruction Queue Entry
762 //-----------------------
763 /** Sets this instruction as a entry the IQ. */
764 void setInIQ() { status.set(IqEntry); }
765
766 /** Sets this instruction as a entry the IQ. */
767 void clearInIQ() { status.reset(IqEntry); }
768
769 /** Returns whether or not this instruction has issued. */
770 bool isInIQ() const { return status[IqEntry]; }
771
772 /** Sets this instruction as squashed in the IQ. */
773 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
774
775 /** Returns whether or not this instruction is squashed in the IQ. */
776 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
777
778
779 //Load / Store Queue Functions
780 //-----------------------
781 /** Sets this instruction as a entry the LSQ. */
782 void setInLSQ() { status.set(LsqEntry); }
783
784 /** Sets this instruction as a entry the LSQ. */
785 void removeInLSQ() { status.reset(LsqEntry); }
786
787 /** Returns whether or not this instruction is in the LSQ. */
788 bool isInLSQ() const { return status[LsqEntry]; }
789
790 /** Sets this instruction as squashed in the LSQ. */
791 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
792
793 /** Returns whether or not this instruction is squashed in the LSQ. */
794 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
795
796
797 //Reorder Buffer Functions
798 //-----------------------
799 /** Sets this instruction as a entry the ROB. */
800 void setInROB() { status.set(RobEntry); }
801
802 /** Sets this instruction as a entry the ROB. */
803 void clearInROB() { status.reset(RobEntry); }
804
805 /** Returns whether or not this instruction is in the ROB. */
806 bool isInROB() const { return status[RobEntry]; }
807
808 /** Sets this instruction as squashed in the ROB. */
809 void setSquashedInROB() { status.set(SquashedInROB); }
810
811 /** Returns whether or not this instruction is squashed in the ROB. */
812 bool isSquashedInROB() const { return status[SquashedInROB]; }
813
814 /** Read the PC state of this instruction. */
815 TheISA::PCState pcState() const { return pc; }
816
817 /** Set the PC state of this instruction. */
818 void pcState(const TheISA::PCState &val) { pc = val; }
819
820 /** Read the PC of this instruction. */
821 Addr instAddr() const { return pc.instAddr(); }
822
823 /** Read the PC of the next instruction. */
824 Addr nextInstAddr() const { return pc.nextInstAddr(); }
825
826 /**Read the micro PC of this instruction. */
827 Addr microPC() const { return pc.microPC(); }
828
829 bool readPredicate()
830 {
831 return instFlags[Predicate];
832 }
833
834 void setPredicate(bool val)
835 {
836 instFlags[Predicate] = val;
837
838 if (traceData) {
839 traceData->setPredicate(val);
840 }
841 }
842
843 /** Sets the ASID. */
844 void setASID(short addr_space_id) { asid = addr_space_id; }
845
846 /** Sets the thread id. */
847 void setTid(ThreadID tid) { threadNumber = tid; }
848
849 /** Sets the pointer to the thread state. */
850 void setThreadState(ImplState *state) { thread = state; }
851
852 /** Returns the thread context. */
853 ThreadContext *tcBase() { return thread->getTC(); }
854
855 public:
856 /** Returns whether or not the eff. addr. source registers are ready. */
857 bool eaSrcsReady();
858
859 /** Is this instruction's memory access strictly ordered? */
860 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
861
862 /** Has this instruction generated a memory request. */
863 bool hasRequest() { return instFlags[ReqMade]; }
864
865 /** Returns iterator to this instruction in the list of all insts. */
866 ListIt &getInstListIt() { return instListIt; }
867
868 /** Sets iterator for this instruction in the list of all insts. */
869 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
870
871 public:
872 /** Returns the number of consecutive store conditional failures. */
873 unsigned int readStCondFailures() const
874 { return thread->storeCondFailures; }
875
876 /** Sets the number of consecutive store conditional failures. */
877 void setStCondFailures(unsigned int sc_failures)
878 { thread->storeCondFailures = sc_failures; }
879
880 public:
881 // monitor/mwait funtions
882 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
883 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
884 void mwaitAtomic(ThreadContext *tc)
885 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
886 AddressMonitor *getAddrMonitor()
887 { return cpu->getCpuAddrMonitor(threadNumber); }
888};
889
890template<class Impl>
891Fault
892BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
893 Request::Flags flags)
894{
895 instFlags[ReqMade] = true;
896 Request *req = NULL;
897 Request *sreqLow = NULL;
898 Request *sreqHigh = NULL;
899
900 if (instFlags[ReqMade] && translationStarted()) {
901 req = savedReq;
902 sreqLow = savedSreqLow;
903 sreqHigh = savedSreqHigh;
904 } else {
905 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
906 thread->contextId());
907
908 req->taskId(cpu->taskId());
909
910 // Only split the request if the ISA supports unaligned accesses.
911 if (TheISA::HasUnalignedMemAcc) {
912 splitRequest(req, sreqLow, sreqHigh);
913 }
914 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
915 }
916
917 if (translationCompleted()) {
918 if (fault == NoFault) {
919 effAddr = req->getVaddr();
920 effSize = size;
921 instFlags[EffAddrValid] = true;
922
923 if (cpu->checker) {
924 if (reqToVerify != NULL) {
925 delete reqToVerify;
926 }
927 reqToVerify = new Request(*req);
928 }
929 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
930 } else {
931 // Commit will have to clean up whatever happened. Set this
932 // instruction as executed.
933 this->setExecuted();
934 }
935 }
936
937 if (traceData)
938 traceData->setMem(addr, size, flags);
939
940 return fault;
941}
942
943template<class Impl>
944Fault
945BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
946 Request::Flags flags, uint64_t *res)
947{
948 if (traceData)
949 traceData->setMem(addr, size, flags);
950
951 instFlags[ReqMade] = true;
952 Request *req = NULL;
953 Request *sreqLow = NULL;
954 Request *sreqHigh = NULL;
955
956 if (instFlags[ReqMade] && translationStarted()) {
957 req = savedReq;
958 sreqLow = savedSreqLow;
959 sreqHigh = savedSreqHigh;
960 } else {
961 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
962 thread->contextId());
963
964 req->taskId(cpu->taskId());
965
966 // Only split the request if the ISA supports unaligned accesses.
967 if (TheISA::HasUnalignedMemAcc) {
968 splitRequest(req, sreqLow, sreqHigh);
969 }
970 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
971 }
972
973 if (fault == NoFault && translationCompleted()) {
974 effAddr = req->getVaddr();
975 effSize = size;
976 instFlags[EffAddrValid] = true;
977
978 if (cpu->checker) {
979 if (reqToVerify != NULL) {
980 delete reqToVerify;
981 }
982 reqToVerify = new Request(*req);
983 }
984 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
985 }
986
987 return fault;
988}
989
990template<class Impl>
991inline void
992BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
993 RequestPtr &sreqHigh)
994{
995 // Check to see if the request crosses the next level block boundary.
996 unsigned block_size = cpu->cacheLineSize();
997 Addr addr = req->getVaddr();
998 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
999 assert(split_addr <= addr || split_addr - addr < block_size);
1000
1001 // Spans two blocks.
1002 if (split_addr > addr) {
1003 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1004 }
1005}
1006
1007template<class Impl>
1008inline void
1009BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1010 RequestPtr sreqHigh, uint64_t *res,
1011 BaseTLB::Mode mode)
1012{
1013 translationStarted(true);
1014
1015 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1016 WholeTranslationState *state =
1017 new WholeTranslationState(req, NULL, res, mode);
1018
1019 // One translation if the request isn't split.
1020 DataTranslation<BaseDynInstPtr> *trans =
1021 new DataTranslation<BaseDynInstPtr>(this, state);
1022
1023 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1024
1025 if (!translationCompleted()) {
1026 // The translation isn't yet complete, so we can't possibly have a
1027 // fault. Overwrite any existing fault we might have from a previous
1028 // execution of this instruction (e.g. an uncachable load that
1029 // couldn't execute because it wasn't at the head of the ROB).
1030 fault = NoFault;
1031
1032 // Save memory requests.
1033 savedReq = state->mainReq;
1034 savedSreqLow = state->sreqLow;
1035 savedSreqHigh = state->sreqHigh;
1036 }
1037 } else {
1038 WholeTranslationState *state =
1039 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1040
1041 // Two translations when the request is split.
1042 DataTranslation<BaseDynInstPtr> *stransLow =
1043 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1044 DataTranslation<BaseDynInstPtr> *stransHigh =
1045 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1046
1047 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1048 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1049
1050 if (!translationCompleted()) {
1051 // The translation isn't yet complete, so we can't possibly have a
1052 // fault. Overwrite any existing fault we might have from a previous
1053 // execution of this instruction (e.g. an uncachable load that
1054 // couldn't execute because it wasn't at the head of the ROB).
1055 fault = NoFault;
1056
1057 // Save memory requests.
1058 savedReq = state->mainReq;
1059 savedSreqLow = state->sreqLow;
1060 savedSreqHigh = state->sreqHigh;
1061 }
1062 }
1063}
1064
1065template<class Impl>
1066inline void
1067BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1068{
1069 fault = state->getFault();
1070
1071 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1072
1073 if (fault == NoFault) {
1074 // save Paddr for a single req
1075 physEffAddrLow = state->getPaddr();
1076
1077 // case for the request that has been split
1078 if (state->isSplit) {
1079 physEffAddrLow = state->sreqLow->getPaddr();
1080 physEffAddrHigh = state->sreqHigh->getPaddr();
1081 }
1082
1083 memReqFlags = state->getFlags();
1084
1085 if (state->mainReq->isCondSwap()) {
1086 assert(state->res);
1087 state->mainReq->setExtraData(*state->res);
1088 }
1089
1090 } else {
1091 state->deleteReqs();
1092 }
1093 delete state;
1094
1095 translationCompleted(true);
1096}
1097
1098#endif // __CPU_BASE_DYN_INST_HH__
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