base_dyn_inst.hh (10190:fb83d025d1c3) base_dyn_inst.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exec_context.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
60#include "cpu/exetrace.hh"
61#include "cpu/inst_seq.hh"
62#include "cpu/op_class.hh"
63#include "cpu/static_inst.hh"
64#include "cpu/translation.hh"
65#include "mem/packet.hh"
66#include "sim/byteswap.hh"
67#include "sim/fault_fwd.hh"
68#include "sim/system.hh"
69#include "sim/tlb.hh"
70
71/**
72 * @file
73 * Defines a dynamic instruction context.
74 */
75
76template <class Impl>
76class BaseDynInst : public RefCounted
77class BaseDynInst : public ExecContext, public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
78{
79 public:
80 // Typedef for the CPU.
81 typedef typename Impl::CPUType ImplCPU;
82 typedef typename ImplCPU::ImplState ImplState;
83
84 // Logical register index type.
85 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 union Result {
103 uint64_t integer;
104 double dbl;
105 void set(uint64_t i) { integer = i; }
106 void set(double d) { dbl = d; }
107 void get(uint64_t& i) { i = integer; }
108 void get(double& d) { d = dbl; }
109 };
110
111 protected:
112 enum Status {
113 IqEntry, /// Instruction is in the IQ
114 RobEntry, /// Instruction is in the ROB
115 LsqEntry, /// Instruction is in the LSQ
116 Completed, /// Instruction has completed
117 ResultReady, /// Instruction has its result
118 CanIssue, /// Instruction can issue and execute
119 Issued, /// Instruction has issued
120 Executed, /// Instruction has executed
121 CanCommit, /// Instruction can commit
122 AtCommit, /// Instruction has reached commit
123 Committed, /// Instruction has committed
124 Squashed, /// Instruction is squashed
125 SquashedInIQ, /// Instruction is squashed in the IQ
126 SquashedInLSQ, /// Instruction is squashed in the LSQ
127 SquashedInROB, /// Instruction is squashed in the ROB
128 RecoverInst, /// Is a recover instruction
129 BlockingInst, /// Is a blocking instruction
130 ThreadsyncWait, /// Is a thread synchronization instruction
131 SerializeBefore, /// Needs to serialize on
132 /// instructions ahead of it
133 SerializeAfter, /// Needs to serialize instructions behind it
134 SerializeHandled, /// Serialization has been handled
135 NumStatus
136 };
137
138 enum Flags {
139 TranslationStarted,
140 TranslationCompleted,
141 PossibleLoadViolation,
142 HitExternalSnoop,
143 EffAddrValid,
144 RecordResult,
145 Predicate,
146 PredTaken,
147 /** Whether or not the effective address calculation is completed.
148 * @todo: Consider if this is necessary or not.
149 */
150 EACalcDone,
151 IsUncacheable,
152 ReqMade,
153 MemOpDone,
154 MaxFlags
155 };
156
157 public:
158 /** The sequence number of the instruction. */
159 InstSeqNum seqNum;
160
161 /** The StaticInst used by this BaseDynInst. */
162 StaticInstPtr staticInst;
163
164 /** Pointer to the Impl's CPU object. */
165 ImplCPU *cpu;
166
167 BaseCPU *getCpuPtr() { return cpu; }
168
169 /** Pointer to the thread state. */
170 ImplState *thread;
171
172 /** The kind of fault this instruction has generated. */
173 Fault fault;
174
175 /** InstRecord that tracks this instructions. */
176 Trace::InstRecord *traceData;
177
178 protected:
179 /** The result of the instruction; assumes an instruction can have many
180 * destination registers.
181 */
182 std::queue<Result> instResult;
183
184 /** PC state for this instruction. */
185 TheISA::PCState pc;
186
187 /* An amalgamation of a lot of boolean values into one */
188 std::bitset<MaxFlags> instFlags;
189
190 /** The status of this BaseDynInst. Several bits can be set. */
191 std::bitset<NumStatus> status;
192
193 /** Whether or not the source register is ready.
194 * @todo: Not sure this should be here vs the derived class.
195 */
196 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
197
198 public:
199 /** The thread this instruction is from. */
200 ThreadID threadNumber;
201
202 /** Iterator pointing to this BaseDynInst in the list of all insts. */
203 ListIt instListIt;
204
205 ////////////////////// Branch Data ///////////////
206 /** Predicted PC state after this instruction. */
207 TheISA::PCState predPC;
208
209 /** The Macroop if one exists */
210 StaticInstPtr macroop;
211
212 /** How many source registers are ready. */
213 uint8_t readyRegs;
214
215 public:
216 /////////////////////// Load Store Data //////////////////////
217 /** The effective virtual address (lds & stores only). */
218 Addr effAddr;
219
220 /** The effective physical address. */
221 Addr physEffAddr;
222
223 /** The memory request flags (from translation). */
224 unsigned memReqFlags;
225
226 /** data address space ID, for loads & stores. */
227 short asid;
228
229 /** The size of the request */
230 uint8_t effSize;
231
232 /** Pointer to the data for the memory access. */
233 uint8_t *memData;
234
235 /** Load queue index. */
236 int16_t lqIdx;
237
238 /** Store queue index. */
239 int16_t sqIdx;
240
241
242 /////////////////////// TLB Miss //////////////////////
243 /**
244 * Saved memory requests (needed when the DTB address translation is
245 * delayed due to a hw page table walk).
246 */
247 RequestPtr savedReq;
248 RequestPtr savedSreqLow;
249 RequestPtr savedSreqHigh;
250
251 /////////////////////// Checker //////////////////////
252 // Need a copy of main request pointer to verify on writes.
253 RequestPtr reqToVerify;
254
255 private:
256 /** Instruction effective address.
257 * @todo: Consider if this is necessary or not.
258 */
259 Addr instEffAddr;
260
261 protected:
262 /** Flattened register index of the destination registers of this
263 * instruction.
264 */
265 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
266
267 /** Physical register index of the destination registers of this
268 * instruction.
269 */
270 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
271
272 /** Physical register index of the source registers of this
273 * instruction.
274 */
275 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
276
277 /** Physical register index of the previous producers of the
278 * architected destinations.
279 */
280 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
281
282
283 public:
284 /** Records changes to result? */
285 void recordResult(bool f) { instFlags[RecordResult] = f; }
286
287 /** Is the effective virtual address valid. */
288 bool effAddrValid() const { return instFlags[EffAddrValid]; }
289
290 /** Whether or not the memory operation is done. */
291 bool memOpDone() const { return instFlags[MemOpDone]; }
292 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
293
294
295 ////////////////////////////////////////////
296 //
297 // INSTRUCTION EXECUTION
298 //
299 ////////////////////////////////////////////
300
301 void demapPage(Addr vaddr, uint64_t asn)
302 {
303 cpu->demapPage(vaddr, asn);
304 }
305 void demapInstPage(Addr vaddr, uint64_t asn)
306 {
307 cpu->demapPage(vaddr, asn);
308 }
309 void demapDataPage(Addr vaddr, uint64_t asn)
310 {
311 cpu->demapPage(vaddr, asn);
312 }
313
314 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
315
316 Fault writeMem(uint8_t *data, unsigned size,
317 Addr addr, unsigned flags, uint64_t *res);
318
319 /** Splits a request in two if it crosses a dcache block. */
320 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
321 RequestPtr &sreqHigh);
322
323 /** Initiate a DTB address translation. */
324 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
325 RequestPtr sreqHigh, uint64_t *res,
326 BaseTLB::Mode mode);
327
328 /** Finish a DTB address translation. */
329 void finishTranslation(WholeTranslationState *state);
330
331 /** True if the DTB address translation has started. */
332 bool translationStarted() const { return instFlags[TranslationStarted]; }
333 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
334
335 /** True if the DTB address translation has completed. */
336 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
337 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
338
339 /** True if this address was found to match a previous load and they issued
340 * out of order. If that happend, then it's only a problem if an incoming
341 * snoop invalidate modifies the line, in which case we need to squash.
342 * If nothing modified the line the order doesn't matter.
343 */
344 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
345 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
346
347 /** True if the address hit a external snoop while sitting in the LSQ.
348 * If this is true and a older instruction sees it, this instruction must
349 * reexecute
350 */
351 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
352 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
353
354 /**
355 * Returns true if the DTB address translation is being delayed due to a hw
356 * page table walk.
357 */
358 bool isTranslationDelayed() const
359 {
360 return (translationStarted() && !translationCompleted());
361 }
362
363 public:
364#ifdef DEBUG
365 void dumpSNList();
366#endif
367
368 /** Returns the physical register index of the i'th destination
369 * register.
370 */
371 PhysRegIndex renamedDestRegIdx(int idx) const
372 {
373 return _destRegIdx[idx];
374 }
375
376 /** Returns the physical register index of the i'th source register. */
377 PhysRegIndex renamedSrcRegIdx(int idx) const
378 {
379 assert(TheISA::MaxInstSrcRegs > idx);
380 return _srcRegIdx[idx];
381 }
382
383 /** Returns the flattened register index of the i'th destination
384 * register.
385 */
386 TheISA::RegIndex flattenedDestRegIdx(int idx) const
387 {
388 return _flatDestRegIdx[idx];
389 }
390
391 /** Returns the physical register index of the previous physical register
392 * that remapped to the same logical register index.
393 */
394 PhysRegIndex prevDestRegIdx(int idx) const
395 {
396 return _prevDestRegIdx[idx];
397 }
398
399 /** Renames a destination register to a physical register. Also records
400 * the previous physical register that the logical register mapped to.
401 */
402 void renameDestReg(int idx,
403 PhysRegIndex renamed_dest,
404 PhysRegIndex previous_rename)
405 {
406 _destRegIdx[idx] = renamed_dest;
407 _prevDestRegIdx[idx] = previous_rename;
408 }
409
410 /** Renames a source logical register to the physical register which
411 * has/will produce that logical register's result.
412 * @todo: add in whether or not the source register is ready.
413 */
414 void renameSrcReg(int idx, PhysRegIndex renamed_src)
415 {
416 _srcRegIdx[idx] = renamed_src;
417 }
418
419 /** Flattens a destination architectural register index into a logical
420 * index.
421 */
422 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
423 {
424 _flatDestRegIdx[idx] = flattened_dest;
425 }
426 /** BaseDynInst constructor given a binary instruction.
427 * @param staticInst A StaticInstPtr to the underlying instruction.
428 * @param pc The PC state for the instruction.
429 * @param predPC The predicted next PC state for the instruction.
430 * @param seq_num The sequence number of the instruction.
431 * @param cpu Pointer to the instruction's CPU.
432 */
433 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
434 TheISA::PCState pc, TheISA::PCState predPC,
435 InstSeqNum seq_num, ImplCPU *cpu);
436
437 /** BaseDynInst constructor given a StaticInst pointer.
438 * @param _staticInst The StaticInst for this BaseDynInst.
439 */
440 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
441
442 /** BaseDynInst destructor. */
443 ~BaseDynInst();
444
445 private:
446 /** Function to initialize variables in the constructors. */
447 void initVars();
448
449 public:
450 /** Dumps out contents of this BaseDynInst. */
451 void dump();
452
453 /** Dumps out contents of this BaseDynInst into given string. */
454 void dump(std::string &outstring);
455
456 /** Read this CPU's ID. */
457 int cpuId() const { return cpu->cpuId(); }
458
459 /** Read this CPU's Socket ID. */
460 uint32_t socketId() const { return cpu->socketId(); }
461
462 /** Read this CPU's data requestor ID */
463 MasterID masterId() const { return cpu->dataMasterId(); }
464
465 /** Read this context's system-wide ID **/
466 int contextId() const { return thread->contextId(); }
467
468 /** Returns the fault type. */
469 Fault getFault() const { return fault; }
470
471 /** Checks whether or not this instruction has had its branch target
472 * calculated yet. For now it is not utilized and is hacked to be
473 * always false.
474 * @todo: Actually use this instruction.
475 */
476 bool doneTargCalc() { return false; }
477
478 /** Set the predicted target of this current instruction. */
479 void setPredTarg(const TheISA::PCState &_predPC)
480 {
481 predPC = _predPC;
482 }
483
484 const TheISA::PCState &readPredTarg() { return predPC; }
485
486 /** Returns the predicted PC immediately after the branch. */
487 Addr predInstAddr() { return predPC.instAddr(); }
488
489 /** Returns the predicted PC two instructions after the branch */
490 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
491
492 /** Returns the predicted micro PC after the branch */
493 Addr predMicroPC() { return predPC.microPC(); }
494
495 /** Returns whether the instruction was predicted taken or not. */
496 bool readPredTaken()
497 {
498 return instFlags[PredTaken];
499 }
500
501 void setPredTaken(bool predicted_taken)
502 {
503 instFlags[PredTaken] = predicted_taken;
504 }
505
506 /** Returns whether the instruction mispredicted. */
507 bool mispredicted()
508 {
509 TheISA::PCState tempPC = pc;
510 TheISA::advancePC(tempPC, staticInst);
511 return !(tempPC == predPC);
512 }
513
514 //
515 // Instruction types. Forward checks to StaticInst object.
516 //
517 bool isNop() const { return staticInst->isNop(); }
518 bool isMemRef() const { return staticInst->isMemRef(); }
519 bool isLoad() const { return staticInst->isLoad(); }
520 bool isStore() const { return staticInst->isStore(); }
521 bool isStoreConditional() const
522 { return staticInst->isStoreConditional(); }
523 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
524 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
525 bool isInteger() const { return staticInst->isInteger(); }
526 bool isFloating() const { return staticInst->isFloating(); }
527 bool isControl() const { return staticInst->isControl(); }
528 bool isCall() const { return staticInst->isCall(); }
529 bool isReturn() const { return staticInst->isReturn(); }
530 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
531 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
532 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
533 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
534 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
535 bool isThreadSync() const { return staticInst->isThreadSync(); }
536 bool isSerializing() const { return staticInst->isSerializing(); }
537 bool isSerializeBefore() const
538 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
539 bool isSerializeAfter() const
540 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
541 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
542 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
543 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
544 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
545 bool isQuiesce() const { return staticInst->isQuiesce(); }
546 bool isIprAccess() const { return staticInst->isIprAccess(); }
547 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
548 bool isSyscall() const { return staticInst->isSyscall(); }
549 bool isMacroop() const { return staticInst->isMacroop(); }
550 bool isMicroop() const { return staticInst->isMicroop(); }
551 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
552 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
553 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
554 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
555
556 /** Temporarily sets this instruction as a serialize before instruction. */
557 void setSerializeBefore() { status.set(SerializeBefore); }
558
559 /** Clears the serializeBefore part of this instruction. */
560 void clearSerializeBefore() { status.reset(SerializeBefore); }
561
562 /** Checks if this serializeBefore is only temporarily set. */
563 bool isTempSerializeBefore() { return status[SerializeBefore]; }
564
565 /** Temporarily sets this instruction as a serialize after instruction. */
566 void setSerializeAfter() { status.set(SerializeAfter); }
567
568 /** Clears the serializeAfter part of this instruction.*/
569 void clearSerializeAfter() { status.reset(SerializeAfter); }
570
571 /** Checks if this serializeAfter is only temporarily set. */
572 bool isTempSerializeAfter() { return status[SerializeAfter]; }
573
574 /** Sets the serialization part of this instruction as handled. */
575 void setSerializeHandled() { status.set(SerializeHandled); }
576
577 /** Checks if the serialization part of this instruction has been
578 * handled. This does not apply to the temporary serializing
579 * state; it only applies to this instruction's own permanent
580 * serializing state.
581 */
582 bool isSerializeHandled() { return status[SerializeHandled]; }
583
584 /** Returns the opclass of this instruction. */
585 OpClass opClass() const { return staticInst->opClass(); }
586
587 /** Returns the branch target address. */
588 TheISA::PCState branchTarget() const
589 { return staticInst->branchTarget(pc); }
590
591 /** Returns the number of source registers. */
592 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
593
594 /** Returns the number of destination registers. */
595 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
596
597 // the following are used to track physical register usage
598 // for machines with separate int & FP reg files
599 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
600 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
601
602 /** Returns the logical register index of the i'th destination register. */
603 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
604
605 /** Returns the logical register index of the i'th source register. */
606 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
607
608 /** Pops a result off the instResult queue */
609 template <class T>
610 void popResult(T& t)
611 {
612 if (!instResult.empty()) {
613 instResult.front().get(t);
614 instResult.pop();
615 }
616 }
617
618 /** Read the most recent result stored by this instruction */
619 template <class T>
620 void readResult(T& t)
621 {
622 instResult.back().get(t);
623 }
624
625 /** Pushes a result onto the instResult queue */
626 template <class T>
627 void setResult(T t)
628 {
629 if (instFlags[RecordResult]) {
630 Result instRes;
631 instRes.set(t);
632 instResult.push(instRes);
633 }
634 }
635
636 /** Records an integer register being set to a value. */
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 union Result {
100 uint64_t integer;
101 double dbl;
102 void set(uint64_t i) { integer = i; }
103 void set(double d) { dbl = d; }
104 void get(uint64_t& i) { i = integer; }
105 void get(double& d) { d = dbl; }
106 };
107
108 protected:
109 enum Status {
110 IqEntry, /// Instruction is in the IQ
111 RobEntry, /// Instruction is in the ROB
112 LsqEntry, /// Instruction is in the LSQ
113 Completed, /// Instruction has completed
114 ResultReady, /// Instruction has its result
115 CanIssue, /// Instruction can issue and execute
116 Issued, /// Instruction has issued
117 Executed, /// Instruction has executed
118 CanCommit, /// Instruction can commit
119 AtCommit, /// Instruction has reached commit
120 Committed, /// Instruction has committed
121 Squashed, /// Instruction is squashed
122 SquashedInIQ, /// Instruction is squashed in the IQ
123 SquashedInLSQ, /// Instruction is squashed in the LSQ
124 SquashedInROB, /// Instruction is squashed in the ROB
125 RecoverInst, /// Is a recover instruction
126 BlockingInst, /// Is a blocking instruction
127 ThreadsyncWait, /// Is a thread synchronization instruction
128 SerializeBefore, /// Needs to serialize on
129 /// instructions ahead of it
130 SerializeAfter, /// Needs to serialize instructions behind it
131 SerializeHandled, /// Serialization has been handled
132 NumStatus
133 };
134
135 enum Flags {
136 TranslationStarted,
137 TranslationCompleted,
138 PossibleLoadViolation,
139 HitExternalSnoop,
140 EffAddrValid,
141 RecordResult,
142 Predicate,
143 PredTaken,
144 /** Whether or not the effective address calculation is completed.
145 * @todo: Consider if this is necessary or not.
146 */
147 EACalcDone,
148 IsUncacheable,
149 ReqMade,
150 MemOpDone,
151 MaxFlags
152 };
153
154 public:
155 /** The sequence number of the instruction. */
156 InstSeqNum seqNum;
157
158 /** The StaticInst used by this BaseDynInst. */
159 StaticInstPtr staticInst;
160
161 /** Pointer to the Impl's CPU object. */
162 ImplCPU *cpu;
163
164 BaseCPU *getCpuPtr() { return cpu; }
165
166 /** Pointer to the thread state. */
167 ImplState *thread;
168
169 /** The kind of fault this instruction has generated. */
170 Fault fault;
171
172 /** InstRecord that tracks this instructions. */
173 Trace::InstRecord *traceData;
174
175 protected:
176 /** The result of the instruction; assumes an instruction can have many
177 * destination registers.
178 */
179 std::queue<Result> instResult;
180
181 /** PC state for this instruction. */
182 TheISA::PCState pc;
183
184 /* An amalgamation of a lot of boolean values into one */
185 std::bitset<MaxFlags> instFlags;
186
187 /** The status of this BaseDynInst. Several bits can be set. */
188 std::bitset<NumStatus> status;
189
190 /** Whether or not the source register is ready.
191 * @todo: Not sure this should be here vs the derived class.
192 */
193 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
194
195 public:
196 /** The thread this instruction is from. */
197 ThreadID threadNumber;
198
199 /** Iterator pointing to this BaseDynInst in the list of all insts. */
200 ListIt instListIt;
201
202 ////////////////////// Branch Data ///////////////
203 /** Predicted PC state after this instruction. */
204 TheISA::PCState predPC;
205
206 /** The Macroop if one exists */
207 StaticInstPtr macroop;
208
209 /** How many source registers are ready. */
210 uint8_t readyRegs;
211
212 public:
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
215 Addr effAddr;
216
217 /** The effective physical address. */
218 Addr physEffAddr;
219
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
222
223 /** data address space ID, for loads & stores. */
224 short asid;
225
226 /** The size of the request */
227 uint8_t effSize;
228
229 /** Pointer to the data for the memory access. */
230 uint8_t *memData;
231
232 /** Load queue index. */
233 int16_t lqIdx;
234
235 /** Store queue index. */
236 int16_t sqIdx;
237
238
239 /////////////////////// TLB Miss //////////////////////
240 /**
241 * Saved memory requests (needed when the DTB address translation is
242 * delayed due to a hw page table walk).
243 */
244 RequestPtr savedReq;
245 RequestPtr savedSreqLow;
246 RequestPtr savedSreqHigh;
247
248 /////////////////////// Checker //////////////////////
249 // Need a copy of main request pointer to verify on writes.
250 RequestPtr reqToVerify;
251
252 private:
253 /** Instruction effective address.
254 * @todo: Consider if this is necessary or not.
255 */
256 Addr instEffAddr;
257
258 protected:
259 /** Flattened register index of the destination registers of this
260 * instruction.
261 */
262 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
263
264 /** Physical register index of the destination registers of this
265 * instruction.
266 */
267 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
268
269 /** Physical register index of the source registers of this
270 * instruction.
271 */
272 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
273
274 /** Physical register index of the previous producers of the
275 * architected destinations.
276 */
277 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
278
279
280 public:
281 /** Records changes to result? */
282 void recordResult(bool f) { instFlags[RecordResult] = f; }
283
284 /** Is the effective virtual address valid. */
285 bool effAddrValid() const { return instFlags[EffAddrValid]; }
286
287 /** Whether or not the memory operation is done. */
288 bool memOpDone() const { return instFlags[MemOpDone]; }
289 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
290
291
292 ////////////////////////////////////////////
293 //
294 // INSTRUCTION EXECUTION
295 //
296 ////////////////////////////////////////////
297
298 void demapPage(Addr vaddr, uint64_t asn)
299 {
300 cpu->demapPage(vaddr, asn);
301 }
302 void demapInstPage(Addr vaddr, uint64_t asn)
303 {
304 cpu->demapPage(vaddr, asn);
305 }
306 void demapDataPage(Addr vaddr, uint64_t asn)
307 {
308 cpu->demapPage(vaddr, asn);
309 }
310
311 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
312
313 Fault writeMem(uint8_t *data, unsigned size,
314 Addr addr, unsigned flags, uint64_t *res);
315
316 /** Splits a request in two if it crosses a dcache block. */
317 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
318 RequestPtr &sreqHigh);
319
320 /** Initiate a DTB address translation. */
321 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
322 RequestPtr sreqHigh, uint64_t *res,
323 BaseTLB::Mode mode);
324
325 /** Finish a DTB address translation. */
326 void finishTranslation(WholeTranslationState *state);
327
328 /** True if the DTB address translation has started. */
329 bool translationStarted() const { return instFlags[TranslationStarted]; }
330 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
331
332 /** True if the DTB address translation has completed. */
333 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
334 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
335
336 /** True if this address was found to match a previous load and they issued
337 * out of order. If that happend, then it's only a problem if an incoming
338 * snoop invalidate modifies the line, in which case we need to squash.
339 * If nothing modified the line the order doesn't matter.
340 */
341 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
342 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
343
344 /** True if the address hit a external snoop while sitting in the LSQ.
345 * If this is true and a older instruction sees it, this instruction must
346 * reexecute
347 */
348 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
349 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
350
351 /**
352 * Returns true if the DTB address translation is being delayed due to a hw
353 * page table walk.
354 */
355 bool isTranslationDelayed() const
356 {
357 return (translationStarted() && !translationCompleted());
358 }
359
360 public:
361#ifdef DEBUG
362 void dumpSNList();
363#endif
364
365 /** Returns the physical register index of the i'th destination
366 * register.
367 */
368 PhysRegIndex renamedDestRegIdx(int idx) const
369 {
370 return _destRegIdx[idx];
371 }
372
373 /** Returns the physical register index of the i'th source register. */
374 PhysRegIndex renamedSrcRegIdx(int idx) const
375 {
376 assert(TheISA::MaxInstSrcRegs > idx);
377 return _srcRegIdx[idx];
378 }
379
380 /** Returns the flattened register index of the i'th destination
381 * register.
382 */
383 TheISA::RegIndex flattenedDestRegIdx(int idx) const
384 {
385 return _flatDestRegIdx[idx];
386 }
387
388 /** Returns the physical register index of the previous physical register
389 * that remapped to the same logical register index.
390 */
391 PhysRegIndex prevDestRegIdx(int idx) const
392 {
393 return _prevDestRegIdx[idx];
394 }
395
396 /** Renames a destination register to a physical register. Also records
397 * the previous physical register that the logical register mapped to.
398 */
399 void renameDestReg(int idx,
400 PhysRegIndex renamed_dest,
401 PhysRegIndex previous_rename)
402 {
403 _destRegIdx[idx] = renamed_dest;
404 _prevDestRegIdx[idx] = previous_rename;
405 }
406
407 /** Renames a source logical register to the physical register which
408 * has/will produce that logical register's result.
409 * @todo: add in whether or not the source register is ready.
410 */
411 void renameSrcReg(int idx, PhysRegIndex renamed_src)
412 {
413 _srcRegIdx[idx] = renamed_src;
414 }
415
416 /** Flattens a destination architectural register index into a logical
417 * index.
418 */
419 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
420 {
421 _flatDestRegIdx[idx] = flattened_dest;
422 }
423 /** BaseDynInst constructor given a binary instruction.
424 * @param staticInst A StaticInstPtr to the underlying instruction.
425 * @param pc The PC state for the instruction.
426 * @param predPC The predicted next PC state for the instruction.
427 * @param seq_num The sequence number of the instruction.
428 * @param cpu Pointer to the instruction's CPU.
429 */
430 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
431 TheISA::PCState pc, TheISA::PCState predPC,
432 InstSeqNum seq_num, ImplCPU *cpu);
433
434 /** BaseDynInst constructor given a StaticInst pointer.
435 * @param _staticInst The StaticInst for this BaseDynInst.
436 */
437 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
438
439 /** BaseDynInst destructor. */
440 ~BaseDynInst();
441
442 private:
443 /** Function to initialize variables in the constructors. */
444 void initVars();
445
446 public:
447 /** Dumps out contents of this BaseDynInst. */
448 void dump();
449
450 /** Dumps out contents of this BaseDynInst into given string. */
451 void dump(std::string &outstring);
452
453 /** Read this CPU's ID. */
454 int cpuId() const { return cpu->cpuId(); }
455
456 /** Read this CPU's Socket ID. */
457 uint32_t socketId() const { return cpu->socketId(); }
458
459 /** Read this CPU's data requestor ID */
460 MasterID masterId() const { return cpu->dataMasterId(); }
461
462 /** Read this context's system-wide ID **/
463 int contextId() const { return thread->contextId(); }
464
465 /** Returns the fault type. */
466 Fault getFault() const { return fault; }
467
468 /** Checks whether or not this instruction has had its branch target
469 * calculated yet. For now it is not utilized and is hacked to be
470 * always false.
471 * @todo: Actually use this instruction.
472 */
473 bool doneTargCalc() { return false; }
474
475 /** Set the predicted target of this current instruction. */
476 void setPredTarg(const TheISA::PCState &_predPC)
477 {
478 predPC = _predPC;
479 }
480
481 const TheISA::PCState &readPredTarg() { return predPC; }
482
483 /** Returns the predicted PC immediately after the branch. */
484 Addr predInstAddr() { return predPC.instAddr(); }
485
486 /** Returns the predicted PC two instructions after the branch */
487 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
488
489 /** Returns the predicted micro PC after the branch */
490 Addr predMicroPC() { return predPC.microPC(); }
491
492 /** Returns whether the instruction was predicted taken or not. */
493 bool readPredTaken()
494 {
495 return instFlags[PredTaken];
496 }
497
498 void setPredTaken(bool predicted_taken)
499 {
500 instFlags[PredTaken] = predicted_taken;
501 }
502
503 /** Returns whether the instruction mispredicted. */
504 bool mispredicted()
505 {
506 TheISA::PCState tempPC = pc;
507 TheISA::advancePC(tempPC, staticInst);
508 return !(tempPC == predPC);
509 }
510
511 //
512 // Instruction types. Forward checks to StaticInst object.
513 //
514 bool isNop() const { return staticInst->isNop(); }
515 bool isMemRef() const { return staticInst->isMemRef(); }
516 bool isLoad() const { return staticInst->isLoad(); }
517 bool isStore() const { return staticInst->isStore(); }
518 bool isStoreConditional() const
519 { return staticInst->isStoreConditional(); }
520 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
521 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
522 bool isInteger() const { return staticInst->isInteger(); }
523 bool isFloating() const { return staticInst->isFloating(); }
524 bool isControl() const { return staticInst->isControl(); }
525 bool isCall() const { return staticInst->isCall(); }
526 bool isReturn() const { return staticInst->isReturn(); }
527 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
528 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
529 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
530 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
531 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
532 bool isThreadSync() const { return staticInst->isThreadSync(); }
533 bool isSerializing() const { return staticInst->isSerializing(); }
534 bool isSerializeBefore() const
535 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
536 bool isSerializeAfter() const
537 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
538 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
539 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
540 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
541 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
542 bool isQuiesce() const { return staticInst->isQuiesce(); }
543 bool isIprAccess() const { return staticInst->isIprAccess(); }
544 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
545 bool isSyscall() const { return staticInst->isSyscall(); }
546 bool isMacroop() const { return staticInst->isMacroop(); }
547 bool isMicroop() const { return staticInst->isMicroop(); }
548 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
549 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
550 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
551 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
552
553 /** Temporarily sets this instruction as a serialize before instruction. */
554 void setSerializeBefore() { status.set(SerializeBefore); }
555
556 /** Clears the serializeBefore part of this instruction. */
557 void clearSerializeBefore() { status.reset(SerializeBefore); }
558
559 /** Checks if this serializeBefore is only temporarily set. */
560 bool isTempSerializeBefore() { return status[SerializeBefore]; }
561
562 /** Temporarily sets this instruction as a serialize after instruction. */
563 void setSerializeAfter() { status.set(SerializeAfter); }
564
565 /** Clears the serializeAfter part of this instruction.*/
566 void clearSerializeAfter() { status.reset(SerializeAfter); }
567
568 /** Checks if this serializeAfter is only temporarily set. */
569 bool isTempSerializeAfter() { return status[SerializeAfter]; }
570
571 /** Sets the serialization part of this instruction as handled. */
572 void setSerializeHandled() { status.set(SerializeHandled); }
573
574 /** Checks if the serialization part of this instruction has been
575 * handled. This does not apply to the temporary serializing
576 * state; it only applies to this instruction's own permanent
577 * serializing state.
578 */
579 bool isSerializeHandled() { return status[SerializeHandled]; }
580
581 /** Returns the opclass of this instruction. */
582 OpClass opClass() const { return staticInst->opClass(); }
583
584 /** Returns the branch target address. */
585 TheISA::PCState branchTarget() const
586 { return staticInst->branchTarget(pc); }
587
588 /** Returns the number of source registers. */
589 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
590
591 /** Returns the number of destination registers. */
592 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
593
594 // the following are used to track physical register usage
595 // for machines with separate int & FP reg files
596 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
597 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
598
599 /** Returns the logical register index of the i'th destination register. */
600 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
601
602 /** Returns the logical register index of the i'th source register. */
603 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
604
605 /** Pops a result off the instResult queue */
606 template <class T>
607 void popResult(T& t)
608 {
609 if (!instResult.empty()) {
610 instResult.front().get(t);
611 instResult.pop();
612 }
613 }
614
615 /** Read the most recent result stored by this instruction */
616 template <class T>
617 void readResult(T& t)
618 {
619 instResult.back().get(t);
620 }
621
622 /** Pushes a result onto the instResult queue */
623 template <class T>
624 void setResult(T t)
625 {
626 if (instFlags[RecordResult]) {
627 Result instRes;
628 instRes.set(t);
629 instResult.push(instRes);
630 }
631 }
632
633 /** Records an integer register being set to a value. */
637 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
634 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
638 {
639 setResult<uint64_t>(val);
640 }
641
642 /** Records a CC register being set to a value. */
635 {
636 setResult<uint64_t>(val);
637 }
638
639 /** Records a CC register being set to a value. */
643 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
640 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
644 {
645 setResult<uint64_t>(val);
646 }
647
648 /** Records an fp register being set to a value. */
641 {
642 setResult<uint64_t>(val);
643 }
644
645 /** Records an fp register being set to a value. */
649 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
650 int width)
651 {
652 if (width == 32 || width == 64) {
653 setResult<double>(val);
654 } else {
655 panic("Unsupported width!");
656 }
657 }
658
659 /** Records an fp register being set to a value. */
660 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
661 {
662 setResult<double>(val);
663 }
664
665 /** Records an fp register being set to an integer value. */
646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
647 {
648 setResult<double>(val);
649 }
650
651 /** Records an fp register being set to an integer value. */
666 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
667 int width)
652 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
668 {
669 setResult<uint64_t>(val);
670 }
671
653 {
654 setResult<uint64_t>(val);
655 }
656
672 /** Records an fp register being set to an integer value. */
673 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
674 {
675 setResult<uint64_t>(val);
676 }
677
678 /** Records that one of the source registers is ready. */
679 void markSrcRegReady();
680
681 /** Marks a specific register as ready. */
682 void markSrcRegReady(RegIndex src_idx);
683
684 /** Returns if a source register is ready. */
685 bool isReadySrcRegIdx(int idx) const
686 {
687 return this->_readySrcRegIdx[idx];
688 }
689
690 /** Sets this instruction as completed. */
691 void setCompleted() { status.set(Completed); }
692
693 /** Returns whether or not this instruction is completed. */
694 bool isCompleted() const { return status[Completed]; }
695
696 /** Marks the result as ready. */
697 void setResultReady() { status.set(ResultReady); }
698
699 /** Returns whether or not the result is ready. */
700 bool isResultReady() const { return status[ResultReady]; }
701
702 /** Sets this instruction as ready to issue. */
703 void setCanIssue() { status.set(CanIssue); }
704
705 /** Returns whether or not this instruction is ready to issue. */
706 bool readyToIssue() const { return status[CanIssue]; }
707
708 /** Clears this instruction being able to issue. */
709 void clearCanIssue() { status.reset(CanIssue); }
710
711 /** Sets this instruction as issued from the IQ. */
712 void setIssued() { status.set(Issued); }
713
714 /** Returns whether or not this instruction has issued. */
715 bool isIssued() const { return status[Issued]; }
716
717 /** Clears this instruction as being issued. */
718 void clearIssued() { status.reset(Issued); }
719
720 /** Sets this instruction as executed. */
721 void setExecuted() { status.set(Executed); }
722
723 /** Returns whether or not this instruction has executed. */
724 bool isExecuted() const { return status[Executed]; }
725
726 /** Sets this instruction as ready to commit. */
727 void setCanCommit() { status.set(CanCommit); }
728
729 /** Clears this instruction as being ready to commit. */
730 void clearCanCommit() { status.reset(CanCommit); }
731
732 /** Returns whether or not this instruction is ready to commit. */
733 bool readyToCommit() const { return status[CanCommit]; }
734
735 void setAtCommit() { status.set(AtCommit); }
736
737 bool isAtCommit() { return status[AtCommit]; }
738
739 /** Sets this instruction as committed. */
740 void setCommitted() { status.set(Committed); }
741
742 /** Returns whether or not this instruction is committed. */
743 bool isCommitted() const { return status[Committed]; }
744
745 /** Sets this instruction as squashed. */
746 void setSquashed() { status.set(Squashed); }
747
748 /** Returns whether or not this instruction is squashed. */
749 bool isSquashed() const { return status[Squashed]; }
750
751 //Instruction Queue Entry
752 //-----------------------
753 /** Sets this instruction as a entry the IQ. */
754 void setInIQ() { status.set(IqEntry); }
755
756 /** Sets this instruction as a entry the IQ. */
757 void clearInIQ() { status.reset(IqEntry); }
758
759 /** Returns whether or not this instruction has issued. */
760 bool isInIQ() const { return status[IqEntry]; }
761
762 /** Sets this instruction as squashed in the IQ. */
763 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
764
765 /** Returns whether or not this instruction is squashed in the IQ. */
766 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
767
768
769 //Load / Store Queue Functions
770 //-----------------------
771 /** Sets this instruction as a entry the LSQ. */
772 void setInLSQ() { status.set(LsqEntry); }
773
774 /** Sets this instruction as a entry the LSQ. */
775 void removeInLSQ() { status.reset(LsqEntry); }
776
777 /** Returns whether or not this instruction is in the LSQ. */
778 bool isInLSQ() const { return status[LsqEntry]; }
779
780 /** Sets this instruction as squashed in the LSQ. */
781 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
782
783 /** Returns whether or not this instruction is squashed in the LSQ. */
784 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
785
786
787 //Reorder Buffer Functions
788 //-----------------------
789 /** Sets this instruction as a entry the ROB. */
790 void setInROB() { status.set(RobEntry); }
791
792 /** Sets this instruction as a entry the ROB. */
793 void clearInROB() { status.reset(RobEntry); }
794
795 /** Returns whether or not this instruction is in the ROB. */
796 bool isInROB() const { return status[RobEntry]; }
797
798 /** Sets this instruction as squashed in the ROB. */
799 void setSquashedInROB() { status.set(SquashedInROB); }
800
801 /** Returns whether or not this instruction is squashed in the ROB. */
802 bool isSquashedInROB() const { return status[SquashedInROB]; }
803
804 /** Read the PC state of this instruction. */
657 /** Records that one of the source registers is ready. */
658 void markSrcRegReady();
659
660 /** Marks a specific register as ready. */
661 void markSrcRegReady(RegIndex src_idx);
662
663 /** Returns if a source register is ready. */
664 bool isReadySrcRegIdx(int idx) const
665 {
666 return this->_readySrcRegIdx[idx];
667 }
668
669 /** Sets this instruction as completed. */
670 void setCompleted() { status.set(Completed); }
671
672 /** Returns whether or not this instruction is completed. */
673 bool isCompleted() const { return status[Completed]; }
674
675 /** Marks the result as ready. */
676 void setResultReady() { status.set(ResultReady); }
677
678 /** Returns whether or not the result is ready. */
679 bool isResultReady() const { return status[ResultReady]; }
680
681 /** Sets this instruction as ready to issue. */
682 void setCanIssue() { status.set(CanIssue); }
683
684 /** Returns whether or not this instruction is ready to issue. */
685 bool readyToIssue() const { return status[CanIssue]; }
686
687 /** Clears this instruction being able to issue. */
688 void clearCanIssue() { status.reset(CanIssue); }
689
690 /** Sets this instruction as issued from the IQ. */
691 void setIssued() { status.set(Issued); }
692
693 /** Returns whether or not this instruction has issued. */
694 bool isIssued() const { return status[Issued]; }
695
696 /** Clears this instruction as being issued. */
697 void clearIssued() { status.reset(Issued); }
698
699 /** Sets this instruction as executed. */
700 void setExecuted() { status.set(Executed); }
701
702 /** Returns whether or not this instruction has executed. */
703 bool isExecuted() const { return status[Executed]; }
704
705 /** Sets this instruction as ready to commit. */
706 void setCanCommit() { status.set(CanCommit); }
707
708 /** Clears this instruction as being ready to commit. */
709 void clearCanCommit() { status.reset(CanCommit); }
710
711 /** Returns whether or not this instruction is ready to commit. */
712 bool readyToCommit() const { return status[CanCommit]; }
713
714 void setAtCommit() { status.set(AtCommit); }
715
716 bool isAtCommit() { return status[AtCommit]; }
717
718 /** Sets this instruction as committed. */
719 void setCommitted() { status.set(Committed); }
720
721 /** Returns whether or not this instruction is committed. */
722 bool isCommitted() const { return status[Committed]; }
723
724 /** Sets this instruction as squashed. */
725 void setSquashed() { status.set(Squashed); }
726
727 /** Returns whether or not this instruction is squashed. */
728 bool isSquashed() const { return status[Squashed]; }
729
730 //Instruction Queue Entry
731 //-----------------------
732 /** Sets this instruction as a entry the IQ. */
733 void setInIQ() { status.set(IqEntry); }
734
735 /** Sets this instruction as a entry the IQ. */
736 void clearInIQ() { status.reset(IqEntry); }
737
738 /** Returns whether or not this instruction has issued. */
739 bool isInIQ() const { return status[IqEntry]; }
740
741 /** Sets this instruction as squashed in the IQ. */
742 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
743
744 /** Returns whether or not this instruction is squashed in the IQ. */
745 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
746
747
748 //Load / Store Queue Functions
749 //-----------------------
750 /** Sets this instruction as a entry the LSQ. */
751 void setInLSQ() { status.set(LsqEntry); }
752
753 /** Sets this instruction as a entry the LSQ. */
754 void removeInLSQ() { status.reset(LsqEntry); }
755
756 /** Returns whether or not this instruction is in the LSQ. */
757 bool isInLSQ() const { return status[LsqEntry]; }
758
759 /** Sets this instruction as squashed in the LSQ. */
760 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
761
762 /** Returns whether or not this instruction is squashed in the LSQ. */
763 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
764
765
766 //Reorder Buffer Functions
767 //-----------------------
768 /** Sets this instruction as a entry the ROB. */
769 void setInROB() { status.set(RobEntry); }
770
771 /** Sets this instruction as a entry the ROB. */
772 void clearInROB() { status.reset(RobEntry); }
773
774 /** Returns whether or not this instruction is in the ROB. */
775 bool isInROB() const { return status[RobEntry]; }
776
777 /** Sets this instruction as squashed in the ROB. */
778 void setSquashedInROB() { status.set(SquashedInROB); }
779
780 /** Returns whether or not this instruction is squashed in the ROB. */
781 bool isSquashedInROB() const { return status[SquashedInROB]; }
782
783 /** Read the PC state of this instruction. */
805 const TheISA::PCState pcState() const { return pc; }
784 TheISA::PCState pcState() const { return pc; }
806
807 /** Set the PC state of this instruction. */
785
786 /** Set the PC state of this instruction. */
808 const void pcState(const TheISA::PCState &val) { pc = val; }
787 void pcState(const TheISA::PCState &val) { pc = val; }
809
810 /** Read the PC of this instruction. */
811 const Addr instAddr() const { return pc.instAddr(); }
812
813 /** Read the PC of the next instruction. */
814 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
815
816 /**Read the micro PC of this instruction. */
817 const Addr microPC() const { return pc.microPC(); }
818
819 bool readPredicate()
820 {
821 return instFlags[Predicate];
822 }
823
824 void setPredicate(bool val)
825 {
826 instFlags[Predicate] = val;
827
828 if (traceData) {
829 traceData->setPredicate(val);
830 }
831 }
832
833 /** Sets the ASID. */
834 void setASID(short addr_space_id) { asid = addr_space_id; }
835
836 /** Sets the thread id. */
837 void setTid(ThreadID tid) { threadNumber = tid; }
838
839 /** Sets the pointer to the thread state. */
840 void setThreadState(ImplState *state) { thread = state; }
841
842 /** Returns the thread context. */
843 ThreadContext *tcBase() { return thread->getTC(); }
844
845 public:
846 /** Sets the effective address. */
788
789 /** Read the PC of this instruction. */
790 const Addr instAddr() const { return pc.instAddr(); }
791
792 /** Read the PC of the next instruction. */
793 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
794
795 /**Read the micro PC of this instruction. */
796 const Addr microPC() const { return pc.microPC(); }
797
798 bool readPredicate()
799 {
800 return instFlags[Predicate];
801 }
802
803 void setPredicate(bool val)
804 {
805 instFlags[Predicate] = val;
806
807 if (traceData) {
808 traceData->setPredicate(val);
809 }
810 }
811
812 /** Sets the ASID. */
813 void setASID(short addr_space_id) { asid = addr_space_id; }
814
815 /** Sets the thread id. */
816 void setTid(ThreadID tid) { threadNumber = tid; }
817
818 /** Sets the pointer to the thread state. */
819 void setThreadState(ImplState *state) { thread = state; }
820
821 /** Returns the thread context. */
822 ThreadContext *tcBase() { return thread->getTC(); }
823
824 public:
825 /** Sets the effective address. */
847 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
826 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
848
849 /** Returns the effective address. */
827
828 /** Returns the effective address. */
850 const Addr &getEA() const { return instEffAddr; }
829 Addr getEA() const { return instEffAddr; }
851
852 /** Returns whether or not the eff. addr. calculation has been completed. */
853 bool doneEACalc() { return instFlags[EACalcDone]; }
854
855 /** Returns whether or not the eff. addr. source registers are ready. */
856 bool eaSrcsReady();
857
858 /** Is this instruction's memory access uncacheable. */
859 bool uncacheable() { return instFlags[IsUncacheable]; }
860
861 /** Has this instruction generated a memory request. */
862 bool hasRequest() { return instFlags[ReqMade]; }
863
864 /** Returns iterator to this instruction in the list of all insts. */
865 ListIt &getInstListIt() { return instListIt; }
866
867 /** Sets iterator for this instruction in the list of all insts. */
868 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
869
870 public:
871 /** Returns the number of consecutive store conditional failures. */
830
831 /** Returns whether or not the eff. addr. calculation has been completed. */
832 bool doneEACalc() { return instFlags[EACalcDone]; }
833
834 /** Returns whether or not the eff. addr. source registers are ready. */
835 bool eaSrcsReady();
836
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return instFlags[IsUncacheable]; }
839
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return instFlags[ReqMade]; }
842
843 /** Returns iterator to this instruction in the list of all insts. */
844 ListIt &getInstListIt() { return instListIt; }
845
846 /** Sets iterator for this instruction in the list of all insts. */
847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
848
849 public:
850 /** Returns the number of consecutive store conditional failures. */
872 unsigned readStCondFailures()
851 unsigned int readStCondFailures() const
873 { return thread->storeCondFailures; }
874
875 /** Sets the number of consecutive store conditional failures. */
852 { return thread->storeCondFailures; }
853
854 /** Sets the number of consecutive store conditional failures. */
876 void setStCondFailures(unsigned sc_failures)
855 void setStCondFailures(unsigned int sc_failures)
877 { thread->storeCondFailures = sc_failures; }
878};
879
880template<class Impl>
881Fault
882BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
883 unsigned size, unsigned flags)
884{
885 instFlags[ReqMade] = true;
886 Request *req = NULL;
887 Request *sreqLow = NULL;
888 Request *sreqHigh = NULL;
889
890 if (instFlags[ReqMade] && translationStarted()) {
891 req = savedReq;
892 sreqLow = savedSreqLow;
893 sreqHigh = savedSreqHigh;
894 } else {
895 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
896 thread->contextId(), threadNumber);
897
898 req->taskId(cpu->taskId());
899
900 // Only split the request if the ISA supports unaligned accesses.
901 if (TheISA::HasUnalignedMemAcc) {
902 splitRequest(req, sreqLow, sreqHigh);
903 }
904 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
905 }
906
907 if (translationCompleted()) {
908 if (fault == NoFault) {
909 effAddr = req->getVaddr();
910 effSize = size;
911 instFlags[EffAddrValid] = true;
912
913 if (cpu->checker) {
914 if (reqToVerify != NULL) {
915 delete reqToVerify;
916 }
917 reqToVerify = new Request(*req);
918 }
919 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
920 } else {
921 // Commit will have to clean up whatever happened. Set this
922 // instruction as executed.
923 this->setExecuted();
924 }
925
926 if (fault != NoFault) {
927 // Return a fixed value to keep simulation deterministic even
928 // along misspeculated paths.
929 if (data)
930 bzero(data, size);
931 }
932 }
933
934 if (traceData) {
935 traceData->setAddr(addr);
936 }
937
938 return fault;
939}
940
941template<class Impl>
942Fault
943BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
944 Addr addr, unsigned flags, uint64_t *res)
945{
946 if (traceData) {
947 traceData->setAddr(addr);
948 }
949
950 instFlags[ReqMade] = true;
951 Request *req = NULL;
952 Request *sreqLow = NULL;
953 Request *sreqHigh = NULL;
954
955 if (instFlags[ReqMade] && translationStarted()) {
956 req = savedReq;
957 sreqLow = savedSreqLow;
958 sreqHigh = savedSreqHigh;
959 } else {
960 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
961 thread->contextId(), threadNumber);
962
963 req->taskId(cpu->taskId());
964
965 // Only split the request if the ISA supports unaligned accesses.
966 if (TheISA::HasUnalignedMemAcc) {
967 splitRequest(req, sreqLow, sreqHigh);
968 }
969 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
970 }
971
972 if (fault == NoFault && translationCompleted()) {
973 effAddr = req->getVaddr();
974 effSize = size;
975 instFlags[EffAddrValid] = true;
976
977 if (cpu->checker) {
978 if (reqToVerify != NULL) {
979 delete reqToVerify;
980 }
981 reqToVerify = new Request(*req);
982 }
983 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
984 }
985
986 return fault;
987}
988
989template<class Impl>
990inline void
991BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
992 RequestPtr &sreqHigh)
993{
994 // Check to see if the request crosses the next level block boundary.
995 unsigned block_size = cpu->cacheLineSize();
996 Addr addr = req->getVaddr();
997 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
998 assert(split_addr <= addr || split_addr - addr < block_size);
999
1000 // Spans two blocks.
1001 if (split_addr > addr) {
1002 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1003 }
1004}
1005
1006template<class Impl>
1007inline void
1008BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1009 RequestPtr sreqHigh, uint64_t *res,
1010 BaseTLB::Mode mode)
1011{
1012 translationStarted(true);
1013
1014 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1015 WholeTranslationState *state =
1016 new WholeTranslationState(req, NULL, res, mode);
1017
1018 // One translation if the request isn't split.
1019 DataTranslation<BaseDynInstPtr> *trans =
1020 new DataTranslation<BaseDynInstPtr>(this, state);
1021
1022 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1023
1024 if (!translationCompleted()) {
1025 // The translation isn't yet complete, so we can't possibly have a
1026 // fault. Overwrite any existing fault we might have from a previous
1027 // execution of this instruction (e.g. an uncachable load that
1028 // couldn't execute because it wasn't at the head of the ROB).
1029 fault = NoFault;
1030
1031 // Save memory requests.
1032 savedReq = state->mainReq;
1033 savedSreqLow = state->sreqLow;
1034 savedSreqHigh = state->sreqHigh;
1035 }
1036 } else {
1037 WholeTranslationState *state =
1038 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1039
1040 // Two translations when the request is split.
1041 DataTranslation<BaseDynInstPtr> *stransLow =
1042 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1043 DataTranslation<BaseDynInstPtr> *stransHigh =
1044 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1045
1046 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1047 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1048
1049 if (!translationCompleted()) {
1050 // The translation isn't yet complete, so we can't possibly have a
1051 // fault. Overwrite any existing fault we might have from a previous
1052 // execution of this instruction (e.g. an uncachable load that
1053 // couldn't execute because it wasn't at the head of the ROB).
1054 fault = NoFault;
1055
1056 // Save memory requests.
1057 savedReq = state->mainReq;
1058 savedSreqLow = state->sreqLow;
1059 savedSreqHigh = state->sreqHigh;
1060 }
1061 }
1062}
1063
1064template<class Impl>
1065inline void
1066BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1067{
1068 fault = state->getFault();
1069
1070 instFlags[IsUncacheable] = state->isUncacheable();
1071
1072 if (fault == NoFault) {
1073 physEffAddr = state->getPaddr();
1074 memReqFlags = state->getFlags();
1075
1076 if (state->mainReq->isCondSwap()) {
1077 assert(state->res);
1078 state->mainReq->setExtraData(*state->res);
1079 }
1080
1081 } else {
1082 state->deleteReqs();
1083 }
1084 delete state;
1085
1086 translationCompleted(true);
1087}
1088
1089#endif // __CPU_BASE_DYN_INST_HH__
856 { thread->storeCondFailures = sc_failures; }
857};
858
859template<class Impl>
860Fault
861BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
862 unsigned size, unsigned flags)
863{
864 instFlags[ReqMade] = true;
865 Request *req = NULL;
866 Request *sreqLow = NULL;
867 Request *sreqHigh = NULL;
868
869 if (instFlags[ReqMade] && translationStarted()) {
870 req = savedReq;
871 sreqLow = savedSreqLow;
872 sreqHigh = savedSreqHigh;
873 } else {
874 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
875 thread->contextId(), threadNumber);
876
877 req->taskId(cpu->taskId());
878
879 // Only split the request if the ISA supports unaligned accesses.
880 if (TheISA::HasUnalignedMemAcc) {
881 splitRequest(req, sreqLow, sreqHigh);
882 }
883 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
884 }
885
886 if (translationCompleted()) {
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
889 effSize = size;
890 instFlags[EffAddrValid] = true;
891
892 if (cpu->checker) {
893 if (reqToVerify != NULL) {
894 delete reqToVerify;
895 }
896 reqToVerify = new Request(*req);
897 }
898 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
899 } else {
900 // Commit will have to clean up whatever happened. Set this
901 // instruction as executed.
902 this->setExecuted();
903 }
904
905 if (fault != NoFault) {
906 // Return a fixed value to keep simulation deterministic even
907 // along misspeculated paths.
908 if (data)
909 bzero(data, size);
910 }
911 }
912
913 if (traceData) {
914 traceData->setAddr(addr);
915 }
916
917 return fault;
918}
919
920template<class Impl>
921Fault
922BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
923 Addr addr, unsigned flags, uint64_t *res)
924{
925 if (traceData) {
926 traceData->setAddr(addr);
927 }
928
929 instFlags[ReqMade] = true;
930 Request *req = NULL;
931 Request *sreqLow = NULL;
932 Request *sreqHigh = NULL;
933
934 if (instFlags[ReqMade] && translationStarted()) {
935 req = savedReq;
936 sreqLow = savedSreqLow;
937 sreqHigh = savedSreqHigh;
938 } else {
939 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
940 thread->contextId(), threadNumber);
941
942 req->taskId(cpu->taskId());
943
944 // Only split the request if the ISA supports unaligned accesses.
945 if (TheISA::HasUnalignedMemAcc) {
946 splitRequest(req, sreqLow, sreqHigh);
947 }
948 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
949 }
950
951 if (fault == NoFault && translationCompleted()) {
952 effAddr = req->getVaddr();
953 effSize = size;
954 instFlags[EffAddrValid] = true;
955
956 if (cpu->checker) {
957 if (reqToVerify != NULL) {
958 delete reqToVerify;
959 }
960 reqToVerify = new Request(*req);
961 }
962 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
963 }
964
965 return fault;
966}
967
968template<class Impl>
969inline void
970BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
971 RequestPtr &sreqHigh)
972{
973 // Check to see if the request crosses the next level block boundary.
974 unsigned block_size = cpu->cacheLineSize();
975 Addr addr = req->getVaddr();
976 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
977 assert(split_addr <= addr || split_addr - addr < block_size);
978
979 // Spans two blocks.
980 if (split_addr > addr) {
981 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
982 }
983}
984
985template<class Impl>
986inline void
987BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
988 RequestPtr sreqHigh, uint64_t *res,
989 BaseTLB::Mode mode)
990{
991 translationStarted(true);
992
993 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
994 WholeTranslationState *state =
995 new WholeTranslationState(req, NULL, res, mode);
996
997 // One translation if the request isn't split.
998 DataTranslation<BaseDynInstPtr> *trans =
999 new DataTranslation<BaseDynInstPtr>(this, state);
1000
1001 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1002
1003 if (!translationCompleted()) {
1004 // The translation isn't yet complete, so we can't possibly have a
1005 // fault. Overwrite any existing fault we might have from a previous
1006 // execution of this instruction (e.g. an uncachable load that
1007 // couldn't execute because it wasn't at the head of the ROB).
1008 fault = NoFault;
1009
1010 // Save memory requests.
1011 savedReq = state->mainReq;
1012 savedSreqLow = state->sreqLow;
1013 savedSreqHigh = state->sreqHigh;
1014 }
1015 } else {
1016 WholeTranslationState *state =
1017 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1018
1019 // Two translations when the request is split.
1020 DataTranslation<BaseDynInstPtr> *stransLow =
1021 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1022 DataTranslation<BaseDynInstPtr> *stransHigh =
1023 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1024
1025 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1026 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1027
1028 if (!translationCompleted()) {
1029 // The translation isn't yet complete, so we can't possibly have a
1030 // fault. Overwrite any existing fault we might have from a previous
1031 // execution of this instruction (e.g. an uncachable load that
1032 // couldn't execute because it wasn't at the head of the ROB).
1033 fault = NoFault;
1034
1035 // Save memory requests.
1036 savedReq = state->mainReq;
1037 savedSreqLow = state->sreqLow;
1038 savedSreqHigh = state->sreqHigh;
1039 }
1040 }
1041}
1042
1043template<class Impl>
1044inline void
1045BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1046{
1047 fault = state->getFault();
1048
1049 instFlags[IsUncacheable] = state->isUncacheable();
1050
1051 if (fault == NoFault) {
1052 physEffAddr = state->getPaddr();
1053 memReqFlags = state->getFlags();
1054
1055 if (state->mainReq->isCondSwap()) {
1056 assert(state->res);
1057 state->mainReq->setExtraData(*state->res);
1058 }
1059
1060 } else {
1061 state->deleteReqs();
1062 }
1063 delete state;
1064
1065 translationCompleted(true);
1066}
1067
1068#endif // __CPU_BASE_DYN_INST_HH__