1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 union Result {
103 uint64_t integer;
104 double dbl;
105 void set(uint64_t i) { integer = i; }
106 void set(double d) { dbl = d; }
107 void get(uint64_t& i) { i = integer; }
108 void get(double& d) { d = dbl; }
109 };
110
111 protected:
112 enum Status {
113 IqEntry, /// Instruction is in the IQ
114 RobEntry, /// Instruction is in the ROB
115 LsqEntry, /// Instruction is in the LSQ
116 Completed, /// Instruction has completed
117 ResultReady, /// Instruction has its result
118 CanIssue, /// Instruction can issue and execute
119 Issued, /// Instruction has issued
120 Executed, /// Instruction has executed
121 CanCommit, /// Instruction can commit
122 AtCommit, /// Instruction has reached commit
123 Committed, /// Instruction has committed
124 Squashed, /// Instruction is squashed
125 SquashedInIQ, /// Instruction is squashed in the IQ
126 SquashedInLSQ, /// Instruction is squashed in the LSQ
127 SquashedInROB, /// Instruction is squashed in the ROB
128 RecoverInst, /// Is a recover instruction
129 BlockingInst, /// Is a blocking instruction
130 ThreadsyncWait, /// Is a thread synchronization instruction
131 SerializeBefore, /// Needs to serialize on
132 /// instructions ahead of it
133 SerializeAfter, /// Needs to serialize instructions behind it
134 SerializeHandled, /// Serialization has been handled
135 NumStatus
136 };
137
138 enum Flags {
139 TranslationStarted,
140 TranslationCompleted,
141 PossibleLoadViolation,
142 HitExternalSnoop,
143 EffAddrValid,
144 RecordResult,
145 Predicate,
146 PredTaken,
147 /** Whether or not the effective address calculation is completed.
148 * @todo: Consider if this is necessary or not.
149 */
150 EACalcDone,
151 IsUncacheable,
152 ReqMade,
153 MemOpDone,
154 MaxFlags
155 };
156
157 public:
158 /** The sequence number of the instruction. */
159 InstSeqNum seqNum;
160
161 /** The StaticInst used by this BaseDynInst. */
162 StaticInstPtr staticInst;
163
164 /** Pointer to the Impl's CPU object. */
165 ImplCPU *cpu;
166
| 1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <bitset>
50#include <list>
51#include <string>
52#include <queue>
53
54#include "arch/utility.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
100 };
101
102 union Result {
103 uint64_t integer;
104 double dbl;
105 void set(uint64_t i) { integer = i; }
106 void set(double d) { dbl = d; }
107 void get(uint64_t& i) { i = integer; }
108 void get(double& d) { d = dbl; }
109 };
110
111 protected:
112 enum Status {
113 IqEntry, /// Instruction is in the IQ
114 RobEntry, /// Instruction is in the ROB
115 LsqEntry, /// Instruction is in the LSQ
116 Completed, /// Instruction has completed
117 ResultReady, /// Instruction has its result
118 CanIssue, /// Instruction can issue and execute
119 Issued, /// Instruction has issued
120 Executed, /// Instruction has executed
121 CanCommit, /// Instruction can commit
122 AtCommit, /// Instruction has reached commit
123 Committed, /// Instruction has committed
124 Squashed, /// Instruction is squashed
125 SquashedInIQ, /// Instruction is squashed in the IQ
126 SquashedInLSQ, /// Instruction is squashed in the LSQ
127 SquashedInROB, /// Instruction is squashed in the ROB
128 RecoverInst, /// Is a recover instruction
129 BlockingInst, /// Is a blocking instruction
130 ThreadsyncWait, /// Is a thread synchronization instruction
131 SerializeBefore, /// Needs to serialize on
132 /// instructions ahead of it
133 SerializeAfter, /// Needs to serialize instructions behind it
134 SerializeHandled, /// Serialization has been handled
135 NumStatus
136 };
137
138 enum Flags {
139 TranslationStarted,
140 TranslationCompleted,
141 PossibleLoadViolation,
142 HitExternalSnoop,
143 EffAddrValid,
144 RecordResult,
145 Predicate,
146 PredTaken,
147 /** Whether or not the effective address calculation is completed.
148 * @todo: Consider if this is necessary or not.
149 */
150 EACalcDone,
151 IsUncacheable,
152 ReqMade,
153 MemOpDone,
154 MaxFlags
155 };
156
157 public:
158 /** The sequence number of the instruction. */
159 InstSeqNum seqNum;
160
161 /** The StaticInst used by this BaseDynInst. */
162 StaticInstPtr staticInst;
163
164 /** Pointer to the Impl's CPU object. */
165 ImplCPU *cpu;
166
|
167 /** Pointer to the thread state. */
168 ImplState *thread;
169
170 /** The kind of fault this instruction has generated. */
171 Fault fault;
172
173 /** InstRecord that tracks this instructions. */
174 Trace::InstRecord *traceData;
175
176 protected:
177 /** The result of the instruction; assumes an instruction can have many
178 * destination registers.
179 */
180 std::queue<Result> instResult;
181
182 /** PC state for this instruction. */
183 TheISA::PCState pc;
184
185 /* An amalgamation of a lot of boolean values into one */
186 std::bitset<MaxFlags> instFlags;
187
188 /** The status of this BaseDynInst. Several bits can be set. */
189 std::bitset<NumStatus> status;
190
191 /** Whether or not the source register is ready.
192 * @todo: Not sure this should be here vs the derived class.
193 */
194 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
195
196 public:
197 /** The thread this instruction is from. */
198 ThreadID threadNumber;
199
200 /** Iterator pointing to this BaseDynInst in the list of all insts. */
201 ListIt instListIt;
202
203 ////////////////////// Branch Data ///////////////
204 /** Predicted PC state after this instruction. */
205 TheISA::PCState predPC;
206
207 /** The Macroop if one exists */
208 StaticInstPtr macroop;
209
210 /** How many source registers are ready. */
211 uint8_t readyRegs;
212
213 public:
214 /////////////////////// Load Store Data //////////////////////
215 /** The effective virtual address (lds & stores only). */
216 Addr effAddr;
217
218 /** The effective physical address. */
219 Addr physEffAddr;
220
221 /** The memory request flags (from translation). */
222 unsigned memReqFlags;
223
224 /** data address space ID, for loads & stores. */
225 short asid;
226
227 /** The size of the request */
228 uint8_t effSize;
229
230 /** Pointer to the data for the memory access. */
231 uint8_t *memData;
232
233 /** Load queue index. */
234 int16_t lqIdx;
235
236 /** Store queue index. */
237 int16_t sqIdx;
238
239
240 /////////////////////// TLB Miss //////////////////////
241 /**
242 * Saved memory requests (needed when the DTB address translation is
243 * delayed due to a hw page table walk).
244 */
245 RequestPtr savedReq;
246 RequestPtr savedSreqLow;
247 RequestPtr savedSreqHigh;
248
249 /////////////////////// Checker //////////////////////
250 // Need a copy of main request pointer to verify on writes.
251 RequestPtr reqToVerify;
252
253 private:
254 /** Instruction effective address.
255 * @todo: Consider if this is necessary or not.
256 */
257 Addr instEffAddr;
258
259 protected:
260 /** Flattened register index of the destination registers of this
261 * instruction.
262 */
263 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
264
265 /** Physical register index of the destination registers of this
266 * instruction.
267 */
268 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
269
270 /** Physical register index of the source registers of this
271 * instruction.
272 */
273 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
274
275 /** Physical register index of the previous producers of the
276 * architected destinations.
277 */
278 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
279
280
281 public:
282 /** Records changes to result? */
283 void recordResult(bool f) { instFlags[RecordResult] = f; }
284
285 /** Is the effective virtual address valid. */
286 bool effAddrValid() const { return instFlags[EffAddrValid]; }
287
288 /** Whether or not the memory operation is done. */
289 bool memOpDone() const { return instFlags[MemOpDone]; }
290 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
291
292
293 ////////////////////////////////////////////
294 //
295 // INSTRUCTION EXECUTION
296 //
297 ////////////////////////////////////////////
298
299 void demapPage(Addr vaddr, uint64_t asn)
300 {
301 cpu->demapPage(vaddr, asn);
302 }
303 void demapInstPage(Addr vaddr, uint64_t asn)
304 {
305 cpu->demapPage(vaddr, asn);
306 }
307 void demapDataPage(Addr vaddr, uint64_t asn)
308 {
309 cpu->demapPage(vaddr, asn);
310 }
311
312 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
313
314 Fault writeMem(uint8_t *data, unsigned size,
315 Addr addr, unsigned flags, uint64_t *res);
316
317 /** Splits a request in two if it crosses a dcache block. */
318 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
319 RequestPtr &sreqHigh);
320
321 /** Initiate a DTB address translation. */
322 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
323 RequestPtr sreqHigh, uint64_t *res,
324 BaseTLB::Mode mode);
325
326 /** Finish a DTB address translation. */
327 void finishTranslation(WholeTranslationState *state);
328
329 /** True if the DTB address translation has started. */
330 bool translationStarted() const { return instFlags[TranslationStarted]; }
331 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
332
333 /** True if the DTB address translation has completed. */
334 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
335 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
336
337 /** True if this address was found to match a previous load and they issued
338 * out of order. If that happend, then it's only a problem if an incoming
339 * snoop invalidate modifies the line, in which case we need to squash.
340 * If nothing modified the line the order doesn't matter.
341 */
342 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
343 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
344
345 /** True if the address hit a external snoop while sitting in the LSQ.
346 * If this is true and a older instruction sees it, this instruction must
347 * reexecute
348 */
349 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
350 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
351
352 /**
353 * Returns true if the DTB address translation is being delayed due to a hw
354 * page table walk.
355 */
356 bool isTranslationDelayed() const
357 {
358 return (translationStarted() && !translationCompleted());
359 }
360
361 public:
362#ifdef DEBUG
363 void dumpSNList();
364#endif
365
366 /** Returns the physical register index of the i'th destination
367 * register.
368 */
369 PhysRegIndex renamedDestRegIdx(int idx) const
370 {
371 return _destRegIdx[idx];
372 }
373
374 /** Returns the physical register index of the i'th source register. */
375 PhysRegIndex renamedSrcRegIdx(int idx) const
376 {
377 assert(TheISA::MaxInstSrcRegs > idx);
378 return _srcRegIdx[idx];
379 }
380
381 /** Returns the flattened register index of the i'th destination
382 * register.
383 */
384 TheISA::RegIndex flattenedDestRegIdx(int idx) const
385 {
386 return _flatDestRegIdx[idx];
387 }
388
389 /** Returns the physical register index of the previous physical register
390 * that remapped to the same logical register index.
391 */
392 PhysRegIndex prevDestRegIdx(int idx) const
393 {
394 return _prevDestRegIdx[idx];
395 }
396
397 /** Renames a destination register to a physical register. Also records
398 * the previous physical register that the logical register mapped to.
399 */
400 void renameDestReg(int idx,
401 PhysRegIndex renamed_dest,
402 PhysRegIndex previous_rename)
403 {
404 _destRegIdx[idx] = renamed_dest;
405 _prevDestRegIdx[idx] = previous_rename;
406 }
407
408 /** Renames a source logical register to the physical register which
409 * has/will produce that logical register's result.
410 * @todo: add in whether or not the source register is ready.
411 */
412 void renameSrcReg(int idx, PhysRegIndex renamed_src)
413 {
414 _srcRegIdx[idx] = renamed_src;
415 }
416
417 /** Flattens a destination architectural register index into a logical
418 * index.
419 */
420 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
421 {
422 _flatDestRegIdx[idx] = flattened_dest;
423 }
424 /** BaseDynInst constructor given a binary instruction.
425 * @param staticInst A StaticInstPtr to the underlying instruction.
426 * @param pc The PC state for the instruction.
427 * @param predPC The predicted next PC state for the instruction.
428 * @param seq_num The sequence number of the instruction.
429 * @param cpu Pointer to the instruction's CPU.
430 */
431 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
432 TheISA::PCState pc, TheISA::PCState predPC,
433 InstSeqNum seq_num, ImplCPU *cpu);
434
435 /** BaseDynInst constructor given a StaticInst pointer.
436 * @param _staticInst The StaticInst for this BaseDynInst.
437 */
438 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
439
440 /** BaseDynInst destructor. */
441 ~BaseDynInst();
442
443 private:
444 /** Function to initialize variables in the constructors. */
445 void initVars();
446
447 public:
448 /** Dumps out contents of this BaseDynInst. */
449 void dump();
450
451 /** Dumps out contents of this BaseDynInst into given string. */
452 void dump(std::string &outstring);
453
454 /** Read this CPU's ID. */
455 int cpuId() { return cpu->cpuId(); }
456
457 /** Read this CPU's data requestor ID */
458 MasterID masterId() { return cpu->dataMasterId(); }
459
460 /** Read this context's system-wide ID **/
461 int contextId() { return thread->contextId(); }
462
463 /** Returns the fault type. */
464 Fault getFault() { return fault; }
465
466 /** Checks whether or not this instruction has had its branch target
467 * calculated yet. For now it is not utilized and is hacked to be
468 * always false.
469 * @todo: Actually use this instruction.
470 */
471 bool doneTargCalc() { return false; }
472
473 /** Set the predicted target of this current instruction. */
474 void setPredTarg(const TheISA::PCState &_predPC)
475 {
476 predPC = _predPC;
477 }
478
479 const TheISA::PCState &readPredTarg() { return predPC; }
480
481 /** Returns the predicted PC immediately after the branch. */
482 Addr predInstAddr() { return predPC.instAddr(); }
483
484 /** Returns the predicted PC two instructions after the branch */
485 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
486
487 /** Returns the predicted micro PC after the branch */
488 Addr predMicroPC() { return predPC.microPC(); }
489
490 /** Returns whether the instruction was predicted taken or not. */
491 bool readPredTaken()
492 {
493 return instFlags[PredTaken];
494 }
495
496 void setPredTaken(bool predicted_taken)
497 {
498 instFlags[PredTaken] = predicted_taken;
499 }
500
501 /** Returns whether the instruction mispredicted. */
502 bool mispredicted()
503 {
504 TheISA::PCState tempPC = pc;
505 TheISA::advancePC(tempPC, staticInst);
506 return !(tempPC == predPC);
507 }
508
509 //
510 // Instruction types. Forward checks to StaticInst object.
511 //
512 bool isNop() const { return staticInst->isNop(); }
513 bool isMemRef() const { return staticInst->isMemRef(); }
514 bool isLoad() const { return staticInst->isLoad(); }
515 bool isStore() const { return staticInst->isStore(); }
516 bool isStoreConditional() const
517 { return staticInst->isStoreConditional(); }
518 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
519 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
520 bool isInteger() const { return staticInst->isInteger(); }
521 bool isFloating() const { return staticInst->isFloating(); }
522 bool isControl() const { return staticInst->isControl(); }
523 bool isCall() const { return staticInst->isCall(); }
524 bool isReturn() const { return staticInst->isReturn(); }
525 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
526 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
527 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
528 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
529 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
530 bool isThreadSync() const { return staticInst->isThreadSync(); }
531 bool isSerializing() const { return staticInst->isSerializing(); }
532 bool isSerializeBefore() const
533 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
534 bool isSerializeAfter() const
535 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
536 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
537 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
538 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
539 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
540 bool isQuiesce() const { return staticInst->isQuiesce(); }
541 bool isIprAccess() const { return staticInst->isIprAccess(); }
542 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
543 bool isSyscall() const { return staticInst->isSyscall(); }
544 bool isMacroop() const { return staticInst->isMacroop(); }
545 bool isMicroop() const { return staticInst->isMicroop(); }
546 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
547 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
548 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
549 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
550
551 /** Temporarily sets this instruction as a serialize before instruction. */
552 void setSerializeBefore() { status.set(SerializeBefore); }
553
554 /** Clears the serializeBefore part of this instruction. */
555 void clearSerializeBefore() { status.reset(SerializeBefore); }
556
557 /** Checks if this serializeBefore is only temporarily set. */
558 bool isTempSerializeBefore() { return status[SerializeBefore]; }
559
560 /** Temporarily sets this instruction as a serialize after instruction. */
561 void setSerializeAfter() { status.set(SerializeAfter); }
562
563 /** Clears the serializeAfter part of this instruction.*/
564 void clearSerializeAfter() { status.reset(SerializeAfter); }
565
566 /** Checks if this serializeAfter is only temporarily set. */
567 bool isTempSerializeAfter() { return status[SerializeAfter]; }
568
569 /** Sets the serialization part of this instruction as handled. */
570 void setSerializeHandled() { status.set(SerializeHandled); }
571
572 /** Checks if the serialization part of this instruction has been
573 * handled. This does not apply to the temporary serializing
574 * state; it only applies to this instruction's own permanent
575 * serializing state.
576 */
577 bool isSerializeHandled() { return status[SerializeHandled]; }
578
579 /** Returns the opclass of this instruction. */
580 OpClass opClass() const { return staticInst->opClass(); }
581
582 /** Returns the branch target address. */
583 TheISA::PCState branchTarget() const
584 { return staticInst->branchTarget(pc); }
585
586 /** Returns the number of source registers. */
587 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
588
589 /** Returns the number of destination registers. */
590 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
591
592 // the following are used to track physical register usage
593 // for machines with separate int & FP reg files
594 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
595 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
596
597 /** Returns the logical register index of the i'th destination register. */
598 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
599
600 /** Returns the logical register index of the i'th source register. */
601 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
602
603 /** Pops a result off the instResult queue */
604 template <class T>
605 void popResult(T& t)
606 {
607 if (!instResult.empty()) {
608 instResult.front().get(t);
609 instResult.pop();
610 }
611 }
612
613 /** Read the most recent result stored by this instruction */
614 template <class T>
615 void readResult(T& t)
616 {
617 instResult.back().get(t);
618 }
619
620 /** Pushes a result onto the instResult queue */
621 template <class T>
622 void setResult(T t)
623 {
624 if (instFlags[RecordResult]) {
625 Result instRes;
626 instRes.set(t);
627 instResult.push(instRes);
628 }
629 }
630
631 /** Records an integer register being set to a value. */
632 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
633 {
634 setResult<uint64_t>(val);
635 }
636
637 /** Records a CC register being set to a value. */
638 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
639 {
640 setResult<uint64_t>(val);
641 }
642
643 /** Records an fp register being set to a value. */
644 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
645 int width)
646 {
647 if (width == 32 || width == 64) {
648 setResult<double>(val);
649 } else {
650 panic("Unsupported width!");
651 }
652 }
653
654 /** Records an fp register being set to a value. */
655 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
656 {
657 setResult<double>(val);
658 }
659
660 /** Records an fp register being set to an integer value. */
661 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
662 int width)
663 {
664 setResult<uint64_t>(val);
665 }
666
667 /** Records an fp register being set to an integer value. */
668 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
669 {
670 setResult<uint64_t>(val);
671 }
672
673 /** Records that one of the source registers is ready. */
674 void markSrcRegReady();
675
676 /** Marks a specific register as ready. */
677 void markSrcRegReady(RegIndex src_idx);
678
679 /** Returns if a source register is ready. */
680 bool isReadySrcRegIdx(int idx) const
681 {
682 return this->_readySrcRegIdx[idx];
683 }
684
685 /** Sets this instruction as completed. */
686 void setCompleted() { status.set(Completed); }
687
688 /** Returns whether or not this instruction is completed. */
689 bool isCompleted() const { return status[Completed]; }
690
691 /** Marks the result as ready. */
692 void setResultReady() { status.set(ResultReady); }
693
694 /** Returns whether or not the result is ready. */
695 bool isResultReady() const { return status[ResultReady]; }
696
697 /** Sets this instruction as ready to issue. */
698 void setCanIssue() { status.set(CanIssue); }
699
700 /** Returns whether or not this instruction is ready to issue. */
701 bool readyToIssue() const { return status[CanIssue]; }
702
703 /** Clears this instruction being able to issue. */
704 void clearCanIssue() { status.reset(CanIssue); }
705
706 /** Sets this instruction as issued from the IQ. */
707 void setIssued() { status.set(Issued); }
708
709 /** Returns whether or not this instruction has issued. */
710 bool isIssued() const { return status[Issued]; }
711
712 /** Clears this instruction as being issued. */
713 void clearIssued() { status.reset(Issued); }
714
715 /** Sets this instruction as executed. */
716 void setExecuted() { status.set(Executed); }
717
718 /** Returns whether or not this instruction has executed. */
719 bool isExecuted() const { return status[Executed]; }
720
721 /** Sets this instruction as ready to commit. */
722 void setCanCommit() { status.set(CanCommit); }
723
724 /** Clears this instruction as being ready to commit. */
725 void clearCanCommit() { status.reset(CanCommit); }
726
727 /** Returns whether or not this instruction is ready to commit. */
728 bool readyToCommit() const { return status[CanCommit]; }
729
730 void setAtCommit() { status.set(AtCommit); }
731
732 bool isAtCommit() { return status[AtCommit]; }
733
734 /** Sets this instruction as committed. */
735 void setCommitted() { status.set(Committed); }
736
737 /** Returns whether or not this instruction is committed. */
738 bool isCommitted() const { return status[Committed]; }
739
740 /** Sets this instruction as squashed. */
741 void setSquashed() { status.set(Squashed); }
742
743 /** Returns whether or not this instruction is squashed. */
744 bool isSquashed() const { return status[Squashed]; }
745
746 //Instruction Queue Entry
747 //-----------------------
748 /** Sets this instruction as a entry the IQ. */
749 void setInIQ() { status.set(IqEntry); }
750
751 /** Sets this instruction as a entry the IQ. */
752 void clearInIQ() { status.reset(IqEntry); }
753
754 /** Returns whether or not this instruction has issued. */
755 bool isInIQ() const { return status[IqEntry]; }
756
757 /** Sets this instruction as squashed in the IQ. */
758 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
759
760 /** Returns whether or not this instruction is squashed in the IQ. */
761 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
762
763
764 //Load / Store Queue Functions
765 //-----------------------
766 /** Sets this instruction as a entry the LSQ. */
767 void setInLSQ() { status.set(LsqEntry); }
768
769 /** Sets this instruction as a entry the LSQ. */
770 void removeInLSQ() { status.reset(LsqEntry); }
771
772 /** Returns whether or not this instruction is in the LSQ. */
773 bool isInLSQ() const { return status[LsqEntry]; }
774
775 /** Sets this instruction as squashed in the LSQ. */
776 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
777
778 /** Returns whether or not this instruction is squashed in the LSQ. */
779 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
780
781
782 //Reorder Buffer Functions
783 //-----------------------
784 /** Sets this instruction as a entry the ROB. */
785 void setInROB() { status.set(RobEntry); }
786
787 /** Sets this instruction as a entry the ROB. */
788 void clearInROB() { status.reset(RobEntry); }
789
790 /** Returns whether or not this instruction is in the ROB. */
791 bool isInROB() const { return status[RobEntry]; }
792
793 /** Sets this instruction as squashed in the ROB. */
794 void setSquashedInROB() { status.set(SquashedInROB); }
795
796 /** Returns whether or not this instruction is squashed in the ROB. */
797 bool isSquashedInROB() const { return status[SquashedInROB]; }
798
799 /** Read the PC state of this instruction. */
800 const TheISA::PCState pcState() const { return pc; }
801
802 /** Set the PC state of this instruction. */
803 const void pcState(const TheISA::PCState &val) { pc = val; }
804
805 /** Read the PC of this instruction. */
806 const Addr instAddr() const { return pc.instAddr(); }
807
808 /** Read the PC of the next instruction. */
809 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
810
811 /**Read the micro PC of this instruction. */
812 const Addr microPC() const { return pc.microPC(); }
813
814 bool readPredicate()
815 {
816 return instFlags[Predicate];
817 }
818
819 void setPredicate(bool val)
820 {
821 instFlags[Predicate] = val;
822
823 if (traceData) {
824 traceData->setPredicate(val);
825 }
826 }
827
828 /** Sets the ASID. */
829 void setASID(short addr_space_id) { asid = addr_space_id; }
830
831 /** Sets the thread id. */
832 void setTid(ThreadID tid) { threadNumber = tid; }
833
834 /** Sets the pointer to the thread state. */
835 void setThreadState(ImplState *state) { thread = state; }
836
837 /** Returns the thread context. */
838 ThreadContext *tcBase() { return thread->getTC(); }
839
840 public:
841 /** Sets the effective address. */
842 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
843
844 /** Returns the effective address. */
845 const Addr &getEA() const { return instEffAddr; }
846
847 /** Returns whether or not the eff. addr. calculation has been completed. */
848 bool doneEACalc() { return instFlags[EACalcDone]; }
849
850 /** Returns whether or not the eff. addr. source registers are ready. */
851 bool eaSrcsReady();
852
853 /** Is this instruction's memory access uncacheable. */
854 bool uncacheable() { return instFlags[IsUncacheable]; }
855
856 /** Has this instruction generated a memory request. */
857 bool hasRequest() { return instFlags[ReqMade]; }
858
859 /** Returns iterator to this instruction in the list of all insts. */
860 ListIt &getInstListIt() { return instListIt; }
861
862 /** Sets iterator for this instruction in the list of all insts. */
863 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
864
865 public:
866 /** Returns the number of consecutive store conditional failures. */
867 unsigned readStCondFailures()
868 { return thread->storeCondFailures; }
869
870 /** Sets the number of consecutive store conditional failures. */
871 void setStCondFailures(unsigned sc_failures)
872 { thread->storeCondFailures = sc_failures; }
873};
874
875template<class Impl>
876Fault
877BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
878 unsigned size, unsigned flags)
879{
880 instFlags[ReqMade] = true;
881 Request *req = NULL;
882 Request *sreqLow = NULL;
883 Request *sreqHigh = NULL;
884
885 if (instFlags[ReqMade] && translationStarted()) {
886 req = savedReq;
887 sreqLow = savedSreqLow;
888 sreqHigh = savedSreqHigh;
889 } else {
890 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
891 thread->contextId(), threadNumber);
892
893 req->taskId(cpu->taskId());
894
895 // Only split the request if the ISA supports unaligned accesses.
896 if (TheISA::HasUnalignedMemAcc) {
897 splitRequest(req, sreqLow, sreqHigh);
898 }
899 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
900 }
901
902 if (translationCompleted()) {
903 if (fault == NoFault) {
904 effAddr = req->getVaddr();
905 effSize = size;
906 instFlags[EffAddrValid] = true;
907
908 if (cpu->checker) {
909 if (reqToVerify != NULL) {
910 delete reqToVerify;
911 }
912 reqToVerify = new Request(*req);
913 }
914 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
915 } else {
916 // Commit will have to clean up whatever happened. Set this
917 // instruction as executed.
918 this->setExecuted();
919 }
920
921 if (fault != NoFault) {
922 // Return a fixed value to keep simulation deterministic even
923 // along misspeculated paths.
924 if (data)
925 bzero(data, size);
926 }
927 }
928
929 if (traceData) {
930 traceData->setAddr(addr);
931 }
932
933 return fault;
934}
935
936template<class Impl>
937Fault
938BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
939 Addr addr, unsigned flags, uint64_t *res)
940{
941 if (traceData) {
942 traceData->setAddr(addr);
943 }
944
945 instFlags[ReqMade] = true;
946 Request *req = NULL;
947 Request *sreqLow = NULL;
948 Request *sreqHigh = NULL;
949
950 if (instFlags[ReqMade] && translationStarted()) {
951 req = savedReq;
952 sreqLow = savedSreqLow;
953 sreqHigh = savedSreqHigh;
954 } else {
955 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
956 thread->contextId(), threadNumber);
957
958 req->taskId(cpu->taskId());
959
960 // Only split the request if the ISA supports unaligned accesses.
961 if (TheISA::HasUnalignedMemAcc) {
962 splitRequest(req, sreqLow, sreqHigh);
963 }
964 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
965 }
966
967 if (fault == NoFault && translationCompleted()) {
968 effAddr = req->getVaddr();
969 effSize = size;
970 instFlags[EffAddrValid] = true;
971
972 if (cpu->checker) {
973 if (reqToVerify != NULL) {
974 delete reqToVerify;
975 }
976 reqToVerify = new Request(*req);
977 }
978 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
979 }
980
981 return fault;
982}
983
984template<class Impl>
985inline void
986BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
987 RequestPtr &sreqHigh)
988{
989 // Check to see if the request crosses the next level block boundary.
990 unsigned block_size = cpu->cacheLineSize();
991 Addr addr = req->getVaddr();
992 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
993 assert(split_addr <= addr || split_addr - addr < block_size);
994
995 // Spans two blocks.
996 if (split_addr > addr) {
997 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
998 }
999}
1000
1001template<class Impl>
1002inline void
1003BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1004 RequestPtr sreqHigh, uint64_t *res,
1005 BaseTLB::Mode mode)
1006{
1007 translationStarted(true);
1008
1009 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1010 WholeTranslationState *state =
1011 new WholeTranslationState(req, NULL, res, mode);
1012
1013 // One translation if the request isn't split.
1014 DataTranslation<BaseDynInstPtr> *trans =
1015 new DataTranslation<BaseDynInstPtr>(this, state);
1016
1017 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1018
1019 if (!translationCompleted()) {
1020 // The translation isn't yet complete, so we can't possibly have a
1021 // fault. Overwrite any existing fault we might have from a previous
1022 // execution of this instruction (e.g. an uncachable load that
1023 // couldn't execute because it wasn't at the head of the ROB).
1024 fault = NoFault;
1025
1026 // Save memory requests.
1027 savedReq = state->mainReq;
1028 savedSreqLow = state->sreqLow;
1029 savedSreqHigh = state->sreqHigh;
1030 }
1031 } else {
1032 WholeTranslationState *state =
1033 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1034
1035 // Two translations when the request is split.
1036 DataTranslation<BaseDynInstPtr> *stransLow =
1037 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1038 DataTranslation<BaseDynInstPtr> *stransHigh =
1039 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1040
1041 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1042 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1043
1044 if (!translationCompleted()) {
1045 // The translation isn't yet complete, so we can't possibly have a
1046 // fault. Overwrite any existing fault we might have from a previous
1047 // execution of this instruction (e.g. an uncachable load that
1048 // couldn't execute because it wasn't at the head of the ROB).
1049 fault = NoFault;
1050
1051 // Save memory requests.
1052 savedReq = state->mainReq;
1053 savedSreqLow = state->sreqLow;
1054 savedSreqHigh = state->sreqHigh;
1055 }
1056 }
1057}
1058
1059template<class Impl>
1060inline void
1061BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1062{
1063 fault = state->getFault();
1064
1065 instFlags[IsUncacheable] = state->isUncacheable();
1066
1067 if (fault == NoFault) {
1068 physEffAddr = state->getPaddr();
1069 memReqFlags = state->getFlags();
1070
1071 if (state->mainReq->isCondSwap()) {
1072 assert(state->res);
1073 state->mainReq->setExtraData(*state->res);
1074 }
1075
1076 } else {
1077 state->deleteReqs();
1078 }
1079 delete state;
1080
1081 translationCompleted(true);
1082}
1083
1084#endif // __CPU_BASE_DYN_INST_HH__
| 169 /** Pointer to the thread state. */
170 ImplState *thread;
171
172 /** The kind of fault this instruction has generated. */
173 Fault fault;
174
175 /** InstRecord that tracks this instructions. */
176 Trace::InstRecord *traceData;
177
178 protected:
179 /** The result of the instruction; assumes an instruction can have many
180 * destination registers.
181 */
182 std::queue<Result> instResult;
183
184 /** PC state for this instruction. */
185 TheISA::PCState pc;
186
187 /* An amalgamation of a lot of boolean values into one */
188 std::bitset<MaxFlags> instFlags;
189
190 /** The status of this BaseDynInst. Several bits can be set. */
191 std::bitset<NumStatus> status;
192
193 /** Whether or not the source register is ready.
194 * @todo: Not sure this should be here vs the derived class.
195 */
196 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
197
198 public:
199 /** The thread this instruction is from. */
200 ThreadID threadNumber;
201
202 /** Iterator pointing to this BaseDynInst in the list of all insts. */
203 ListIt instListIt;
204
205 ////////////////////// Branch Data ///////////////
206 /** Predicted PC state after this instruction. */
207 TheISA::PCState predPC;
208
209 /** The Macroop if one exists */
210 StaticInstPtr macroop;
211
212 /** How many source registers are ready. */
213 uint8_t readyRegs;
214
215 public:
216 /////////////////////// Load Store Data //////////////////////
217 /** The effective virtual address (lds & stores only). */
218 Addr effAddr;
219
220 /** The effective physical address. */
221 Addr physEffAddr;
222
223 /** The memory request flags (from translation). */
224 unsigned memReqFlags;
225
226 /** data address space ID, for loads & stores. */
227 short asid;
228
229 /** The size of the request */
230 uint8_t effSize;
231
232 /** Pointer to the data for the memory access. */
233 uint8_t *memData;
234
235 /** Load queue index. */
236 int16_t lqIdx;
237
238 /** Store queue index. */
239 int16_t sqIdx;
240
241
242 /////////////////////// TLB Miss //////////////////////
243 /**
244 * Saved memory requests (needed when the DTB address translation is
245 * delayed due to a hw page table walk).
246 */
247 RequestPtr savedReq;
248 RequestPtr savedSreqLow;
249 RequestPtr savedSreqHigh;
250
251 /////////////////////// Checker //////////////////////
252 // Need a copy of main request pointer to verify on writes.
253 RequestPtr reqToVerify;
254
255 private:
256 /** Instruction effective address.
257 * @todo: Consider if this is necessary or not.
258 */
259 Addr instEffAddr;
260
261 protected:
262 /** Flattened register index of the destination registers of this
263 * instruction.
264 */
265 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
266
267 /** Physical register index of the destination registers of this
268 * instruction.
269 */
270 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
271
272 /** Physical register index of the source registers of this
273 * instruction.
274 */
275 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
276
277 /** Physical register index of the previous producers of the
278 * architected destinations.
279 */
280 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
281
282
283 public:
284 /** Records changes to result? */
285 void recordResult(bool f) { instFlags[RecordResult] = f; }
286
287 /** Is the effective virtual address valid. */
288 bool effAddrValid() const { return instFlags[EffAddrValid]; }
289
290 /** Whether or not the memory operation is done. */
291 bool memOpDone() const { return instFlags[MemOpDone]; }
292 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
293
294
295 ////////////////////////////////////////////
296 //
297 // INSTRUCTION EXECUTION
298 //
299 ////////////////////////////////////////////
300
301 void demapPage(Addr vaddr, uint64_t asn)
302 {
303 cpu->demapPage(vaddr, asn);
304 }
305 void demapInstPage(Addr vaddr, uint64_t asn)
306 {
307 cpu->demapPage(vaddr, asn);
308 }
309 void demapDataPage(Addr vaddr, uint64_t asn)
310 {
311 cpu->demapPage(vaddr, asn);
312 }
313
314 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
315
316 Fault writeMem(uint8_t *data, unsigned size,
317 Addr addr, unsigned flags, uint64_t *res);
318
319 /** Splits a request in two if it crosses a dcache block. */
320 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
321 RequestPtr &sreqHigh);
322
323 /** Initiate a DTB address translation. */
324 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
325 RequestPtr sreqHigh, uint64_t *res,
326 BaseTLB::Mode mode);
327
328 /** Finish a DTB address translation. */
329 void finishTranslation(WholeTranslationState *state);
330
331 /** True if the DTB address translation has started. */
332 bool translationStarted() const { return instFlags[TranslationStarted]; }
333 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
334
335 /** True if the DTB address translation has completed. */
336 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
337 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
338
339 /** True if this address was found to match a previous load and they issued
340 * out of order. If that happend, then it's only a problem if an incoming
341 * snoop invalidate modifies the line, in which case we need to squash.
342 * If nothing modified the line the order doesn't matter.
343 */
344 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
345 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
346
347 /** True if the address hit a external snoop while sitting in the LSQ.
348 * If this is true and a older instruction sees it, this instruction must
349 * reexecute
350 */
351 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
352 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
353
354 /**
355 * Returns true if the DTB address translation is being delayed due to a hw
356 * page table walk.
357 */
358 bool isTranslationDelayed() const
359 {
360 return (translationStarted() && !translationCompleted());
361 }
362
363 public:
364#ifdef DEBUG
365 void dumpSNList();
366#endif
367
368 /** Returns the physical register index of the i'th destination
369 * register.
370 */
371 PhysRegIndex renamedDestRegIdx(int idx) const
372 {
373 return _destRegIdx[idx];
374 }
375
376 /** Returns the physical register index of the i'th source register. */
377 PhysRegIndex renamedSrcRegIdx(int idx) const
378 {
379 assert(TheISA::MaxInstSrcRegs > idx);
380 return _srcRegIdx[idx];
381 }
382
383 /** Returns the flattened register index of the i'th destination
384 * register.
385 */
386 TheISA::RegIndex flattenedDestRegIdx(int idx) const
387 {
388 return _flatDestRegIdx[idx];
389 }
390
391 /** Returns the physical register index of the previous physical register
392 * that remapped to the same logical register index.
393 */
394 PhysRegIndex prevDestRegIdx(int idx) const
395 {
396 return _prevDestRegIdx[idx];
397 }
398
399 /** Renames a destination register to a physical register. Also records
400 * the previous physical register that the logical register mapped to.
401 */
402 void renameDestReg(int idx,
403 PhysRegIndex renamed_dest,
404 PhysRegIndex previous_rename)
405 {
406 _destRegIdx[idx] = renamed_dest;
407 _prevDestRegIdx[idx] = previous_rename;
408 }
409
410 /** Renames a source logical register to the physical register which
411 * has/will produce that logical register's result.
412 * @todo: add in whether or not the source register is ready.
413 */
414 void renameSrcReg(int idx, PhysRegIndex renamed_src)
415 {
416 _srcRegIdx[idx] = renamed_src;
417 }
418
419 /** Flattens a destination architectural register index into a logical
420 * index.
421 */
422 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
423 {
424 _flatDestRegIdx[idx] = flattened_dest;
425 }
426 /** BaseDynInst constructor given a binary instruction.
427 * @param staticInst A StaticInstPtr to the underlying instruction.
428 * @param pc The PC state for the instruction.
429 * @param predPC The predicted next PC state for the instruction.
430 * @param seq_num The sequence number of the instruction.
431 * @param cpu Pointer to the instruction's CPU.
432 */
433 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
434 TheISA::PCState pc, TheISA::PCState predPC,
435 InstSeqNum seq_num, ImplCPU *cpu);
436
437 /** BaseDynInst constructor given a StaticInst pointer.
438 * @param _staticInst The StaticInst for this BaseDynInst.
439 */
440 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
441
442 /** BaseDynInst destructor. */
443 ~BaseDynInst();
444
445 private:
446 /** Function to initialize variables in the constructors. */
447 void initVars();
448
449 public:
450 /** Dumps out contents of this BaseDynInst. */
451 void dump();
452
453 /** Dumps out contents of this BaseDynInst into given string. */
454 void dump(std::string &outstring);
455
456 /** Read this CPU's ID. */
457 int cpuId() { return cpu->cpuId(); }
458
459 /** Read this CPU's data requestor ID */
460 MasterID masterId() { return cpu->dataMasterId(); }
461
462 /** Read this context's system-wide ID **/
463 int contextId() { return thread->contextId(); }
464
465 /** Returns the fault type. */
466 Fault getFault() { return fault; }
467
468 /** Checks whether or not this instruction has had its branch target
469 * calculated yet. For now it is not utilized and is hacked to be
470 * always false.
471 * @todo: Actually use this instruction.
472 */
473 bool doneTargCalc() { return false; }
474
475 /** Set the predicted target of this current instruction. */
476 void setPredTarg(const TheISA::PCState &_predPC)
477 {
478 predPC = _predPC;
479 }
480
481 const TheISA::PCState &readPredTarg() { return predPC; }
482
483 /** Returns the predicted PC immediately after the branch. */
484 Addr predInstAddr() { return predPC.instAddr(); }
485
486 /** Returns the predicted PC two instructions after the branch */
487 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
488
489 /** Returns the predicted micro PC after the branch */
490 Addr predMicroPC() { return predPC.microPC(); }
491
492 /** Returns whether the instruction was predicted taken or not. */
493 bool readPredTaken()
494 {
495 return instFlags[PredTaken];
496 }
497
498 void setPredTaken(bool predicted_taken)
499 {
500 instFlags[PredTaken] = predicted_taken;
501 }
502
503 /** Returns whether the instruction mispredicted. */
504 bool mispredicted()
505 {
506 TheISA::PCState tempPC = pc;
507 TheISA::advancePC(tempPC, staticInst);
508 return !(tempPC == predPC);
509 }
510
511 //
512 // Instruction types. Forward checks to StaticInst object.
513 //
514 bool isNop() const { return staticInst->isNop(); }
515 bool isMemRef() const { return staticInst->isMemRef(); }
516 bool isLoad() const { return staticInst->isLoad(); }
517 bool isStore() const { return staticInst->isStore(); }
518 bool isStoreConditional() const
519 { return staticInst->isStoreConditional(); }
520 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
521 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
522 bool isInteger() const { return staticInst->isInteger(); }
523 bool isFloating() const { return staticInst->isFloating(); }
524 bool isControl() const { return staticInst->isControl(); }
525 bool isCall() const { return staticInst->isCall(); }
526 bool isReturn() const { return staticInst->isReturn(); }
527 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
528 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
529 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
530 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
531 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
532 bool isThreadSync() const { return staticInst->isThreadSync(); }
533 bool isSerializing() const { return staticInst->isSerializing(); }
534 bool isSerializeBefore() const
535 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
536 bool isSerializeAfter() const
537 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
538 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
539 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
540 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
541 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
542 bool isQuiesce() const { return staticInst->isQuiesce(); }
543 bool isIprAccess() const { return staticInst->isIprAccess(); }
544 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
545 bool isSyscall() const { return staticInst->isSyscall(); }
546 bool isMacroop() const { return staticInst->isMacroop(); }
547 bool isMicroop() const { return staticInst->isMicroop(); }
548 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
549 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
550 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
551 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
552
553 /** Temporarily sets this instruction as a serialize before instruction. */
554 void setSerializeBefore() { status.set(SerializeBefore); }
555
556 /** Clears the serializeBefore part of this instruction. */
557 void clearSerializeBefore() { status.reset(SerializeBefore); }
558
559 /** Checks if this serializeBefore is only temporarily set. */
560 bool isTempSerializeBefore() { return status[SerializeBefore]; }
561
562 /** Temporarily sets this instruction as a serialize after instruction. */
563 void setSerializeAfter() { status.set(SerializeAfter); }
564
565 /** Clears the serializeAfter part of this instruction.*/
566 void clearSerializeAfter() { status.reset(SerializeAfter); }
567
568 /** Checks if this serializeAfter is only temporarily set. */
569 bool isTempSerializeAfter() { return status[SerializeAfter]; }
570
571 /** Sets the serialization part of this instruction as handled. */
572 void setSerializeHandled() { status.set(SerializeHandled); }
573
574 /** Checks if the serialization part of this instruction has been
575 * handled. This does not apply to the temporary serializing
576 * state; it only applies to this instruction's own permanent
577 * serializing state.
578 */
579 bool isSerializeHandled() { return status[SerializeHandled]; }
580
581 /** Returns the opclass of this instruction. */
582 OpClass opClass() const { return staticInst->opClass(); }
583
584 /** Returns the branch target address. */
585 TheISA::PCState branchTarget() const
586 { return staticInst->branchTarget(pc); }
587
588 /** Returns the number of source registers. */
589 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
590
591 /** Returns the number of destination registers. */
592 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
593
594 // the following are used to track physical register usage
595 // for machines with separate int & FP reg files
596 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
597 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
598
599 /** Returns the logical register index of the i'th destination register. */
600 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
601
602 /** Returns the logical register index of the i'th source register. */
603 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
604
605 /** Pops a result off the instResult queue */
606 template <class T>
607 void popResult(T& t)
608 {
609 if (!instResult.empty()) {
610 instResult.front().get(t);
611 instResult.pop();
612 }
613 }
614
615 /** Read the most recent result stored by this instruction */
616 template <class T>
617 void readResult(T& t)
618 {
619 instResult.back().get(t);
620 }
621
622 /** Pushes a result onto the instResult queue */
623 template <class T>
624 void setResult(T t)
625 {
626 if (instFlags[RecordResult]) {
627 Result instRes;
628 instRes.set(t);
629 instResult.push(instRes);
630 }
631 }
632
633 /** Records an integer register being set to a value. */
634 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
635 {
636 setResult<uint64_t>(val);
637 }
638
639 /** Records a CC register being set to a value. */
640 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
641 {
642 setResult<uint64_t>(val);
643 }
644
645 /** Records an fp register being set to a value. */
646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
647 int width)
648 {
649 if (width == 32 || width == 64) {
650 setResult<double>(val);
651 } else {
652 panic("Unsupported width!");
653 }
654 }
655
656 /** Records an fp register being set to a value. */
657 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
658 {
659 setResult<double>(val);
660 }
661
662 /** Records an fp register being set to an integer value. */
663 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
664 int width)
665 {
666 setResult<uint64_t>(val);
667 }
668
669 /** Records an fp register being set to an integer value. */
670 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
671 {
672 setResult<uint64_t>(val);
673 }
674
675 /** Records that one of the source registers is ready. */
676 void markSrcRegReady();
677
678 /** Marks a specific register as ready. */
679 void markSrcRegReady(RegIndex src_idx);
680
681 /** Returns if a source register is ready. */
682 bool isReadySrcRegIdx(int idx) const
683 {
684 return this->_readySrcRegIdx[idx];
685 }
686
687 /** Sets this instruction as completed. */
688 void setCompleted() { status.set(Completed); }
689
690 /** Returns whether or not this instruction is completed. */
691 bool isCompleted() const { return status[Completed]; }
692
693 /** Marks the result as ready. */
694 void setResultReady() { status.set(ResultReady); }
695
696 /** Returns whether or not the result is ready. */
697 bool isResultReady() const { return status[ResultReady]; }
698
699 /** Sets this instruction as ready to issue. */
700 void setCanIssue() { status.set(CanIssue); }
701
702 /** Returns whether or not this instruction is ready to issue. */
703 bool readyToIssue() const { return status[CanIssue]; }
704
705 /** Clears this instruction being able to issue. */
706 void clearCanIssue() { status.reset(CanIssue); }
707
708 /** Sets this instruction as issued from the IQ. */
709 void setIssued() { status.set(Issued); }
710
711 /** Returns whether or not this instruction has issued. */
712 bool isIssued() const { return status[Issued]; }
713
714 /** Clears this instruction as being issued. */
715 void clearIssued() { status.reset(Issued); }
716
717 /** Sets this instruction as executed. */
718 void setExecuted() { status.set(Executed); }
719
720 /** Returns whether or not this instruction has executed. */
721 bool isExecuted() const { return status[Executed]; }
722
723 /** Sets this instruction as ready to commit. */
724 void setCanCommit() { status.set(CanCommit); }
725
726 /** Clears this instruction as being ready to commit. */
727 void clearCanCommit() { status.reset(CanCommit); }
728
729 /** Returns whether or not this instruction is ready to commit. */
730 bool readyToCommit() const { return status[CanCommit]; }
731
732 void setAtCommit() { status.set(AtCommit); }
733
734 bool isAtCommit() { return status[AtCommit]; }
735
736 /** Sets this instruction as committed. */
737 void setCommitted() { status.set(Committed); }
738
739 /** Returns whether or not this instruction is committed. */
740 bool isCommitted() const { return status[Committed]; }
741
742 /** Sets this instruction as squashed. */
743 void setSquashed() { status.set(Squashed); }
744
745 /** Returns whether or not this instruction is squashed. */
746 bool isSquashed() const { return status[Squashed]; }
747
748 //Instruction Queue Entry
749 //-----------------------
750 /** Sets this instruction as a entry the IQ. */
751 void setInIQ() { status.set(IqEntry); }
752
753 /** Sets this instruction as a entry the IQ. */
754 void clearInIQ() { status.reset(IqEntry); }
755
756 /** Returns whether or not this instruction has issued. */
757 bool isInIQ() const { return status[IqEntry]; }
758
759 /** Sets this instruction as squashed in the IQ. */
760 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
761
762 /** Returns whether or not this instruction is squashed in the IQ. */
763 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
764
765
766 //Load / Store Queue Functions
767 //-----------------------
768 /** Sets this instruction as a entry the LSQ. */
769 void setInLSQ() { status.set(LsqEntry); }
770
771 /** Sets this instruction as a entry the LSQ. */
772 void removeInLSQ() { status.reset(LsqEntry); }
773
774 /** Returns whether or not this instruction is in the LSQ. */
775 bool isInLSQ() const { return status[LsqEntry]; }
776
777 /** Sets this instruction as squashed in the LSQ. */
778 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
779
780 /** Returns whether or not this instruction is squashed in the LSQ. */
781 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
782
783
784 //Reorder Buffer Functions
785 //-----------------------
786 /** Sets this instruction as a entry the ROB. */
787 void setInROB() { status.set(RobEntry); }
788
789 /** Sets this instruction as a entry the ROB. */
790 void clearInROB() { status.reset(RobEntry); }
791
792 /** Returns whether or not this instruction is in the ROB. */
793 bool isInROB() const { return status[RobEntry]; }
794
795 /** Sets this instruction as squashed in the ROB. */
796 void setSquashedInROB() { status.set(SquashedInROB); }
797
798 /** Returns whether or not this instruction is squashed in the ROB. */
799 bool isSquashedInROB() const { return status[SquashedInROB]; }
800
801 /** Read the PC state of this instruction. */
802 const TheISA::PCState pcState() const { return pc; }
803
804 /** Set the PC state of this instruction. */
805 const void pcState(const TheISA::PCState &val) { pc = val; }
806
807 /** Read the PC of this instruction. */
808 const Addr instAddr() const { return pc.instAddr(); }
809
810 /** Read the PC of the next instruction. */
811 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
812
813 /**Read the micro PC of this instruction. */
814 const Addr microPC() const { return pc.microPC(); }
815
816 bool readPredicate()
817 {
818 return instFlags[Predicate];
819 }
820
821 void setPredicate(bool val)
822 {
823 instFlags[Predicate] = val;
824
825 if (traceData) {
826 traceData->setPredicate(val);
827 }
828 }
829
830 /** Sets the ASID. */
831 void setASID(short addr_space_id) { asid = addr_space_id; }
832
833 /** Sets the thread id. */
834 void setTid(ThreadID tid) { threadNumber = tid; }
835
836 /** Sets the pointer to the thread state. */
837 void setThreadState(ImplState *state) { thread = state; }
838
839 /** Returns the thread context. */
840 ThreadContext *tcBase() { return thread->getTC(); }
841
842 public:
843 /** Sets the effective address. */
844 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
845
846 /** Returns the effective address. */
847 const Addr &getEA() const { return instEffAddr; }
848
849 /** Returns whether or not the eff. addr. calculation has been completed. */
850 bool doneEACalc() { return instFlags[EACalcDone]; }
851
852 /** Returns whether or not the eff. addr. source registers are ready. */
853 bool eaSrcsReady();
854
855 /** Is this instruction's memory access uncacheable. */
856 bool uncacheable() { return instFlags[IsUncacheable]; }
857
858 /** Has this instruction generated a memory request. */
859 bool hasRequest() { return instFlags[ReqMade]; }
860
861 /** Returns iterator to this instruction in the list of all insts. */
862 ListIt &getInstListIt() { return instListIt; }
863
864 /** Sets iterator for this instruction in the list of all insts. */
865 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
866
867 public:
868 /** Returns the number of consecutive store conditional failures. */
869 unsigned readStCondFailures()
870 { return thread->storeCondFailures; }
871
872 /** Sets the number of consecutive store conditional failures. */
873 void setStCondFailures(unsigned sc_failures)
874 { thread->storeCondFailures = sc_failures; }
875};
876
877template<class Impl>
878Fault
879BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
880 unsigned size, unsigned flags)
881{
882 instFlags[ReqMade] = true;
883 Request *req = NULL;
884 Request *sreqLow = NULL;
885 Request *sreqHigh = NULL;
886
887 if (instFlags[ReqMade] && translationStarted()) {
888 req = savedReq;
889 sreqLow = savedSreqLow;
890 sreqHigh = savedSreqHigh;
891 } else {
892 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
893 thread->contextId(), threadNumber);
894
895 req->taskId(cpu->taskId());
896
897 // Only split the request if the ISA supports unaligned accesses.
898 if (TheISA::HasUnalignedMemAcc) {
899 splitRequest(req, sreqLow, sreqHigh);
900 }
901 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
902 }
903
904 if (translationCompleted()) {
905 if (fault == NoFault) {
906 effAddr = req->getVaddr();
907 effSize = size;
908 instFlags[EffAddrValid] = true;
909
910 if (cpu->checker) {
911 if (reqToVerify != NULL) {
912 delete reqToVerify;
913 }
914 reqToVerify = new Request(*req);
915 }
916 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
917 } else {
918 // Commit will have to clean up whatever happened. Set this
919 // instruction as executed.
920 this->setExecuted();
921 }
922
923 if (fault != NoFault) {
924 // Return a fixed value to keep simulation deterministic even
925 // along misspeculated paths.
926 if (data)
927 bzero(data, size);
928 }
929 }
930
931 if (traceData) {
932 traceData->setAddr(addr);
933 }
934
935 return fault;
936}
937
938template<class Impl>
939Fault
940BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
941 Addr addr, unsigned flags, uint64_t *res)
942{
943 if (traceData) {
944 traceData->setAddr(addr);
945 }
946
947 instFlags[ReqMade] = true;
948 Request *req = NULL;
949 Request *sreqLow = NULL;
950 Request *sreqHigh = NULL;
951
952 if (instFlags[ReqMade] && translationStarted()) {
953 req = savedReq;
954 sreqLow = savedSreqLow;
955 sreqHigh = savedSreqHigh;
956 } else {
957 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
958 thread->contextId(), threadNumber);
959
960 req->taskId(cpu->taskId());
961
962 // Only split the request if the ISA supports unaligned accesses.
963 if (TheISA::HasUnalignedMemAcc) {
964 splitRequest(req, sreqLow, sreqHigh);
965 }
966 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
967 }
968
969 if (fault == NoFault && translationCompleted()) {
970 effAddr = req->getVaddr();
971 effSize = size;
972 instFlags[EffAddrValid] = true;
973
974 if (cpu->checker) {
975 if (reqToVerify != NULL) {
976 delete reqToVerify;
977 }
978 reqToVerify = new Request(*req);
979 }
980 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
981 }
982
983 return fault;
984}
985
986template<class Impl>
987inline void
988BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
989 RequestPtr &sreqHigh)
990{
991 // Check to see if the request crosses the next level block boundary.
992 unsigned block_size = cpu->cacheLineSize();
993 Addr addr = req->getVaddr();
994 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
995 assert(split_addr <= addr || split_addr - addr < block_size);
996
997 // Spans two blocks.
998 if (split_addr > addr) {
999 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1000 }
1001}
1002
1003template<class Impl>
1004inline void
1005BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1006 RequestPtr sreqHigh, uint64_t *res,
1007 BaseTLB::Mode mode)
1008{
1009 translationStarted(true);
1010
1011 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, NULL, res, mode);
1014
1015 // One translation if the request isn't split.
1016 DataTranslation<BaseDynInstPtr> *trans =
1017 new DataTranslation<BaseDynInstPtr>(this, state);
1018
1019 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1020
1021 if (!translationCompleted()) {
1022 // The translation isn't yet complete, so we can't possibly have a
1023 // fault. Overwrite any existing fault we might have from a previous
1024 // execution of this instruction (e.g. an uncachable load that
1025 // couldn't execute because it wasn't at the head of the ROB).
1026 fault = NoFault;
1027
1028 // Save memory requests.
1029 savedReq = state->mainReq;
1030 savedSreqLow = state->sreqLow;
1031 savedSreqHigh = state->sreqHigh;
1032 }
1033 } else {
1034 WholeTranslationState *state =
1035 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1036
1037 // Two translations when the request is split.
1038 DataTranslation<BaseDynInstPtr> *stransLow =
1039 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1040 DataTranslation<BaseDynInstPtr> *stransHigh =
1041 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1042
1043 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1044 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1045
1046 if (!translationCompleted()) {
1047 // The translation isn't yet complete, so we can't possibly have a
1048 // fault. Overwrite any existing fault we might have from a previous
1049 // execution of this instruction (e.g. an uncachable load that
1050 // couldn't execute because it wasn't at the head of the ROB).
1051 fault = NoFault;
1052
1053 // Save memory requests.
1054 savedReq = state->mainReq;
1055 savedSreqLow = state->sreqLow;
1056 savedSreqHigh = state->sreqHigh;
1057 }
1058 }
1059}
1060
1061template<class Impl>
1062inline void
1063BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1064{
1065 fault = state->getFault();
1066
1067 instFlags[IsUncacheable] = state->isUncacheable();
1068
1069 if (fault == NoFault) {
1070 physEffAddr = state->getPaddr();
1071 memReqFlags = state->getFlags();
1072
1073 if (state->mainReq->isCondSwap()) {
1074 assert(state->res);
1075 state->mainReq->setExtraData(*state->res);
1076 }
1077
1078 } else {
1079 state->deleteReqs();
1080 }
1081 delete state;
1082
1083 translationCompleted(true);
1084}
1085
1086#endif // __CPU_BASE_DYN_INST_HH__
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