base_dyn_inst.hh (6221:58a3c04e6344) | base_dyn_inst.hh (6429:7ed8937e375a) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 843 unchanged lines hidden (view full) --- 852}; 853 854template<class Impl> 855template<class T> 856inline Fault 857BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 858{ 859 reqMade = true; | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 843 unchanged lines hidden (view full) --- 852}; 853 854template<class Impl> 855template<class T> 856inline Fault 857BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags) 858{ 859 reqMade = true; |
860 Request *req = new Request(); 861 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 862 req->setThreadContext(thread->contextId(), threadNumber); | 860 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, 861 thread->contextId(), threadNumber); |
863 864 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); 865 866 if (req->isUncacheable()) 867 isUncacheable = true; 868 869 if (fault == NoFault) { 870 effAddr = req->getVaddr(); --- 37 unchanged lines hidden (view full) --- 908BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 909{ 910 if (traceData) { 911 traceData->setAddr(addr); 912 traceData->setData(data); 913 } 914 915 reqMade = true; | 862 863 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read); 864 865 if (req->isUncacheable()) 866 isUncacheable = true; 867 868 if (fault == NoFault) { 869 effAddr = req->getVaddr(); --- 37 unchanged lines hidden (view full) --- 907BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res) 908{ 909 if (traceData) { 910 traceData->setAddr(addr); 911 traceData->setData(data); 912 } 913 914 reqMade = true; |
916 Request *req = new Request(); 917 req->setVirt(asid, addr, sizeof(T), flags, this->PC); 918 req->setThreadContext(thread->contextId(), threadNumber); | 915 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC, 916 thread->contextId(), threadNumber); |
919 920 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 921 922 if (req->isUncacheable()) 923 isUncacheable = true; 924 925 if (fault == NoFault) { 926 effAddr = req->getVaddr(); --- 25 unchanged lines hidden --- | 917 918 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write); 919 920 if (req->isUncacheable()) 921 isUncacheable = true; 922 923 if (fault == NoFault) { 924 effAddr = req->getVaddr(); --- 25 unchanged lines hidden --- |