base_dyn_inst.hh (12110:c24ee249b8ba) | base_dyn_inst.hh (12420:f5c80f4ed41f) |
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1/* 2 * Copyright (c) 2011,2013,2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 118 unchanged lines hidden (view full) --- 127 TranslationStarted, 128 TranslationCompleted, 129 PossibleLoadViolation, 130 HitExternalSnoop, 131 EffAddrValid, 132 RecordResult, 133 Predicate, 134 PredTaken, | 1/* 2 * Copyright (c) 2011,2013,2016 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 118 unchanged lines hidden (view full) --- 127 TranslationStarted, 128 TranslationCompleted, 129 PossibleLoadViolation, 130 HitExternalSnoop, 131 EffAddrValid, 132 RecordResult, 133 Predicate, 134 PredTaken, |
135 /** Whether or not the effective address calculation is completed. 136 * @todo: Consider if this is necessary or not. 137 */ 138 EACalcDone, | |
139 IsStrictlyOrdered, 140 ReqMade, 141 MemOpDone, 142 MaxFlags 143 }; 144 145 public: 146 /** The sequence number of the instruction. */ --- 93 unchanged lines hidden (view full) --- 240 RequestPtr savedReq; 241 RequestPtr savedSreqLow; 242 RequestPtr savedSreqHigh; 243 244 /////////////////////// Checker ////////////////////// 245 // Need a copy of main request pointer to verify on writes. 246 RequestPtr reqToVerify; 247 | 135 IsStrictlyOrdered, 136 ReqMade, 137 MemOpDone, 138 MaxFlags 139 }; 140 141 public: 142 /** The sequence number of the instruction. */ --- 93 unchanged lines hidden (view full) --- 236 RequestPtr savedReq; 237 RequestPtr savedSreqLow; 238 RequestPtr savedSreqHigh; 239 240 /////////////////////// Checker ////////////////////// 241 // Need a copy of main request pointer to verify on writes. 242 RequestPtr reqToVerify; 243 |
248 private: 249 /** Instruction effective address. 250 * @todo: Consider if this is necessary or not. 251 */ 252 Addr instEffAddr; 253 | |
254 protected: 255 /** Flattened register index of the destination registers of this 256 * instruction. 257 */ 258 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 259 260 /** Physical register index of the destination registers of this 261 * instruction. --- 592 unchanged lines hidden (view full) --- 854 855 /** Sets the pointer to the thread state. */ 856 void setThreadState(ImplState *state) { thread = state; } 857 858 /** Returns the thread context. */ 859 ThreadContext *tcBase() { return thread->getTC(); } 860 861 public: | 244 protected: 245 /** Flattened register index of the destination registers of this 246 * instruction. 247 */ 248 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx; 249 250 /** Physical register index of the destination registers of this 251 * instruction. --- 592 unchanged lines hidden (view full) --- 844 845 /** Sets the pointer to the thread state. */ 846 void setThreadState(ImplState *state) { thread = state; } 847 848 /** Returns the thread context. */ 849 ThreadContext *tcBase() { return thread->getTC(); } 850 851 public: |
862 /** Sets the effective address. */ 863 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; } 864 865 /** Returns the effective address. */ 866 Addr getEA() const { return instEffAddr; } 867 868 /** Returns whether or not the eff. addr. calculation has been completed. */ 869 bool doneEACalc() { return instFlags[EACalcDone]; } 870 | |
871 /** Returns whether or not the eff. addr. source registers are ready. */ 872 bool eaSrcsReady(); 873 874 /** Is this instruction's memory access strictly ordered? */ 875 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 876 877 /** Has this instruction generated a memory request. */ 878 bool hasRequest() { return instFlags[ReqMade]; } --- 235 unchanged lines hidden --- | 852 /** Returns whether or not the eff. addr. source registers are ready. */ 853 bool eaSrcsReady(); 854 855 /** Is this instruction's memory access strictly ordered? */ 856 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; } 857 858 /** Has this instruction generated a memory request. */ 859 bool hasRequest() { return instFlags[ReqMade]; } --- 235 unchanged lines hidden --- |