1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Timothy M. Jones
43 */
44
45#ifndef __CPU_BASE_DYN_INST_HH__
46#define __CPU_BASE_DYN_INST_HH__
47
48#include <bitset>
49#include <list>
50#include <string>
51
52#include "arch/faults.hh"
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/full_system.hh"
57#include "config/the_isa.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/system.hh"
67#include "sim/tlb.hh"
68
69/**
70 * @file
71 * Defines a dynamic instruction context.
72 */
73
74// Forward declaration.
75class StaticInstPtr;
76
77template <class Impl>
78class BaseDynInst : public FastAlloc, public RefCounted
79{
80 public:
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
91
92 // The DynInstPtr type.
93 typedef typename Impl::DynInstPtr DynInstPtr;
94
95 // The list of instructions iterator type.
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
97
98 enum {
99 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
100 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
101 };
102
103 /** The StaticInst used by this BaseDynInst. */
104 StaticInstPtr staticInst;
105
106 ////////////////////////////////////////////
107 //
108 // INSTRUCTION EXECUTION
109 //
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
113
114 void demapPage(Addr vaddr, uint64_t asn)
115 {
116 cpu->demapPage(vaddr, asn);
117 }
118 void demapInstPage(Addr vaddr, uint64_t asn)
119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 /**
128 * Does a read to a given address.
129 * @param addr The address to read.
130 * @param data The read's data is written into this parameter.
131 * @param flags The request's flags.
132 * @return Returns any fault due to the read.
133 */
134 template <class T>
135 Fault read(Addr addr, T &data, unsigned flags);
136
137 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
138
139 /**
140 * Does a write to a given address.
141 * @param data The data to be written.
142 * @param addr The address to write to.
143 * @param flags The request's flags.
144 * @param res The result of the write (for load locked/store conditionals).
145 * @return Returns any fault due to the write.
146 */
147 template <class T>
148 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
149
150 Fault writeBytes(uint8_t *data, unsigned size,
151 Addr addr, unsigned flags, uint64_t *res);
152
153 /** Splits a request in two if it crosses a dcache block. */
154 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
155 RequestPtr &sreqHigh);
156
157 /** Initiate a DTB address translation. */
158 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
159 RequestPtr sreqHigh, uint64_t *res,
160 BaseTLB::Mode mode);
161
162 /** Finish a DTB address translation. */
163 void finishTranslation(WholeTranslationState *state);
164
165 /** True if the DTB address translation has started. */
166 bool translationStarted;
167
168 /** True if the DTB address translation has completed. */
169 bool translationCompleted;
170
171 /**
172 * Returns true if the DTB address translation is being delayed due to a hw
173 * page table walk.
174 */
175 bool isTranslationDelayed() const
176 {
177 return (translationStarted && !translationCompleted);
178 }
179
180 /**
181 * Saved memory requests (needed when the DTB address translation is
182 * delayed due to a hw page table walk).
183 */
184 RequestPtr savedReq;
185 RequestPtr savedSreqLow;
186 RequestPtr savedSreqHigh;
187
188 /** @todo: Consider making this private. */
189 public:
190 /** The sequence number of the instruction. */
191 InstSeqNum seqNum;
192
193 enum Status {
194 IqEntry, /// Instruction is in the IQ
195 RobEntry, /// Instruction is in the ROB
196 LsqEntry, /// Instruction is in the LSQ
197 Completed, /// Instruction has completed
198 ResultReady, /// Instruction has its result
199 CanIssue, /// Instruction can issue and execute
200 Issued, /// Instruction has issued
201 Executed, /// Instruction has executed
202 CanCommit, /// Instruction can commit
203 AtCommit, /// Instruction has reached commit
204 Committed, /// Instruction has committed
205 Squashed, /// Instruction is squashed
206 SquashedInIQ, /// Instruction is squashed in the IQ
207 SquashedInLSQ, /// Instruction is squashed in the LSQ
208 SquashedInROB, /// Instruction is squashed in the ROB
209 RecoverInst, /// Is a recover instruction
210 BlockingInst, /// Is a blocking instruction
211 ThreadsyncWait, /// Is a thread synchronization instruction
212 SerializeBefore, /// Needs to serialize on
213 /// instructions ahead of it
214 SerializeAfter, /// Needs to serialize instructions behind it
215 SerializeHandled, /// Serialization has been handled
216 NumStatus
217 };
218
219 /** The status of this BaseDynInst. Several bits can be set. */
220 std::bitset<NumStatus> status;
221
222 /** The thread this instruction is from. */
223 ThreadID threadNumber;
224
225 /** data address space ID, for loads & stores. */
226 short asid;
227
228 /** How many source registers are ready. */
229 unsigned readyRegs;
230
231 /** Pointer to the Impl's CPU object. */
232 ImplCPU *cpu;
233
234 /** Pointer to the thread state. */
235 ImplState *thread;
236
237 /** The kind of fault this instruction has generated. */
238 Fault fault;
239
240 /** Pointer to the data for the memory access. */
241 uint8_t *memData;
242
243 /** The effective virtual address (lds & stores only). */
244 Addr effAddr;
245
246 /** The size of the request */
247 Addr effSize;
248
249 /** Is the effective virtual address valid. */
250 bool effAddrValid;
251
252 /** The effective physical address. */
253 Addr physEffAddr;
254
255 /** The memory request flags (from translation). */
256 unsigned memReqFlags;
257
258 union Result {
259 uint64_t integer;
260// float fp;
261 double dbl;
262 };
263
264 /** The result of the instruction; assumes for now that there's only one
265 * destination register.
266 */
267 Result instResult;
268
269 /** Records changes to result? */
270 bool recordResult;
271
272 /** Did this instruction execute, or is it predicated false */
273 bool predicate;
274
275 protected:
276 /** PC state for this instruction. */
277 TheISA::PCState pc;
278
279 /** Predicted PC state after this instruction. */
280 TheISA::PCState predPC;
281
282 /** If this is a branch that was predicted taken */
283 bool predTaken;
284
285 public:
286
287#ifdef DEBUG
288 void dumpSNList();
289#endif
290
291 /** Whether or not the source register is ready.
292 * @todo: Not sure this should be here vs the derived class.
293 */
294 bool _readySrcRegIdx[MaxInstSrcRegs];
295
296 protected:
297 /** Flattened register index of the destination registers of this
298 * instruction.
299 */
300 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
301
302 /** Flattened register index of the source registers of this
303 * instruction.
304 */
305 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
306
307 /** Physical register index of the destination registers of this
308 * instruction.
309 */
310 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
311
312 /** Physical register index of the source registers of this
313 * instruction.
314 */
315 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
316
317 /** Physical register index of the previous producers of the
318 * architected destinations.
319 */
320 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
321
322 public:
323
324 /** Returns the physical register index of the i'th destination
325 * register.
326 */
327 PhysRegIndex renamedDestRegIdx(int idx) const
328 {
329 return _destRegIdx[idx];
330 }
331
332 /** Returns the physical register index of the i'th source register. */
333 PhysRegIndex renamedSrcRegIdx(int idx) const
334 {
335 return _srcRegIdx[idx];
336 }
337
338 /** Returns the flattened register index of the i'th destination
339 * register.
340 */
341 TheISA::RegIndex flattenedDestRegIdx(int idx) const
342 {
343 return _flatDestRegIdx[idx];
344 }
345
346 /** Returns the flattened register index of the i'th source register */
347 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
348 {
349 return _flatSrcRegIdx[idx];
350 }
351
352 /** Returns the physical register index of the previous physical register
353 * that remapped to the same logical register index.
354 */
355 PhysRegIndex prevDestRegIdx(int idx) const
356 {
357 return _prevDestRegIdx[idx];
358 }
359
360 /** Renames a destination register to a physical register. Also records
361 * the previous physical register that the logical register mapped to.
362 */
363 void renameDestReg(int idx,
364 PhysRegIndex renamed_dest,
365 PhysRegIndex previous_rename)
366 {
367 _destRegIdx[idx] = renamed_dest;
368 _prevDestRegIdx[idx] = previous_rename;
369 }
370
371 /** Renames a source logical register to the physical register which
372 * has/will produce that logical register's result.
373 * @todo: add in whether or not the source register is ready.
374 */
375 void renameSrcReg(int idx, PhysRegIndex renamed_src)
376 {
377 _srcRegIdx[idx] = renamed_src;
378 }
379
380 /** Flattens a source architectural register index into a logical index.
381 */
382 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
383 {
384 _flatSrcRegIdx[idx] = flattened_src;
385 }
386
387 /** Flattens a destination architectural register index into a logical
388 * index.
389 */
390 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
391 {
392 _flatDestRegIdx[idx] = flattened_dest;
393 }
394 /** BaseDynInst constructor given a binary instruction.
395 * @param staticInst A StaticInstPtr to the underlying instruction.
396 * @param pc The PC state for the instruction.
397 * @param predPC The predicted next PC state for the instruction.
398 * @param seq_num The sequence number of the instruction.
399 * @param cpu Pointer to the instruction's CPU.
400 */
401 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
402 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
403
404 /** BaseDynInst constructor given a binary instruction.
405 * @param inst The binary instruction.
406 * @param _pc The PC state for the instruction.
407 * @param _predPC The predicted next PC state for the instruction.
408 * @param seq_num The sequence number of the instruction.
409 * @param cpu Pointer to the instruction's CPU.
410 */
411 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
412 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
413
414 /** BaseDynInst constructor given a StaticInst pointer.
415 * @param _staticInst The StaticInst for this BaseDynInst.
416 */
417 BaseDynInst(StaticInstPtr &_staticInst);
418
419 /** BaseDynInst destructor. */
420 ~BaseDynInst();
421
422 private:
423 /** Function to initialize variables in the constructors. */
424 void initVars();
425
426 public:
427 /** Dumps out contents of this BaseDynInst. */
428 void dump();
429
430 /** Dumps out contents of this BaseDynInst into given string. */
431 void dump(std::string &outstring);
432
433 /** Read this CPU's ID. */
434 int cpuId() { return cpu->cpuId(); }
435
436 /** Read this context's system-wide ID **/
437 int contextId() { return thread->contextId(); }
438
439 /** Returns the fault type. */
440 Fault getFault() { return fault; }
441
442 /** Checks whether or not this instruction has had its branch target
443 * calculated yet. For now it is not utilized and is hacked to be
444 * always false.
445 * @todo: Actually use this instruction.
446 */
447 bool doneTargCalc() { return false; }
448
449 /** Set the predicted target of this current instruction. */
450 void setPredTarg(const TheISA::PCState &_predPC)
451 {
452 predPC = _predPC;
453 }
454
455 const TheISA::PCState &readPredTarg() { return predPC; }
456
457 /** Returns the predicted PC immediately after the branch. */
458 Addr predInstAddr() { return predPC.instAddr(); }
459
460 /** Returns the predicted PC two instructions after the branch */
461 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
462
463 /** Returns the predicted micro PC after the branch */
464 Addr predMicroPC() { return predPC.microPC(); }
465
466 /** Returns whether the instruction was predicted taken or not. */
467 bool readPredTaken()
468 {
469 return predTaken;
470 }
471
472 void setPredTaken(bool predicted_taken)
473 {
474 predTaken = predicted_taken;
475 }
476
477 /** Returns whether the instruction mispredicted. */
478 bool mispredicted()
479 {
480 TheISA::PCState tempPC = pc;
481 TheISA::advancePC(tempPC, staticInst);
482 return !(tempPC == predPC);
483 }
484
485 //
486 // Instruction types. Forward checks to StaticInst object.
487 //
488 bool isNop() const { return staticInst->isNop(); }
489 bool isMemRef() const { return staticInst->isMemRef(); }
490 bool isLoad() const { return staticInst->isLoad(); }
491 bool isStore() const { return staticInst->isStore(); }
492 bool isStoreConditional() const
493 { return staticInst->isStoreConditional(); }
494 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
495 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
496 bool isInteger() const { return staticInst->isInteger(); }
497 bool isFloating() const { return staticInst->isFloating(); }
498 bool isControl() const { return staticInst->isControl(); }
499 bool isCall() const { return staticInst->isCall(); }
500 bool isReturn() const { return staticInst->isReturn(); }
501 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
502 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
503 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
504 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
505 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
506 bool isThreadSync() const { return staticInst->isThreadSync(); }
507 bool isSerializing() const { return staticInst->isSerializing(); }
508 bool isSerializeBefore() const
509 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
510 bool isSerializeAfter() const
511 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
512 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
513 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
514 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
515 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
516 bool isQuiesce() const { return staticInst->isQuiesce(); }
517 bool isIprAccess() const { return staticInst->isIprAccess(); }
518 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
519 bool isSyscall() const { return staticInst->isSyscall(); }
520 bool isMacroop() const { return staticInst->isMacroop(); }
521 bool isMicroop() const { return staticInst->isMicroop(); }
522 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
523 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
524 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
525 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
526
527 /** Temporarily sets this instruction as a serialize before instruction. */
528 void setSerializeBefore() { status.set(SerializeBefore); }
529
530 /** Clears the serializeBefore part of this instruction. */
531 void clearSerializeBefore() { status.reset(SerializeBefore); }
532
533 /** Checks if this serializeBefore is only temporarily set. */
534 bool isTempSerializeBefore() { return status[SerializeBefore]; }
535
536 /** Temporarily sets this instruction as a serialize after instruction. */
537 void setSerializeAfter() { status.set(SerializeAfter); }
538
539 /** Clears the serializeAfter part of this instruction.*/
540 void clearSerializeAfter() { status.reset(SerializeAfter); }
541
542 /** Checks if this serializeAfter is only temporarily set. */
543 bool isTempSerializeAfter() { return status[SerializeAfter]; }
544
545 /** Sets the serialization part of this instruction as handled. */
546 void setSerializeHandled() { status.set(SerializeHandled); }
547
548 /** Checks if the serialization part of this instruction has been
549 * handled. This does not apply to the temporary serializing
550 * state; it only applies to this instruction's own permanent
551 * serializing state.
552 */
553 bool isSerializeHandled() { return status[SerializeHandled]; }
554
555 /** Returns the opclass of this instruction. */
556 OpClass opClass() const { return staticInst->opClass(); }
557
558 /** Returns the branch target address. */
559 TheISA::PCState branchTarget() const
560 { return staticInst->branchTarget(pc); }
561
562 /** Returns the number of source registers. */
563 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
564
565 /** Returns the number of destination registers. */
566 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
567
568 // the following are used to track physical register usage
569 // for machines with separate int & FP reg files
570 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
571 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
572
573 /** Returns the logical register index of the i'th destination register. */
574 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
575
576 /** Returns the logical register index of the i'th source register. */
577 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
578
579 /** Returns the result of an integer instruction. */
580 uint64_t readIntResult() { return instResult.integer; }
581
582 /** Returns the result of a floating point instruction. */
583 float readFloatResult() { return (float)instResult.dbl; }
584
585 /** Returns the result of a floating point (double) instruction. */
586 double readDoubleResult() { return instResult.dbl; }
587
588 /** Records an integer register being set to a value. */
589 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
590 {
591 if (recordResult)
592 instResult.integer = val;
593 }
594
595 /** Records an fp register being set to a value. */
596 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
597 int width)
598 {
599 if (recordResult) {
600 if (width == 32)
601 instResult.dbl = (double)val;
602 else if (width == 64)
603 instResult.dbl = val;
604 else
605 panic("Unsupported width!");
606 }
607 }
608
609 /** Records an fp register being set to a value. */
610 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
611 {
612 if (recordResult)
613 instResult.dbl = (double)val;
614 }
615
616 /** Records an fp register being set to an integer value. */
617 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
618 int width)
619 {
620 if (recordResult)
621 instResult.integer = val;
622 }
623
624 /** Records an fp register being set to an integer value. */
625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
626 {
627 if (recordResult)
628 instResult.integer = val;
629 }
630
631 /** Records that one of the source registers is ready. */
632 void markSrcRegReady();
633
634 /** Marks a specific register as ready. */
635 void markSrcRegReady(RegIndex src_idx);
636
637 /** Returns if a source register is ready. */
638 bool isReadySrcRegIdx(int idx) const
639 {
640 return this->_readySrcRegIdx[idx];
641 }
642
643 /** Sets this instruction as completed. */
644 void setCompleted() { status.set(Completed); }
645
646 /** Returns whether or not this instruction is completed. */
647 bool isCompleted() const { return status[Completed]; }
648
649 /** Marks the result as ready. */
650 void setResultReady() { status.set(ResultReady); }
651
652 /** Returns whether or not the result is ready. */
653 bool isResultReady() const { return status[ResultReady]; }
654
655 /** Sets this instruction as ready to issue. */
656 void setCanIssue() { status.set(CanIssue); }
657
658 /** Returns whether or not this instruction is ready to issue. */
659 bool readyToIssue() const { return status[CanIssue]; }
660
661 /** Clears this instruction being able to issue. */
662 void clearCanIssue() { status.reset(CanIssue); }
663
664 /** Sets this instruction as issued from the IQ. */
665 void setIssued() { status.set(Issued); }
666
667 /** Returns whether or not this instruction has issued. */
668 bool isIssued() const { return status[Issued]; }
669
670 /** Clears this instruction as being issued. */
671 void clearIssued() { status.reset(Issued); }
672
673 /** Sets this instruction as executed. */
674 void setExecuted() { status.set(Executed); }
675
676 /** Returns whether or not this instruction has executed. */
677 bool isExecuted() const { return status[Executed]; }
678
679 /** Sets this instruction as ready to commit. */
680 void setCanCommit() { status.set(CanCommit); }
681
682 /** Clears this instruction as being ready to commit. */
683 void clearCanCommit() { status.reset(CanCommit); }
684
685 /** Returns whether or not this instruction is ready to commit. */
686 bool readyToCommit() const { return status[CanCommit]; }
687
688 void setAtCommit() { status.set(AtCommit); }
689
690 bool isAtCommit() { return status[AtCommit]; }
691
692 /** Sets this instruction as committed. */
693 void setCommitted() { status.set(Committed); }
694
695 /** Returns whether or not this instruction is committed. */
696 bool isCommitted() const { return status[Committed]; }
697
698 /** Sets this instruction as squashed. */
699 void setSquashed() { status.set(Squashed); }
700
701 /** Returns whether or not this instruction is squashed. */
702 bool isSquashed() const { return status[Squashed]; }
703
704 //Instruction Queue Entry
705 //-----------------------
706 /** Sets this instruction as a entry the IQ. */
707 void setInIQ() { status.set(IqEntry); }
708
709 /** Sets this instruction as a entry the IQ. */
710 void clearInIQ() { status.reset(IqEntry); }
711
712 /** Returns whether or not this instruction has issued. */
713 bool isInIQ() const { return status[IqEntry]; }
714
715 /** Sets this instruction as squashed in the IQ. */
716 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
717
718 /** Returns whether or not this instruction is squashed in the IQ. */
719 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
720
721
722 //Load / Store Queue Functions
723 //-----------------------
724 /** Sets this instruction as a entry the LSQ. */
725 void setInLSQ() { status.set(LsqEntry); }
726
727 /** Sets this instruction as a entry the LSQ. */
728 void removeInLSQ() { status.reset(LsqEntry); }
729
730 /** Returns whether or not this instruction is in the LSQ. */
731 bool isInLSQ() const { return status[LsqEntry]; }
732
733 /** Sets this instruction as squashed in the LSQ. */
734 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
735
736 /** Returns whether or not this instruction is squashed in the LSQ. */
737 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
738
739
740 //Reorder Buffer Functions
741 //-----------------------
742 /** Sets this instruction as a entry the ROB. */
743 void setInROB() { status.set(RobEntry); }
744
745 /** Sets this instruction as a entry the ROB. */
746 void clearInROB() { status.reset(RobEntry); }
747
748 /** Returns whether or not this instruction is in the ROB. */
749 bool isInROB() const { return status[RobEntry]; }
750
751 /** Sets this instruction as squashed in the ROB. */
752 void setSquashedInROB() { status.set(SquashedInROB); }
753
754 /** Returns whether or not this instruction is squashed in the ROB. */
755 bool isSquashedInROB() const { return status[SquashedInROB]; }
756
757 /** Read the PC state of this instruction. */
758 const TheISA::PCState pcState() const { return pc; }
759
760 /** Set the PC state of this instruction. */
761 const void pcState(const TheISA::PCState &val) { pc = val; }
762
763 /** Read the PC of this instruction. */
764 const Addr instAddr() const { return pc.instAddr(); }
765
766 /** Read the PC of the next instruction. */
767 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
768
769 /**Read the micro PC of this instruction. */
770 const Addr microPC() const { return pc.microPC(); }
771
772 bool readPredicate()
773 {
774 return predicate;
775 }
776
777 void setPredicate(bool val)
778 {
779 predicate = val;
780
781 if (traceData) {
782 traceData->setPredicate(val);
783 }
784 }
785
786 /** Sets the ASID. */
787 void setASID(short addr_space_id) { asid = addr_space_id; }
788
789 /** Sets the thread id. */
790 void setTid(ThreadID tid) { threadNumber = tid; }
791
792 /** Sets the pointer to the thread state. */
793 void setThreadState(ImplState *state) { thread = state; }
794
795 /** Returns the thread context. */
796 ThreadContext *tcBase() { return thread->getTC(); }
797
798 private:
799 /** Instruction effective address.
800 * @todo: Consider if this is necessary or not.
801 */
802 Addr instEffAddr;
803
804 /** Whether or not the effective address calculation is completed.
805 * @todo: Consider if this is necessary or not.
806 */
807 bool eaCalcDone;
808
809 /** Is this instruction's memory access uncacheable. */
810 bool isUncacheable;
811
812 /** Has this instruction generated a memory request. */
813 bool reqMade;
814
815 public:
816 /** Sets the effective address. */
817 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
818
819 /** Returns the effective address. */
820 const Addr &getEA() const { return instEffAddr; }
821
822 /** Returns whether or not the eff. addr. calculation has been completed. */
823 bool doneEACalc() { return eaCalcDone; }
824
825 /** Returns whether or not the eff. addr. source registers are ready. */
826 bool eaSrcsReady();
827
828 /** Whether or not the memory operation is done. */
829 bool memOpDone;
830
831 /** Is this instruction's memory access uncacheable. */
832 bool uncacheable() { return isUncacheable; }
833
834 /** Has this instruction generated a memory request. */
835 bool hasRequest() { return reqMade; }
836
837 public:
838 /** Load queue index. */
839 int16_t lqIdx;
840
841 /** Store queue index. */
842 int16_t sqIdx;
843
844 /** Iterator pointing to this BaseDynInst in the list of all insts. */
845 ListIt instListIt;
846
847 /** Returns iterator to this instruction in the list of all insts. */
848 ListIt &getInstListIt() { return instListIt; }
849
850 /** Sets iterator for this instruction in the list of all insts. */
851 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
852
853 public:
854 /** Returns the number of consecutive store conditional failures. */
855 unsigned readStCondFailures()
856 { return thread->storeCondFailures; }
857
858 /** Sets the number of consecutive store conditional failures. */
859 void setStCondFailures(unsigned sc_failures)
860 { thread->storeCondFailures = sc_failures; }
861};
862
863template<class Impl>
864Fault
865BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
866 unsigned size, unsigned flags)
867{
868 reqMade = true;
869 Request *req = NULL;
870 Request *sreqLow = NULL;
871 Request *sreqHigh = NULL;
872
873 if (reqMade && translationStarted) {
874 req = savedReq;
875 sreqLow = savedSreqLow;
876 sreqHigh = savedSreqHigh;
877 } else {
878 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
879 thread->contextId(), threadNumber);
880
881 // Only split the request if the ISA supports unaligned accesses.
882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
884 }
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886 }
887
888 if (translationCompleted) {
889 if (fault == NoFault) {
890 effAddr = req->getVaddr();
891 effSize = size;
892 effAddrValid = true;
893 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
894 } else {
895 // Commit will have to clean up whatever happened. Set this
896 // instruction as executed.
897 this->setExecuted();
898 }
899
900 if (fault != NoFault) {
901 // Return a fixed value to keep simulation deterministic even
902 // along misspeculated paths.
903 if (data)
904 bzero(data, size);
905 }
906 }
907
908 if (traceData) {
909 traceData->setAddr(addr);
910 }
911
912 return fault;
913}
914
915template<class Impl>
916template<class T>
917inline Fault
918BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
919{
920 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
921
922 data = TheISA::gtoh(data);
923
924 if (traceData) {
925 traceData->setData(data);
926 }
927
928 return fault;
929}
930
931template<class Impl>
932Fault
933BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
934 Addr addr, unsigned flags, uint64_t *res)
935{
936 if (traceData) {
937 traceData->setAddr(addr);
938 }
939
940 reqMade = true;
941 Request *req = NULL;
942 Request *sreqLow = NULL;
943 Request *sreqHigh = NULL;
944
945 if (reqMade && translationStarted) {
946 req = savedReq;
947 sreqLow = savedSreqLow;
948 sreqHigh = savedSreqHigh;
949 } else {
950 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
951 thread->contextId(), threadNumber);
952
953 // Only split the request if the ISA supports unaligned accesses.
954 if (TheISA::HasUnalignedMemAcc) {
955 splitRequest(req, sreqLow, sreqHigh);
956 }
957 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
958 }
959
960 if (fault == NoFault && translationCompleted) {
961 effAddr = req->getVaddr();
962 effSize = size;
963 effAddrValid = true;
964 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
965 }
966
967 return fault;
968}
969
970template<class Impl>
971template<class T>
972inline Fault
973BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
974{
975 if (traceData) {
976 traceData->setData(data);
977 }
978 data = TheISA::htog(data);
979 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
980}
981
982template<class Impl>
983inline void
984BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
985 RequestPtr &sreqHigh)
986{
987 // Check to see if the request crosses the next level block boundary.
988 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
989 Addr addr = req->getVaddr();
990 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
991 assert(split_addr <= addr || split_addr - addr < block_size);
992
993 // Spans two blocks.
994 if (split_addr > addr) {
995 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
996 }
997}
998
999template<class Impl>
1000inline void
1001BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1002 RequestPtr sreqHigh, uint64_t *res,
1003 BaseTLB::Mode mode)
1004{
1005 translationStarted = true;
1006
1007 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1008 WholeTranslationState *state =
1009 new WholeTranslationState(req, NULL, res, mode);
1010
1011 // One translation if the request isn't split.
1012 DataTranslation<BaseDynInst<Impl> > *trans =
1013 new DataTranslation<BaseDynInst<Impl> >(this, state);
1014 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1015 if (!translationCompleted) {
1016 // Save memory requests.
1017 savedReq = state->mainReq;
1018 savedSreqLow = state->sreqLow;
1019 savedSreqHigh = state->sreqHigh;
1020 }
1021 } else {
1022 WholeTranslationState *state =
1023 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1024
1025 // Two translations when the request is split.
1026 DataTranslation<BaseDynInst<Impl> > *stransLow =
1027 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
1028 DataTranslation<BaseDynInst<Impl> > *stransHigh =
1029 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
1030
1031 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1032 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1033 if (!translationCompleted) {
1034 // Save memory requests.
1035 savedReq = state->mainReq;
1036 savedSreqLow = state->sreqLow;
1037 savedSreqHigh = state->sreqHigh;
1038 }
1039 }
1040}
1041
1042template<class Impl>
1043inline void
1044BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1045{
1046 fault = state->getFault();
1047
1048 if (state->isUncacheable())
1049 isUncacheable = true;
1050
1051 if (fault == NoFault) {
1052 physEffAddr = state->getPaddr();
1053 memReqFlags = state->getFlags();
1054
1055 if (state->mainReq->isCondSwap()) {
1056 assert(state->res);
1057 state->mainReq->setExtraData(*state->res);
1058 }
1059
1060 } else {
1061 state->deleteReqs();
1062 }
1063 delete state;
1064
1065 translationCompleted = true;
1066}
1067
1068#endif // __CPU_BASE_DYN_INST_HH__