1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <deque>
52#include <list>
53#include <string>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/exec_context.hh"
61#include "cpu/exetrace.hh"
62#include "cpu/inst_res.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/o3/comm.hh"
65#include "cpu/op_class.hh"
66#include "cpu/static_inst.hh"
67#include "cpu/translation.hh"
68#include "mem/packet.hh"
69#include "mem/request.hh"
70#include "sim/byteswap.hh"
71#include "sim/system.hh"
72
73/**
74 * @file
75 * Defines a dynamic instruction context.
76 */
77
78template <class Impl>
79class BaseDynInst : public ExecContext, public RefCounted
80{
81 public:
82 // Typedef for the CPU.
83 typedef typename Impl::CPUType ImplCPU;
84 typedef typename ImplCPU::ImplState ImplState;
85 using VecRegContainer = TheISA::VecRegContainer;
86
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
90
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
93
94 enum {
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
97 };
98
99 protected:
100 enum Status {
101 IqEntry, /// Instruction is in the IQ
102 RobEntry, /// Instruction is in the ROB
103 LsqEntry, /// Instruction is in the LSQ
104 Completed, /// Instruction has completed
105 ResultReady, /// Instruction has its result
106 CanIssue, /// Instruction can issue and execute
107 Issued, /// Instruction has issued
108 Executed, /// Instruction has executed
109 CanCommit, /// Instruction can commit
110 AtCommit, /// Instruction has reached commit
111 Committed, /// Instruction has committed
112 Squashed, /// Instruction is squashed
113 SquashedInIQ, /// Instruction is squashed in the IQ
114 SquashedInLSQ, /// Instruction is squashed in the LSQ
115 SquashedInROB, /// Instruction is squashed in the ROB
116 RecoverInst, /// Is a recover instruction
117 BlockingInst, /// Is a blocking instruction
118 ThreadsyncWait, /// Is a thread synchronization instruction
119 SerializeBefore, /// Needs to serialize on
120 /// instructions ahead of it
121 SerializeAfter, /// Needs to serialize instructions behind it
122 SerializeHandled, /// Serialization has been handled
123 NumStatus
124 };
125
126 enum Flags {
127 TranslationStarted,
128 TranslationCompleted,
129 PossibleLoadViolation,
130 HitExternalSnoop,
131 EffAddrValid,
132 RecordResult,
133 Predicate,
134 PredTaken,
135 /** Whether or not the effective address calculation is completed.
136 * @todo: Consider if this is necessary or not.
137 */
138 EACalcDone,
139 IsStrictlyOrdered,
140 ReqMade,
141 MemOpDone,
142 MaxFlags
143 };
144
145 public:
146 /** The sequence number of the instruction. */
147 InstSeqNum seqNum;
148
149 /** The StaticInst used by this BaseDynInst. */
150 const StaticInstPtr staticInst;
151
152 /** Pointer to the Impl's CPU object. */
153 ImplCPU *cpu;
154
155 BaseCPU *getCpuPtr() { return cpu; }
156
157 /** Pointer to the thread state. */
158 ImplState *thread;
159
160 /** The kind of fault this instruction has generated. */
161 Fault fault;
162
163 /** InstRecord that tracks this instructions. */
164 Trace::InstRecord *traceData;
165
166 protected:
167 /** The result of the instruction; assumes an instruction can have many
168 * destination registers.
169 */
170 std::queue<InstResult> instResult;
171
172 /** PC state for this instruction. */
173 TheISA::PCState pc;
174
175 /* An amalgamation of a lot of boolean values into one */
176 std::bitset<MaxFlags> instFlags;
177
178 /** The status of this BaseDynInst. Several bits can be set. */
179 std::bitset<NumStatus> status;
180
181 /** Whether or not the source register is ready.
182 * @todo: Not sure this should be here vs the derived class.
183 */
184 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
185
186 public:
187 /** The thread this instruction is from. */
188 ThreadID threadNumber;
189
190 /** Iterator pointing to this BaseDynInst in the list of all insts. */
191 ListIt instListIt;
192
193 ////////////////////// Branch Data ///////////////
194 /** Predicted PC state after this instruction. */
195 TheISA::PCState predPC;
196
197 /** The Macroop if one exists */
198 const StaticInstPtr macroop;
199
200 /** How many source registers are ready. */
201 uint8_t readyRegs;
202
203 public:
204 /////////////////////// Load Store Data //////////////////////
205 /** The effective virtual address (lds & stores only). */
206 Addr effAddr;
207
208 /** The effective physical address. */
209 Addr physEffAddrLow;
210
211 /** The effective physical address
212 * of the second request for a split request
213 */
214 Addr physEffAddrHigh;
215
216 /** The memory request flags (from translation). */
217 unsigned memReqFlags;
218
219 /** data address space ID, for loads & stores. */
220 short asid;
221
222 /** The size of the request */
223 uint8_t effSize;
224
225 /** Pointer to the data for the memory access. */
226 uint8_t *memData;
227
228 /** Load queue index. */
229 int16_t lqIdx;
230
231 /** Store queue index. */
232 int16_t sqIdx;
233
234
235 /////////////////////// TLB Miss //////////////////////
236 /**
237 * Saved memory requests (needed when the DTB address translation is
238 * delayed due to a hw page table walk).
239 */
240 RequestPtr savedReq;
241 RequestPtr savedSreqLow;
242 RequestPtr savedSreqHigh;
243
244 /////////////////////// Checker //////////////////////
245 // Need a copy of main request pointer to verify on writes.
246 RequestPtr reqToVerify;
247
248 private:
249 /** Instruction effective address.
250 * @todo: Consider if this is necessary or not.
251 */
252 Addr instEffAddr;
253
254 protected:
255 /** Flattened register index of the destination registers of this
256 * instruction.
257 */
258 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
259
260 /** Physical register index of the destination registers of this
261 * instruction.
262 */
263 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
264
265 /** Physical register index of the source registers of this
266 * instruction.
267 */
268 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
269
270 /** Physical register index of the previous producers of the
271 * architected destinations.
272 */
273 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
274
275
276 public:
277 /** Records changes to result? */
278 void recordResult(bool f) { instFlags[RecordResult] = f; }
279
280 /** Is the effective virtual address valid. */
281 bool effAddrValid() const { return instFlags[EffAddrValid]; }
282
283 /** Whether or not the memory operation is done. */
284 bool memOpDone() const { return instFlags[MemOpDone]; }
285 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
286
287
288 ////////////////////////////////////////////
289 //
290 // INSTRUCTION EXECUTION
291 //
292 ////////////////////////////////////////////
293
294 void demapPage(Addr vaddr, uint64_t asn)
295 {
296 cpu->demapPage(vaddr, asn);
297 }
298 void demapInstPage(Addr vaddr, uint64_t asn)
299 {
300 cpu->demapPage(vaddr, asn);
301 }
302 void demapDataPage(Addr vaddr, uint64_t asn)
303 {
304 cpu->demapPage(vaddr, asn);
305 }
306
307 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
308
309 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
310 Request::Flags flags, uint64_t *res);
311
312 /** Splits a request in two if it crosses a dcache block. */
313 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
314 RequestPtr &sreqHigh);
315
316 /** Initiate a DTB address translation. */
317 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
318 RequestPtr sreqHigh, uint64_t *res,
319 BaseTLB::Mode mode);
320
321 /** Finish a DTB address translation. */
322 void finishTranslation(WholeTranslationState *state);
323
324 /** True if the DTB address translation has started. */
325 bool translationStarted() const { return instFlags[TranslationStarted]; }
326 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
327
328 /** True if the DTB address translation has completed. */
329 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
330 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
331
332 /** True if this address was found to match a previous load and they issued
333 * out of order. If that happend, then it's only a problem if an incoming
334 * snoop invalidate modifies the line, in which case we need to squash.
335 * If nothing modified the line the order doesn't matter.
336 */
337 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
338 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
339
340 /** True if the address hit a external snoop while sitting in the LSQ.
341 * If this is true and a older instruction sees it, this instruction must
342 * reexecute
343 */
344 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
345 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
346
347 /**
348 * Returns true if the DTB address translation is being delayed due to a hw
349 * page table walk.
350 */
351 bool isTranslationDelayed() const
352 {
353 return (translationStarted() && !translationCompleted());
354 }
355
356 public:
357#ifdef DEBUG
358 void dumpSNList();
359#endif
360
361 /** Returns the physical register index of the i'th destination
362 * register.
363 */
364 PhysRegIdPtr renamedDestRegIdx(int idx) const
365 {
366 return _destRegIdx[idx];
367 }
368
369 /** Returns the physical register index of the i'th source register. */
370 PhysRegIdPtr renamedSrcRegIdx(int idx) const
371 {
372 assert(TheISA::MaxInstSrcRegs > idx);
373 return _srcRegIdx[idx];
374 }
375
376 /** Returns the flattened register index of the i'th destination
377 * register.
378 */
379 const RegId& flattenedDestRegIdx(int idx) const
380 {
381 return _flatDestRegIdx[idx];
382 }
383
384 /** Returns the physical register index of the previous physical register
385 * that remapped to the same logical register index.
386 */
387 PhysRegIdPtr prevDestRegIdx(int idx) const
388 {
389 return _prevDestRegIdx[idx];
390 }
391
392 /** Renames a destination register to a physical register. Also records
393 * the previous physical register that the logical register mapped to.
394 */
395 void renameDestReg(int idx,
396 PhysRegIdPtr renamed_dest,
397 PhysRegIdPtr previous_rename)
398 {
399 _destRegIdx[idx] = renamed_dest;
400 _prevDestRegIdx[idx] = previous_rename;
401 }
402
403 /** Renames a source logical register to the physical register which
404 * has/will produce that logical register's result.
405 * @todo: add in whether or not the source register is ready.
406 */
407 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
408 {
409 _srcRegIdx[idx] = renamed_src;
410 }
411
412 /** Flattens a destination architectural register index into a logical
413 * index.
414 */
415 void flattenDestReg(int idx, const RegId& flattened_dest)
416 {
417 _flatDestRegIdx[idx] = flattened_dest;
418 }
419 /** BaseDynInst constructor given a binary instruction.
420 * @param staticInst A StaticInstPtr to the underlying instruction.
421 * @param pc The PC state for the instruction.
422 * @param predPC The predicted next PC state for the instruction.
423 * @param seq_num The sequence number of the instruction.
424 * @param cpu Pointer to the instruction's CPU.
425 */
426 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
427 TheISA::PCState pc, TheISA::PCState predPC,
428 InstSeqNum seq_num, ImplCPU *cpu);
429
430 /** BaseDynInst constructor given a StaticInst pointer.
431 * @param _staticInst The StaticInst for this BaseDynInst.
432 */
433 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
434
435 /** BaseDynInst destructor. */
436 ~BaseDynInst();
437
438 private:
439 /** Function to initialize variables in the constructors. */
440 void initVars();
441
442 public:
443 /** Dumps out contents of this BaseDynInst. */
444 void dump();
445
446 /** Dumps out contents of this BaseDynInst into given string. */
447 void dump(std::string &outstring);
448
449 /** Read this CPU's ID. */
450 int cpuId() const { return cpu->cpuId(); }
451
452 /** Read this CPU's Socket ID. */
453 uint32_t socketId() const { return cpu->socketId(); }
454
455 /** Read this CPU's data requestor ID */
456 MasterID masterId() const { return cpu->dataMasterId(); }
457
458 /** Read this context's system-wide ID **/
459 ContextID contextId() const { return thread->contextId(); }
460
461 /** Returns the fault type. */
462 Fault getFault() const { return fault; }
463
464 /** Checks whether or not this instruction has had its branch target
465 * calculated yet. For now it is not utilized and is hacked to be
466 * always false.
467 * @todo: Actually use this instruction.
468 */
469 bool doneTargCalc() { return false; }
470
471 /** Set the predicted target of this current instruction. */
472 void setPredTarg(const TheISA::PCState &_predPC)
473 {
474 predPC = _predPC;
475 }
476
477 const TheISA::PCState &readPredTarg() { return predPC; }
478
479 /** Returns the predicted PC immediately after the branch. */
480 Addr predInstAddr() { return predPC.instAddr(); }
481
482 /** Returns the predicted PC two instructions after the branch */
483 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
484
485 /** Returns the predicted micro PC after the branch */
486 Addr predMicroPC() { return predPC.microPC(); }
487
488 /** Returns whether the instruction was predicted taken or not. */
489 bool readPredTaken()
490 {
491 return instFlags[PredTaken];
492 }
493
494 void setPredTaken(bool predicted_taken)
495 {
496 instFlags[PredTaken] = predicted_taken;
497 }
498
499 /** Returns whether the instruction mispredicted. */
500 bool mispredicted()
501 {
502 TheISA::PCState tempPC = pc;
503 TheISA::advancePC(tempPC, staticInst);
504 return !(tempPC == predPC);
505 }
506
507 //
508 // Instruction types. Forward checks to StaticInst object.
509 //
510 bool isNop() const { return staticInst->isNop(); }
511 bool isMemRef() const { return staticInst->isMemRef(); }
512 bool isLoad() const { return staticInst->isLoad(); }
513 bool isStore() const { return staticInst->isStore(); }
514 bool isStoreConditional() const
515 { return staticInst->isStoreConditional(); }
516 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
517 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
518 bool isInteger() const { return staticInst->isInteger(); }
519 bool isFloating() const { return staticInst->isFloating(); }
520 bool isVector() const { return staticInst->isVector(); }
521 bool isControl() const { return staticInst->isControl(); }
522 bool isCall() const { return staticInst->isCall(); }
523 bool isReturn() const { return staticInst->isReturn(); }
524 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
525 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
526 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
527 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
528 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
529 bool isThreadSync() const { return staticInst->isThreadSync(); }
530 bool isSerializing() const { return staticInst->isSerializing(); }
531 bool isSerializeBefore() const
532 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
533 bool isSerializeAfter() const
534 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
535 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
536 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
537 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
538 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
539 bool isQuiesce() const { return staticInst->isQuiesce(); }
540 bool isIprAccess() const { return staticInst->isIprAccess(); }
541 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
542 bool isSyscall() const { return staticInst->isSyscall(); }
543 bool isMacroop() const { return staticInst->isMacroop(); }
544 bool isMicroop() const { return staticInst->isMicroop(); }
545 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
546 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
547 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
548 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
549
550 /** Temporarily sets this instruction as a serialize before instruction. */
551 void setSerializeBefore() { status.set(SerializeBefore); }
552
553 /** Clears the serializeBefore part of this instruction. */
554 void clearSerializeBefore() { status.reset(SerializeBefore); }
555
556 /** Checks if this serializeBefore is only temporarily set. */
557 bool isTempSerializeBefore() { return status[SerializeBefore]; }
558
559 /** Temporarily sets this instruction as a serialize after instruction. */
560 void setSerializeAfter() { status.set(SerializeAfter); }
561
562 /** Clears the serializeAfter part of this instruction.*/
563 void clearSerializeAfter() { status.reset(SerializeAfter); }
564
565 /** Checks if this serializeAfter is only temporarily set. */
566 bool isTempSerializeAfter() { return status[SerializeAfter]; }
567
568 /** Sets the serialization part of this instruction as handled. */
569 void setSerializeHandled() { status.set(SerializeHandled); }
570
571 /** Checks if the serialization part of this instruction has been
572 * handled. This does not apply to the temporary serializing
573 * state; it only applies to this instruction's own permanent
574 * serializing state.
575 */
576 bool isSerializeHandled() { return status[SerializeHandled]; }
577
578 /** Returns the opclass of this instruction. */
579 OpClass opClass() const { return staticInst->opClass(); }
580
581 /** Returns the branch target address. */
582 TheISA::PCState branchTarget() const
583 { return staticInst->branchTarget(pc); }
584
585 /** Returns the number of source registers. */
586 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
587
588 /** Returns the number of destination registers. */
589 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
590
591 // the following are used to track physical register usage
592 // for machines with separate int & FP reg files
593 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
594 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
595 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
596 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
597 int8_t numVecElemDestRegs() const {
598 return staticInst->numVecElemDestRegs();
599 }
600
601 /** Returns the logical register index of the i'th destination register. */
602 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
603
604 /** Returns the logical register index of the i'th source register. */
605 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
606
607 /** Return the size of the instResult queue. */
608 uint8_t resultSize() { return instResult.size(); }
609
610 /** Pops a result off the instResult queue.
611 * If the result stack is empty, return the default value.
612 * */
613 InstResult popResult(InstResult dflt = InstResult())
614 {
615 if (!instResult.empty()) {
616 InstResult t = instResult.front();
617 instResult.pop();
618 return t;
619 }
620 return dflt;
621 }
622
623 /** Pushes a result onto the instResult queue. */
624 /** @{ */
625 /** Scalar result. */
626 template<typename T>
627 void setScalarResult(T&& t)
628 {
629 if (instFlags[RecordResult]) {
630 instResult.push(InstResult(std::forward<T>(t),
631 InstResult::ResultType::Scalar));
632 }
633 }
634
635 /** Full vector result. */
636 template<typename T>
637 void setVecResult(T&& t)
638 {
639 if (instFlags[RecordResult]) {
640 instResult.push(InstResult(std::forward<T>(t),
641 InstResult::ResultType::VecReg));
642 }
643 }
644
645 /** Vector element result. */
646 template<typename T>
647 void setVecElemResult(T&& t)
648 {
649 if (instFlags[RecordResult]) {
650 instResult.push(InstResult(std::forward<T>(t),
651 InstResult::ResultType::VecElem));
652 }
653 }
654 /** @} */
655
656 /** Records an integer register being set to a value. */
657 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
658 {
659 setScalarResult(val);
660 }
661
662 /** Records a CC register being set to a value. */
663 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
664 {
665 setScalarResult(val);
666 }
667
668 /** Records an fp register being set to a value. */
669 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
670 {
671 setScalarResult(val);
672 }
673
674 /** Record a vector register being set to a value */
675 void setVecRegOperand(const StaticInst *si, int idx,
676 const VecRegContainer& val)
677 {
678 setVecResult(val);
679 }
680
681 /** Records an fp register being set to an integer value. */
682 void
683 setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
684 {
685 setScalarResult(val);
686 }
687
688 /** Record a vector register being set to a value */
689 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
690 {
691 setVecElemResult(val);
692 }
693
694 /** Records that one of the source registers is ready. */
695 void markSrcRegReady();
696
697 /** Marks a specific register as ready. */
698 void markSrcRegReady(RegIndex src_idx);
699
700 /** Returns if a source register is ready. */
701 bool isReadySrcRegIdx(int idx) const
702 {
703 return this->_readySrcRegIdx[idx];
704 }
705
706 /** Sets this instruction as completed. */
707 void setCompleted() { status.set(Completed); }
708
709 /** Returns whether or not this instruction is completed. */
710 bool isCompleted() const { return status[Completed]; }
711
712 /** Marks the result as ready. */
713 void setResultReady() { status.set(ResultReady); }
714
715 /** Returns whether or not the result is ready. */
716 bool isResultReady() const { return status[ResultReady]; }
717
718 /** Sets this instruction as ready to issue. */
719 void setCanIssue() { status.set(CanIssue); }
720
721 /** Returns whether or not this instruction is ready to issue. */
722 bool readyToIssue() const { return status[CanIssue]; }
723
724 /** Clears this instruction being able to issue. */
725 void clearCanIssue() { status.reset(CanIssue); }
726
727 /** Sets this instruction as issued from the IQ. */
728 void setIssued() { status.set(Issued); }
729
730 /** Returns whether or not this instruction has issued. */
731 bool isIssued() const { return status[Issued]; }
732
733 /** Clears this instruction as being issued. */
734 void clearIssued() { status.reset(Issued); }
735
736 /** Sets this instruction as executed. */
737 void setExecuted() { status.set(Executed); }
738
739 /** Returns whether or not this instruction has executed. */
740 bool isExecuted() const { return status[Executed]; }
741
742 /** Sets this instruction as ready to commit. */
743 void setCanCommit() { status.set(CanCommit); }
744
745 /** Clears this instruction as being ready to commit. */
746 void clearCanCommit() { status.reset(CanCommit); }
747
748 /** Returns whether or not this instruction is ready to commit. */
749 bool readyToCommit() const { return status[CanCommit]; }
750
751 void setAtCommit() { status.set(AtCommit); }
752
753 bool isAtCommit() { return status[AtCommit]; }
754
755 /** Sets this instruction as committed. */
756 void setCommitted() { status.set(Committed); }
757
758 /** Returns whether or not this instruction is committed. */
759 bool isCommitted() const { return status[Committed]; }
760
761 /** Sets this instruction as squashed. */
762 void setSquashed() { status.set(Squashed); }
763
764 /** Returns whether or not this instruction is squashed. */
765 bool isSquashed() const { return status[Squashed]; }
766
767 //Instruction Queue Entry
768 //-----------------------
769 /** Sets this instruction as a entry the IQ. */
770 void setInIQ() { status.set(IqEntry); }
771
772 /** Sets this instruction as a entry the IQ. */
773 void clearInIQ() { status.reset(IqEntry); }
774
775 /** Returns whether or not this instruction has issued. */
776 bool isInIQ() const { return status[IqEntry]; }
777
778 /** Sets this instruction as squashed in the IQ. */
779 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
780
781 /** Returns whether or not this instruction is squashed in the IQ. */
782 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
783
784
785 //Load / Store Queue Functions
786 //-----------------------
787 /** Sets this instruction as a entry the LSQ. */
788 void setInLSQ() { status.set(LsqEntry); }
789
790 /** Sets this instruction as a entry the LSQ. */
791 void removeInLSQ() { status.reset(LsqEntry); }
792
793 /** Returns whether or not this instruction is in the LSQ. */
794 bool isInLSQ() const { return status[LsqEntry]; }
795
796 /** Sets this instruction as squashed in the LSQ. */
797 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
798
799 /** Returns whether or not this instruction is squashed in the LSQ. */
800 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
801
802
803 //Reorder Buffer Functions
804 //-----------------------
805 /** Sets this instruction as a entry the ROB. */
806 void setInROB() { status.set(RobEntry); }
807
808 /** Sets this instruction as a entry the ROB. */
809 void clearInROB() { status.reset(RobEntry); }
810
811 /** Returns whether or not this instruction is in the ROB. */
812 bool isInROB() const { return status[RobEntry]; }
813
814 /** Sets this instruction as squashed in the ROB. */
815 void setSquashedInROB() { status.set(SquashedInROB); }
816
817 /** Returns whether or not this instruction is squashed in the ROB. */
818 bool isSquashedInROB() const { return status[SquashedInROB]; }
819
820 /** Read the PC state of this instruction. */
821 TheISA::PCState pcState() const { return pc; }
822
823 /** Set the PC state of this instruction. */
824 void pcState(const TheISA::PCState &val) { pc = val; }
825
826 /** Read the PC of this instruction. */
827 Addr instAddr() const { return pc.instAddr(); }
828
829 /** Read the PC of the next instruction. */
830 Addr nextInstAddr() const { return pc.nextInstAddr(); }
831
832 /**Read the micro PC of this instruction. */
833 Addr microPC() const { return pc.microPC(); }
834
835 bool readPredicate()
836 {
837 return instFlags[Predicate];
838 }
839
840 void setPredicate(bool val)
841 {
842 instFlags[Predicate] = val;
843
844 if (traceData) {
845 traceData->setPredicate(val);
846 }
847 }
848
849 /** Sets the ASID. */
850 void setASID(short addr_space_id) { asid = addr_space_id; }
851
852 /** Sets the thread id. */
853 void setTid(ThreadID tid) { threadNumber = tid; }
854
855 /** Sets the pointer to the thread state. */
856 void setThreadState(ImplState *state) { thread = state; }
857
858 /** Returns the thread context. */
859 ThreadContext *tcBase() { return thread->getTC(); }
860
861 public:
862 /** Sets the effective address. */
863 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
864
865 /** Returns the effective address. */
866 Addr getEA() const { return instEffAddr; }
867
868 /** Returns whether or not the eff. addr. calculation has been completed. */
869 bool doneEACalc() { return instFlags[EACalcDone]; }
870
871 /** Returns whether or not the eff. addr. source registers are ready. */
872 bool eaSrcsReady();
873
874 /** Is this instruction's memory access strictly ordered? */
875 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
876
877 /** Has this instruction generated a memory request. */
878 bool hasRequest() { return instFlags[ReqMade]; }
879
880 /** Returns iterator to this instruction in the list of all insts. */
881 ListIt &getInstListIt() { return instListIt; }
882
883 /** Sets iterator for this instruction in the list of all insts. */
884 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
885
886 public:
887 /** Returns the number of consecutive store conditional failures. */
888 unsigned int readStCondFailures() const
889 { return thread->storeCondFailures; }
890
891 /** Sets the number of consecutive store conditional failures. */
892 void setStCondFailures(unsigned int sc_failures)
893 { thread->storeCondFailures = sc_failures; }
894
895 public:
896 // monitor/mwait funtions
897 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
898 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
899 void mwaitAtomic(ThreadContext *tc)
900 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
901 AddressMonitor *getAddrMonitor()
902 { return cpu->getCpuAddrMonitor(threadNumber); }
903};
904
905template<class Impl>
906Fault
907BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
908 Request::Flags flags)
909{
910 instFlags[ReqMade] = true;
911 Request *req = NULL;
912 Request *sreqLow = NULL;
913 Request *sreqHigh = NULL;
914
915 if (instFlags[ReqMade] && translationStarted()) {
916 req = savedReq;
917 sreqLow = savedSreqLow;
918 sreqHigh = savedSreqHigh;
919 } else {
920 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
921 thread->contextId());
922
923 req->taskId(cpu->taskId());
924
925 // Only split the request if the ISA supports unaligned accesses.
926 if (TheISA::HasUnalignedMemAcc) {
927 splitRequest(req, sreqLow, sreqHigh);
928 }
929 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
930 }
931
932 if (translationCompleted()) {
933 if (fault == NoFault) {
934 effAddr = req->getVaddr();
935 effSize = size;
936 instFlags[EffAddrValid] = true;
937
938 if (cpu->checker) {
939 if (reqToVerify != NULL) {
940 delete reqToVerify;
941 }
942 reqToVerify = new Request(*req);
943 }
944 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
945 } else {
946 // Commit will have to clean up whatever happened. Set this
947 // instruction as executed.
948 this->setExecuted();
949 }
950 }
951
952 if (traceData)
953 traceData->setMem(addr, size, flags);
954
955 return fault;
956}
957
958template<class Impl>
959Fault
960BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
961 Request::Flags flags, uint64_t *res)
962{
963 if (traceData)
964 traceData->setMem(addr, size, flags);
965
966 instFlags[ReqMade] = true;
967 Request *req = NULL;
968 Request *sreqLow = NULL;
969 Request *sreqHigh = NULL;
970
971 if (instFlags[ReqMade] && translationStarted()) {
972 req = savedReq;
973 sreqLow = savedSreqLow;
974 sreqHigh = savedSreqHigh;
975 } else {
976 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
977 thread->contextId());
978
979 req->taskId(cpu->taskId());
980
981 // Only split the request if the ISA supports unaligned accesses.
982 if (TheISA::HasUnalignedMemAcc) {
983 splitRequest(req, sreqLow, sreqHigh);
984 }
985 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
986 }
987
988 if (fault == NoFault && translationCompleted()) {
989 effAddr = req->getVaddr();
990 effSize = size;
991 instFlags[EffAddrValid] = true;
992
993 if (cpu->checker) {
994 if (reqToVerify != NULL) {
995 delete reqToVerify;
996 }
997 reqToVerify = new Request(*req);
998 }
999 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
1000 }
1001
1002 return fault;
1003}
1004
1005template<class Impl>
1006inline void
1007BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
1008 RequestPtr &sreqHigh)
1009{
1010 // Check to see if the request crosses the next level block boundary.
1011 unsigned block_size = cpu->cacheLineSize();
1012 Addr addr = req->getVaddr();
1013 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
1014 assert(split_addr <= addr || split_addr - addr < block_size);
1015
1016 // Spans two blocks.
1017 if (split_addr > addr) {
1018 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1019 }
1020}
1021
1022template<class Impl>
1023inline void
1024BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1025 RequestPtr sreqHigh, uint64_t *res,
1026 BaseTLB::Mode mode)
1027{
1028 translationStarted(true);
1029
1030 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1031 WholeTranslationState *state =
1032 new WholeTranslationState(req, NULL, res, mode);
1033
1034 // One translation if the request isn't split.
1035 DataTranslation<BaseDynInstPtr> *trans =
1036 new DataTranslation<BaseDynInstPtr>(this, state);
1037
1038 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1039
1040 if (!translationCompleted()) {
1041 // The translation isn't yet complete, so we can't possibly have a
1042 // fault. Overwrite any existing fault we might have from a previous
1043 // execution of this instruction (e.g. an uncachable load that
1044 // couldn't execute because it wasn't at the head of the ROB).
1045 fault = NoFault;
1046
1047 // Save memory requests.
1048 savedReq = state->mainReq;
1049 savedSreqLow = state->sreqLow;
1050 savedSreqHigh = state->sreqHigh;
1051 }
1052 } else {
1053 WholeTranslationState *state =
1054 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1055
1056 // Two translations when the request is split.
1057 DataTranslation<BaseDynInstPtr> *stransLow =
1058 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1059 DataTranslation<BaseDynInstPtr> *stransHigh =
1060 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1061
1062 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1063 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1064
1065 if (!translationCompleted()) {
1066 // The translation isn't yet complete, so we can't possibly have a
1067 // fault. Overwrite any existing fault we might have from a previous
1068 // execution of this instruction (e.g. an uncachable load that
1069 // couldn't execute because it wasn't at the head of the ROB).
1070 fault = NoFault;
1071
1072 // Save memory requests.
1073 savedReq = state->mainReq;
1074 savedSreqLow = state->sreqLow;
1075 savedSreqHigh = state->sreqHigh;
1076 }
1077 }
1078}
1079
1080template<class Impl>
1081inline void
1082BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1083{
1084 fault = state->getFault();
1085
1086 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1087
1088 if (fault == NoFault) {
1089 // save Paddr for a single req
1090 physEffAddrLow = state->getPaddr();
1091
1092 // case for the request that has been split
1093 if (state->isSplit) {
1094 physEffAddrLow = state->sreqLow->getPaddr();
1095 physEffAddrHigh = state->sreqHigh->getPaddr();
1096 }
1097
1098 memReqFlags = state->getFlags();
1099
1100 if (state->mainReq->isCondSwap()) {
1101 assert(state->res);
1102 state->mainReq->setExtraData(*state->res);
1103 }
1104
1105 } else {
1106 state->deleteReqs();
1107 }
1108 delete state;
1109
1110 translationCompleted(true);
1111}
1112
1113#endif // __CPU_BASE_DYN_INST_HH__