1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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1004
1005 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1006 WholeTranslationState *state =
1007 new WholeTranslationState(req, NULL, res, mode);
1008
1009 // One translation if the request isn't split.
1010 DataTranslation<BaseDynInstPtr> *trans =
1011 new DataTranslation<BaseDynInstPtr>(this, state);
1012 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1013 if (!translationCompleted()) {
1014 // Save memory requests.
1015 savedReq = state->mainReq;
1016 savedSreqLow = state->sreqLow;
1017 savedSreqHigh = state->sreqHigh;
1018 }
1019 } else {
1020 WholeTranslationState *state =
1021 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1022
1023 // Two translations when the request is split.
1024 DataTranslation<BaseDynInstPtr> *stransLow =
1025 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1026 DataTranslation<BaseDynInstPtr> *stransHigh =
1027 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1028
1029 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1030 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1031 if (!translationCompleted()) {
1032 // Save memory requests.
1033 savedReq = state->mainReq;
1034 savedSreqLow = state->sreqLow;
1035 savedSreqHigh = state->sreqHigh;
1036 }
1037 }
1038}
1039

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