1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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97 * @param addr The address to read.
98 * @param data The read's data is written into this parameter.
99 * @param flags The request's flags.
100 * @return Returns any fault due to the read.
101 */
102 template <class T>
103 Fault read(Addr addr, T &data, unsigned flags);
104
105 /**
106 * Does a write to a given address.
107 * @param data The data to be written.
108 * @param addr The address to write to.
109 * @param flags The request's flags.
110 * @param res The result of the write (for load locked/store conditionals).
111 * @return Returns any fault due to the write.
112 */
113 template <class T>
114 Fault write(T data, Addr addr, unsigned flags,
115 uint64_t *res);
116
117 void prefetch(Addr addr, unsigned flags);
118 void writeHint(Addr addr, int size, unsigned flags);
119 Fault copySrcTranslate(Addr src);
120 Fault copy(Addr dest);
121
122 /** @todo: Consider making this private. */
123 public:
124 /** The sequence number of the instruction. */

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833 { return thread->storeCondFailures; }
834
835 /** Sets the number of consecutive store conditional failures. */
836 void setStCondFailures(unsigned sc_failures)
837 { thread->storeCondFailures = sc_failures; }
838};
839
840template<class Impl>
841template<class T>
842inline Fault
843BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
844{
845 reqMade = true;
846 Request *req = new Request();
847 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
848 req->setThreadContext(thread->readCpuId(), threadNumber);

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884 traceData->setAddr(addr);
885 traceData->setData(data);
886 }
887
888 return fault;
889}
890
891template<class Impl>
892template<class T>
893inline Fault
894BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
895{
896 if (traceData) {
897 traceData->setAddr(addr);
898 traceData->setData(data);
899 }

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