1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 207 unchanged lines hidden (view full) ---

216 Addr nextPC;
217
218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
219 Addr nextNPC;
220
221 /** Predicted next PC. */
222 Addr predPC;
223
224 /** Count of total number of dynamic instructions. */
225 static int instcount;
226
227#ifdef DEBUG
228 void dumpSNList();
229#endif
230
231 /** Whether or not the source register is ready.

--- 99 unchanged lines hidden (view full) ---

331 {
332 _flatDestRegIdx[idx] = flattened_dest;
333 }
334
335 /** BaseDynInst constructor given a binary instruction.
336 * @param inst The binary instruction.
337 * @param PC The PC of the instruction.
338 * @param pred_PC The predicted next PC.
339 * @param seq_num The sequence number of the instruction.
340 * @param cpu Pointer to the instruction's CPU.
341 */
342 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr pred_PC,
343 InstSeqNum seq_num, ImplCPU *cpu);
344
345 /** BaseDynInst constructor given a StaticInst pointer.
346 * @param _staticInst The StaticInst for this BaseDynInst.
347 */
348 BaseDynInst(StaticInstPtr &_staticInst);
349
350 /** BaseDynInst destructor. */

--- 29 unchanged lines hidden (view full) ---

380 Addr readNextPC() { return nextPC; }
381
382 /** Returns the next NPC. This could be the speculative next NPC if it is
383 * called prior to the actual branch target being calculated.
384 */
385 Addr readNextNPC() { return nextNPC; }
386
387 /** Set the predicted target of this current instruction. */
388 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
389
390 /** Returns the predicted target of the branch. */
391 Addr readPredTarg() { return predPC; }
392
393 /** Returns whether the instruction was predicted taken or not. */
394 bool predTaken()
395#if ISA_HAS_DELAY_SLOT
396 { return predPC != (nextPC + sizeof(TheISA::MachInst)); }
397#else
398 { return predPC != (PC + sizeof(TheISA::MachInst)); }
399#endif
400
401 /** Returns whether the instruction mispredicted. */
402 bool mispredicted()
403#if ISA_HAS_DELAY_SLOT
404 { return predPC != nextNPC; }
405#else
406 { return predPC != nextPC; }
407#endif
408 //
409 // Instruction types. Forward checks to StaticInst object.
410 //
411 bool isNop() const { return staticInst->isNop(); }
412 bool isMemRef() const { return staticInst->isMemRef(); }
413 bool isLoad() const { return staticInst->isLoad(); }
414 bool isStore() const { return staticInst->isStore(); }
415 bool isStoreConditional() const

--- 434 unchanged lines hidden ---