1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include <bitset>
35#include <list>
36#include <string>
37
38#include "arch/faults.hh"
39#include "base/fast_alloc.hh"
40#include "base/trace.hh"
41#include "config/full_system.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/inst_seq.hh"
44#include "cpu/op_class.hh"
45#include "cpu/static_inst.hh"
46#include "mem/packet.hh"
47#include "sim/system.hh"
48
49/**

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57template <class Impl>
58class BaseDynInst : public FastAlloc, public RefCounted
59{
60 public:
61 // Typedef for the CPU.
62 typedef typename Impl::CPUType ImplCPU;
63 typedef typename ImplCPU::ImplState ImplState;
64
65 // Binary machine instruction type.
66 typedef TheISA::MachInst MachInst;
67 // Extended machine instruction type
68 typedef TheISA::ExtMachInst ExtMachInst;
69 // Logical register index type.
70 typedef TheISA::RegIndex RegIndex;
71 // Integer register type.
72 typedef TheISA::IntReg IntReg;
73 // Floating point register type.
74 typedef TheISA::FloatReg FloatReg;
75
76 // The DynInstPtr type.

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231 void dumpSNList();
232#endif
233
234 /** Whether or not the source register is ready.
235 * @todo: Not sure this should be here vs the derived class.
236 */
237 bool _readySrcRegIdx[MaxInstSrcRegs];
238
239 public:
240 /** BaseDynInst constructor given a binary instruction.
241 * @param inst The binary instruction.
242 * @param PC The PC of the instruction.
243 * @param pred_PC The predicted next PC.
244 * @param seq_num The sequence number of the instruction.
245 * @param cpu Pointer to the instruction's CPU.
246 */
247 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
248 ImplCPU *cpu);
249
250 /** BaseDynInst constructor given a StaticInst pointer.
251 * @param _staticInst The StaticInst for this BaseDynInst.
252 */
253 BaseDynInst(StaticInstPtr &_staticInst);
254
255 /** BaseDynInst destructor. */
256 ~BaseDynInst();

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293 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
294
295 /** Returns the predicted target of the branch. */
296 Addr readPredTarg() { return predPC; }
297
298 /** Returns whether the instruction was predicted taken or not. */
299 bool predTaken()
300#if ISA_HAS_DELAY_SLOT
301 { return predPC != (nextPC + sizeof(MachInst)); }
302#else
303 { return predPC != (PC + sizeof(MachInst)); }
304#endif
305
306 /** Returns whether the instruction mispredicted. */
307 bool mispredicted()
308#if ISA_HAS_DELAY_SLOT
309 { return predPC != nextNPC; }
310#else
311 { return predPC != nextPC; }

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401
402 /** Returns the result of a floating point instruction. */
403 float readFloatResult() { return (float)instResult.dbl; }
404
405 /** Returns the result of a floating point (double) instruction. */
406 double readDoubleResult() { return instResult.dbl; }
407
408 /** Records an integer register being set to a value. */
409 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
410 {
411 if (recordResult)
412 instResult.integer = val;
413 }
414
415 /** Records an fp register being set to a value. */
416 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
417 int width)
418 {
419 if (recordResult) {
420 if (width == 32)
421 instResult.dbl = (double)val;
422 else if (width == 64)
423 instResult.dbl = val;
424 else
425 panic("Unsupported width!");
426 }
427 }
428
429 /** Records an fp register being set to a value. */
430 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
431 {
432 if (recordResult)
433 instResult.dbl = (double)val;
434 }
435
436 /** Records an fp register being set to an integer value. */
437 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
438 int width)
439 {
440 if (recordResult)
441 instResult.integer = val;
442 }
443
444 /** Records an fp register being set to an integer value. */
445 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
446 {
447 if (recordResult)
448 instResult.integer = val;
449 }
450
451 /** Records that one of the source registers is ready. */
452 void markSrcRegReady();
453

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