1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#ifndef __CPU_BASE_DYN_INST_HH__
32#define __CPU_BASE_DYN_INST_HH__
33
34#include <list>
35#include <string>
36
37#include "arch/faults.hh"
38#include "base/fast_alloc.hh"
39#include "base/trace.hh"
40#include "config/full_system.hh"
41#include "cpu/exetrace.hh"

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121 Fault copySrcTranslate(Addr src);
122 Fault copy(Addr dest);
123
124 /** @todo: Consider making this private. */
125 public:
126 /** The sequence number of the instruction. */
127 InstSeqNum seqNum;
128
129 /** Is the instruction in the IQ */
130 bool iqEntry;
131
132 /** Is the instruction in the ROB */
133 bool robEntry;
134
135 /** Is the instruction in the LSQ */
136 bool lsqEntry;
137
138 /** Is the instruction completed. */
139 bool completed;
140
141 /** Is the instruction's result ready. */
142 bool resultReady;
143
144 /** Can this instruction issue. */
145 bool canIssue;
146
147 /** Has this instruction issued. */
148 bool issued;
149
150 /** Has this instruction executed (or made it through execute) yet. */
151 bool executed;
152
153 /** Can this instruction commit. */
154 bool canCommit;
155
156 /** Is this instruction committed. */
157 bool committed;
158
159 /** Is this instruction squashed. */
160 bool squashed;
161
162 /** Is this instruction squashed in the instruction queue. */
163 bool squashedInIQ;
164
165 /** Is this instruction squashed in the instruction queue. */
166 bool squashedInLSQ;
167
168 /** Is this instruction squashed in the instruction queue. */
169 bool squashedInROB;
170
171 /** Is this a recover instruction. */
172 bool recoverInst;
173
174 /** Is this a thread blocking instruction. */
175 bool blockingInst; /* this inst has called thread_block() */
176
177 /** Is this a thread syncrhonization instruction. */
178 bool threadsyncWait;
179
180 /** The thread this instruction is from. */
181 short threadNumber;
182
183 /** data address space ID, for loads & stores. */
184 short asid;
185
186 /** How many source registers are ready. */
187 unsigned readyRegs;

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211 Addr copySrcEffAddr;
212
213 /** Effective physical address for a copy source. */
214 Addr copySrcPhysEffAddr;
215
216 /** The memory request flags (from translation). */
217 unsigned memReqFlags;
218
219 /** The size of the data to be stored. */
220 int storeSize;
221
222 /** The data to be stored. */
223 IntReg storeData;
224
225 union Result {
226 uint64_t integer;
227 float fp;
228 double dbl;
229 };
230
231 /** The result of the instruction; assumes for now that there's only one
232 * destination register.

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333 bool isReturn() const { return staticInst->isReturn(); }
334 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
335 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
336 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
337 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
338 bool isThreadSync() const { return staticInst->isThreadSync(); }
339 bool isSerializing() const { return staticInst->isSerializing(); }
340 bool isSerializeBefore() const
341 { return staticInst->isSerializeBefore() || serializeBefore; }
342 bool isSerializeAfter() const
343 { return staticInst->isSerializeAfter() || serializeAfter; }
344 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
345 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
346 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
347 bool isQuiesce() const { return staticInst->isQuiesce(); }
348 bool isIprAccess() const { return staticInst->isIprAccess(); }
349 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
350
351 /** Temporarily sets this instruction as a serialize before instruction. */
352 void setSerializeBefore() { serializeBefore = true; }
353
354 /** Clears the serializeBefore part of this instruction. */
355 void clearSerializeBefore() { serializeBefore = false; }
356
357 /** Checks if this serializeBefore is only temporarily set. */
358 bool isTempSerializeBefore() { return serializeBefore; }
359
360 /** Tracks if instruction has been externally set as serializeBefore. */
361 bool serializeBefore;
362
363 /** Temporarily sets this instruction as a serialize after instruction. */
364 void setSerializeAfter() { serializeAfter = true; }
365
366 /** Clears the serializeAfter part of this instruction.*/
367 void clearSerializeAfter() { serializeAfter = false; }
368
369 /** Checks if this serializeAfter is only temporarily set. */
370 bool isTempSerializeAfter() { return serializeAfter; }
371
372 /** Tracks if instruction has been externally set as serializeAfter. */
373 bool serializeAfter;
374
375 /** Checks if the serialization part of this instruction has been
376 * handled. This does not apply to the temporary serializing
377 * state; it only applies to this instruction's own permanent
378 * serializing state.
379 */
380 bool isSerializeHandled() { return serializeHandled; }
381
382 /** Sets the serialization part of this instruction as handled. */
383 void setSerializeHandled() { serializeHandled = true; }
384
385 /** Whether or not the serialization of this instruction has been handled. */
386 bool serializeHandled;
387
388 /** Returns the opclass of this instruction. */
389 OpClass opClass() const { return staticInst->opClass(); }
390
391 /** Returns the branch target address. */
392 Addr branchTarget() const { return staticInst->branchTarget(PC); }
393
394 /** Returns the number of source registers. */
395 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }

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460
461 /** Returns if a source register is ready. */
462 bool isReadySrcRegIdx(int idx) const
463 {
464 return this->_readySrcRegIdx[idx];
465 }
466
467 /** Sets this instruction as completed. */
468 void setCompleted() { completed = true; }
469
470 /** Returns whether or not this instruction is completed. */
471 bool isCompleted() const { return completed; }
472
473 void setResultReady() { resultReady = true; }
474
475 bool isResultReady() const { return resultReady; }
476
477 /** Sets this instruction as ready to issue. */
478 void setCanIssue() { canIssue = true; }
479
480 /** Returns whether or not this instruction is ready to issue. */
481 bool readyToIssue() const { return canIssue; }
482
483 /** Sets this instruction as issued from the IQ. */
484 void setIssued() { issued = true; }
485
486 /** Returns whether or not this instruction has issued. */
487 bool isIssued() const { return issued; }
488
489 /** Sets this instruction as executed. */
490 void setExecuted() { executed = true; }
491
492 /** Returns whether or not this instruction has executed. */
493 bool isExecuted() const { return executed; }
494
495 /** Sets this instruction as ready to commit. */
496 void setCanCommit() { canCommit = true; }
497
498 /** Clears this instruction as being ready to commit. */
499 void clearCanCommit() { canCommit = false; }
500
501 /** Returns whether or not this instruction is ready to commit. */
502 bool readyToCommit() const { return canCommit; }
503
504 /** Sets this instruction as committed. */
505 void setCommitted() { committed = true; }
506
507 /** Returns whether or not this instruction is committed. */
508 bool isCommitted() const { return committed; }
509
510 /** Sets this instruction as squashed. */
511 void setSquashed() { squashed = true; }
512
513 /** Returns whether or not this instruction is squashed. */
514 bool isSquashed() const { return squashed; }
515
516 //Instruction Queue Entry
517 //-----------------------
518 /** Sets this instruction as a entry the IQ. */
519 void setInIQ() { iqEntry = true; }
520
521 /** Sets this instruction as a entry the IQ. */
522 void removeInIQ() { iqEntry = false; }
523
524 /** Sets this instruction as squashed in the IQ. */
525 void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
526
527 /** Returns whether or not this instruction is squashed in the IQ. */
528 bool isSquashedInIQ() const { return squashedInIQ; }
529
530 /** Returns whether or not this instruction has issued. */
531 bool isInIQ() const { return iqEntry; }
532
533
534 //Load / Store Queue Functions
535 //-----------------------
536 /** Sets this instruction as a entry the LSQ. */
537 void setInLSQ() { lsqEntry = true; }
538
539 /** Sets this instruction as a entry the LSQ. */
540 void removeInLSQ() { lsqEntry = false; }
541
542 /** Sets this instruction as squashed in the LSQ. */
543 void setSquashedInLSQ() { squashedInLSQ = true;}
544
545 /** Returns whether or not this instruction is squashed in the LSQ. */
546 bool isSquashedInLSQ() const { return squashedInLSQ; }
547
548 /** Returns whether or not this instruction is in the LSQ. */
549 bool isInLSQ() const { return lsqEntry; }
550
551
552 //Reorder Buffer Functions
553 //-----------------------
554 /** Sets this instruction as a entry the ROB. */
555 void setInROB() { robEntry = true; }
556
557 /** Sets this instruction as a entry the ROB. */
558 void removeInROB() { robEntry = false; }
559
560 /** Sets this instruction as squashed in the ROB. */
561 void setSquashedInROB() { squashedInROB = true; }
562
563 /** Returns whether or not this instruction is squashed in the ROB. */
564 bool isSquashedInROB() const { return squashedInROB; }
565
566 /** Returns whether or not this instruction is in the ROB. */
567 bool isInROB() const { return robEntry; }
568
569 /** Read the PC of this instruction. */
570 const Addr readPC() const { return PC; }
571
572 /** Set the next PC of this instruction (its actual target). */
573 void setNextPC(uint64_t val)
574 {
575 nextPC = val;
576 }
577
578 /** Sets the ASID. */
579 void setASID(short addr_space_id) { asid = addr_space_id; }
580
581 /** Sets the thread id. */
582 void setTid(unsigned tid) { threadNumber = tid; }
583
584 void setThreadState(ImplState *state) { thread = state; }
585
586 /** Returns the thread context.
587 */
588 ThreadContext *tcBase() { return thread->getTC(); }
589
590 private:
591 /** Instruction effective address.
592 * @todo: Consider if this is necessary or not.
593 */
594 Addr instEffAddr;
595

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616
617 public:
618 /** Load queue index. */
619 int16_t lqIdx;
620
621 /** Store queue index. */
622 int16_t sqIdx;
623
624 bool reachedCommit;
625
626 /** Iterator pointing to this BaseDynInst in the list of all insts. */
627 ListIt instListIt;
628
629 /** Returns iterator to this instruction in the list of all insts. */
630 ListIt &getInstListIt() { return instListIt; }
631
632 /** Sets iterator for this instruction in the list of all insts. */
633 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }

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