1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 68 unchanged lines hidden (view full) ---

77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80 public:
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87
88 // The DynInstPtr type.
89 typedef typename Impl::DynInstPtr DynInstPtr;
90 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
91
92 // The list of instructions iterator type.
93 typedef typename std::list<DynInstPtr>::iterator ListIt;
94
95 enum {

--- 164 unchanged lines hidden (view full) ---

260 * @todo: Consider if this is necessary or not.
261 */
262 Addr instEffAddr;
263
264 protected:
265 /** Flattened register index of the destination registers of this
266 * instruction.
267 */
268 std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx;
269
270 /** Physical register index of the destination registers of this
271 * instruction.
272 */
273 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx;
274
275 /** Physical register index of the source registers of this
276 * instruction.

--- 104 unchanged lines hidden (view full) ---

381 {
382 assert(TheISA::MaxInstSrcRegs > idx);
383 return _srcRegIdx[idx];
384 }
385
386 /** Returns the flattened register index of the i'th destination
387 * register.
388 */
389 TheISA::RegIndex flattenedDestRegIdx(int idx) const
390 {
391 return _flatDestRegIdx[idx];
392 }
393
394 /** Returns the physical register index of the previous physical register
395 * that remapped to the same logical register index.
396 */
397 PhysRegIndex prevDestRegIdx(int idx) const

--- 19 unchanged lines hidden (view full) ---

417 void renameSrcReg(int idx, PhysRegIndex renamed_src)
418 {
419 _srcRegIdx[idx] = renamed_src;
420 }
421
422 /** Flattens a destination architectural register index into a logical
423 * index.
424 */
425 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
426 {
427 _flatDestRegIdx[idx] = flattened_dest;
428 }
429 /** BaseDynInst constructor given a binary instruction.
430 * @param staticInst A StaticInstPtr to the underlying instruction.
431 * @param pc The PC state for the instruction.
432 * @param predPC The predicted next PC state for the instruction.
433 * @param seq_num The sequence number of the instruction.

--- 165 unchanged lines hidden (view full) ---

599
600 // the following are used to track physical register usage
601 // for machines with separate int & FP reg files
602 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
603 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
604 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
605
606 /** Returns the logical register index of the i'th destination register. */
607 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
608
609 /** Returns the logical register index of the i'th source register. */
610 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
611
612 /** Pops a result off the instResult queue */
613 template <class T>
614 void popResult(T& t)
615 {
616 if (!instResult.empty()) {
617 instResult.front().get(t);
618 instResult.pop();

--- 465 unchanged lines hidden ---