1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 201 unchanged lines hidden (view full) ---

210 uint8_t readyRegs;
211
212 public:
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
215 Addr effAddr;
216
217 /** The effective physical address. */
218 Addr physEffAddr;
219
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
222
223 /** data address space ID, for loads & stores. */
224 short asid;
225
226 /** The size of the request */
227 uint8_t effSize;

--- 823 unchanged lines hidden (view full) ---

1051inline void
1052BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1053{
1054 fault = state->getFault();
1055
1056 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1057
1058 if (fault == NoFault) {
1059 physEffAddr = state->getPaddr();
1060 memReqFlags = state->getFlags();
1061
1062 if (state->mainReq->isCondSwap()) {
1063 assert(state->res);
1064 state->mainReq->setExtraData(*state->res);
1065 }
1066
1067 } else {
1068 state->deleteReqs();
1069 }
1070 delete state;
1071
1072 translationCompleted(true);
1073}
1074
1075#endif // __CPU_BASE_DYN_INST_HH__