1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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912 if (fault != NoFault) {
913 // Return a fixed value to keep simulation deterministic even
914 // along misspeculated paths.
915 if (data)
916 bzero(data, size);
917 }
918 }
919
920 if (traceData) {
921 traceData->setAddr(addr);
922 }
923
924 return fault;
925}
926
927template<class Impl>
928Fault
929BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
930 Addr addr, unsigned flags, uint64_t *res)
931{
932 if (traceData) {
933 traceData->setAddr(addr);
934 }
935
936 instFlags[ReqMade] = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (instFlags[ReqMade] && translationStarted()) {
942 req = savedReq;

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