1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Timothy M. Jones
43 */
44
45#ifndef __CPU_BASE_DYN_INST_HH__
46#define __CPU_BASE_DYN_INST_HH__
47
48#include <bitset>
49#include <list>
50#include <string>
51#include <queue>
52
53#include "arch/utility.hh"
54#include "base/fast_alloc.hh"
55#include "base/trace.hh"
56#include "config/the_isa.hh"
57#include "cpu/checker/cpu.hh"
58#include "cpu/o3/comm.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/inst_seq.hh"
61#include "cpu/op_class.hh"
62#include "cpu/static_inst.hh"
63#include "cpu/translation.hh"
64#include "mem/packet.hh"
65#include "sim/byteswap.hh"
66#include "sim/fault_fwd.hh"
67#include "sim/system.hh"
68#include "sim/tlb.hh"
69
70/**
71 * @file
72 * Defines a dynamic instruction context.
73 */
74
75template <class Impl>
76class BaseDynInst : public FastAlloc, public RefCounted
77{
78 public:
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
82
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
89
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
96
97 enum {
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
100 };
101
102 /** The StaticInst used by this BaseDynInst. */
103 StaticInstPtr staticInst;
104 StaticInstPtr macroop;
105
106 ////////////////////////////////////////////
107 //
108 // INSTRUCTION EXECUTION
109 //
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
113
114 void demapPage(Addr vaddr, uint64_t asn)
115 {
116 cpu->demapPage(vaddr, asn);
117 }
118 void demapInstPage(Addr vaddr, uint64_t asn)
119 {
120 cpu->demapPage(vaddr, asn);
121 }
122 void demapDataPage(Addr vaddr, uint64_t asn)
123 {
124 cpu->demapPage(vaddr, asn);
125 }
126
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
131
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
135
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,
139 BaseTLB::Mode mode);
140
141 /** Finish a DTB address translation. */
142 void finishTranslation(WholeTranslationState *state);
143
144 /** True if the DTB address translation has started. */
145 bool translationStarted;
146
147 /** True if the DTB address translation has completed. */
148 bool translationCompleted;
149
150 /** True if this address was found to match a previous load and they issued
151 * out of order. If that happend, then it's only a problem if an incoming
152 * snoop invalidate modifies the line, in which case we need to squash.
153 * If nothing modified the line the order doesn't matter.
154 */
155 bool possibleLoadViolation;
156
157 /** True if the address hit a external snoop while sitting in the LSQ.
158 * If this is true and a older instruction sees it, this instruction must
159 * reexecute
160 */
161 bool hitExternalSnoop;
162
163 /**
164 * Returns true if the DTB address translation is being delayed due to a hw
165 * page table walk.
166 */
167 bool isTranslationDelayed() const
168 {
169 return (translationStarted && !translationCompleted);
170 }
171
172 /**
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
175 */
176 RequestPtr savedReq;
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
179
180 // Need a copy of main request pointer to verify on writes.
181 RequestPtr reqToVerify;
182
183 /** @todo: Consider making this private. */
184 public:
185 /** The sequence number of the instruction. */
186 InstSeqNum seqNum;
187
188 enum Status {
189 IqEntry, /// Instruction is in the IQ
190 RobEntry, /// Instruction is in the ROB
191 LsqEntry, /// Instruction is in the LSQ
192 Completed, /// Instruction has completed
193 ResultReady, /// Instruction has its result
194 CanIssue, /// Instruction can issue and execute
195 Issued, /// Instruction has issued
196 Executed, /// Instruction has executed
197 CanCommit, /// Instruction can commit
198 AtCommit, /// Instruction has reached commit
199 Committed, /// Instruction has committed
200 Squashed, /// Instruction is squashed
201 SquashedInIQ, /// Instruction is squashed in the IQ
202 SquashedInLSQ, /// Instruction is squashed in the LSQ
203 SquashedInROB, /// Instruction is squashed in the ROB
204 RecoverInst, /// Is a recover instruction
205 BlockingInst, /// Is a blocking instruction
206 ThreadsyncWait, /// Is a thread synchronization instruction
207 SerializeBefore, /// Needs to serialize on
208 /// instructions ahead of it
209 SerializeAfter, /// Needs to serialize instructions behind it
210 SerializeHandled, /// Serialization has been handled
211 NumStatus
212 };
213
214 /** The status of this BaseDynInst. Several bits can be set. */
215 std::bitset<NumStatus> status;
216
217 /** The thread this instruction is from. */
218 ThreadID threadNumber;
219
220 /** data address space ID, for loads & stores. */
221 short asid;
222
223 /** How many source registers are ready. */
224 unsigned readyRegs;
225
226 /** Pointer to the Impl's CPU object. */
227 ImplCPU *cpu;
228
229 /** Pointer to the thread state. */
230 ImplState *thread;
231
232 /** The kind of fault this instruction has generated. */
233 Fault fault;
234
235 /** Pointer to the data for the memory access. */
236 uint8_t *memData;
237
238 /** The effective virtual address (lds & stores only). */
239 Addr effAddr;
240
241 /** The size of the request */
242 Addr effSize;
243
244 /** Is the effective virtual address valid. */
245 bool effAddrValid;
246
247 /** The effective physical address. */
248 Addr physEffAddr;
249
250 /** The memory request flags (from translation). */
251 unsigned memReqFlags;
252
253 union Result {
254 uint64_t integer;
255 double dbl;
256 void set(uint64_t i) { integer = i; }
257 void set(double d) { dbl = d; }
258 void get(uint64_t& i) { i = integer; }
259 void get(double& d) { d = dbl; }
260 };
261
262 /** The result of the instruction; assumes an instruction can have many
263 * destination registers.
264 */
265 std::queue<Result> instResult;
266
267 /** Records changes to result? */
268 bool recordResult;
269
270 /** Did this instruction execute, or is it predicated false */
271 bool predicate;
272
273 protected:
274 /** PC state for this instruction. */
275 TheISA::PCState pc;
276
277 /** Predicted PC state after this instruction. */
278 TheISA::PCState predPC;
279
280 /** If this is a branch that was predicted taken */
281 bool predTaken;
282
283 public:
284
285#ifdef DEBUG
286 void dumpSNList();
287#endif
288
289 /** Whether or not the source register is ready.
290 * @todo: Not sure this should be here vs the derived class.
291 */
292 bool _readySrcRegIdx[MaxInstSrcRegs];
293
294 protected:
295 /** Flattened register index of the destination registers of this
296 * instruction.
297 */
298 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
299
300 /** Flattened register index of the source registers of this
301 * instruction.
302 */
303 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
304
305 /** Physical register index of the destination registers of this
306 * instruction.
307 */
308 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
309
310 /** Physical register index of the source registers of this
311 * instruction.
312 */
313 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
314
315 /** Physical register index of the previous producers of the
316 * architected destinations.
317 */
318 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
319
320 public:
321
322 /** Returns the physical register index of the i'th destination
323 * register.
324 */
325 PhysRegIndex renamedDestRegIdx(int idx) const
326 {
327 return _destRegIdx[idx];
328 }
329
330 /** Returns the physical register index of the i'th source register. */
331 PhysRegIndex renamedSrcRegIdx(int idx) const
332 {
333 return _srcRegIdx[idx];
334 }
335
336 /** Returns the flattened register index of the i'th destination
337 * register.
338 */
339 TheISA::RegIndex flattenedDestRegIdx(int idx) const
340 {
341 return _flatDestRegIdx[idx];
342 }
343
344 /** Returns the flattened register index of the i'th source register */
345 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
346 {
347 return _flatSrcRegIdx[idx];
348 }
349
350 /** Returns the physical register index of the previous physical register
351 * that remapped to the same logical register index.
352 */
353 PhysRegIndex prevDestRegIdx(int idx) const
354 {
355 return _prevDestRegIdx[idx];
356 }
357
358 /** Renames a destination register to a physical register. Also records
359 * the previous physical register that the logical register mapped to.
360 */
361 void renameDestReg(int idx,
362 PhysRegIndex renamed_dest,
363 PhysRegIndex previous_rename)
364 {
365 _destRegIdx[idx] = renamed_dest;
366 _prevDestRegIdx[idx] = previous_rename;
367 }
368
369 /** Renames a source logical register to the physical register which
370 * has/will produce that logical register's result.
371 * @todo: add in whether or not the source register is ready.
372 */
373 void renameSrcReg(int idx, PhysRegIndex renamed_src)
374 {
375 _srcRegIdx[idx] = renamed_src;
376 }
377
378 /** Flattens a source architectural register index into a logical index.
379 */
380 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
381 {
382 _flatSrcRegIdx[idx] = flattened_src;
383 }
384
385 /** Flattens a destination architectural register index into a logical
386 * index.
387 */
388 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
389 {
390 _flatDestRegIdx[idx] = flattened_dest;
391 }
392 /** BaseDynInst constructor given a binary instruction.
393 * @param staticInst A StaticInstPtr to the underlying instruction.
394 * @param pc The PC state for the instruction.
395 * @param predPC The predicted next PC state for the instruction.
396 * @param seq_num The sequence number of the instruction.
397 * @param cpu Pointer to the instruction's CPU.
398 */
399 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
400 TheISA::PCState pc, TheISA::PCState predPC,
401 InstSeqNum seq_num, ImplCPU *cpu);
402
403 /** BaseDynInst constructor given a StaticInst pointer.
404 * @param _staticInst The StaticInst for this BaseDynInst.
405 */
406 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
407
408 /** BaseDynInst destructor. */
409 ~BaseDynInst();
410
411 private:
412 /** Function to initialize variables in the constructors. */
413 void initVars();
414
415 public:
416 /** Dumps out contents of this BaseDynInst. */
417 void dump();
418
419 /** Dumps out contents of this BaseDynInst into given string. */
420 void dump(std::string &outstring);
421
422 /** Read this CPU's ID. */
423 int cpuId() { return cpu->cpuId(); }
424
425 /** Read this CPU's data requestor ID */
426 MasterID masterId() { return cpu->dataMasterId(); }
427
428 /** Read this context's system-wide ID **/
429 int contextId() { return thread->contextId(); }
430
431 /** Returns the fault type. */
432 Fault getFault() { return fault; }
433
434 /** Checks whether or not this instruction has had its branch target
435 * calculated yet. For now it is not utilized and is hacked to be
436 * always false.
437 * @todo: Actually use this instruction.
438 */
439 bool doneTargCalc() { return false; }
440
441 /** Set the predicted target of this current instruction. */
442 void setPredTarg(const TheISA::PCState &_predPC)
443 {
444 predPC = _predPC;
445 }
446
447 const TheISA::PCState &readPredTarg() { return predPC; }
448
449 /** Returns the predicted PC immediately after the branch. */
450 Addr predInstAddr() { return predPC.instAddr(); }
451
452 /** Returns the predicted PC two instructions after the branch */
453 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
454
455 /** Returns the predicted micro PC after the branch */
456 Addr predMicroPC() { return predPC.microPC(); }
457
458 /** Returns whether the instruction was predicted taken or not. */
459 bool readPredTaken()
460 {
461 return predTaken;
462 }
463
464 void setPredTaken(bool predicted_taken)
465 {
466 predTaken = predicted_taken;
467 }
468
469 /** Returns whether the instruction mispredicted. */
470 bool mispredicted()
471 {
472 TheISA::PCState tempPC = pc;
473 TheISA::advancePC(tempPC, staticInst);
474 return !(tempPC == predPC);
475 }
476
477 //
478 // Instruction types. Forward checks to StaticInst object.
479 //
480 bool isNop() const { return staticInst->isNop(); }
481 bool isMemRef() const { return staticInst->isMemRef(); }
482 bool isLoad() const { return staticInst->isLoad(); }
483 bool isStore() const { return staticInst->isStore(); }
484 bool isStoreConditional() const
485 { return staticInst->isStoreConditional(); }
486 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
487 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
488 bool isInteger() const { return staticInst->isInteger(); }
489 bool isFloating() const { return staticInst->isFloating(); }
490 bool isControl() const { return staticInst->isControl(); }
491 bool isCall() const { return staticInst->isCall(); }
492 bool isReturn() const { return staticInst->isReturn(); }
493 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
494 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
495 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
496 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
497 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
498 bool isThreadSync() const { return staticInst->isThreadSync(); }
499 bool isSerializing() const { return staticInst->isSerializing(); }
500 bool isSerializeBefore() const
501 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
502 bool isSerializeAfter() const
503 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
504 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
505 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
506 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
507 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
508 bool isQuiesce() const { return staticInst->isQuiesce(); }
509 bool isIprAccess() const { return staticInst->isIprAccess(); }
510 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
511 bool isSyscall() const { return staticInst->isSyscall(); }
512 bool isMacroop() const { return staticInst->isMacroop(); }
513 bool isMicroop() const { return staticInst->isMicroop(); }
514 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
515 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
516 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
517 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
518
519 /** Temporarily sets this instruction as a serialize before instruction. */
520 void setSerializeBefore() { status.set(SerializeBefore); }
521
522 /** Clears the serializeBefore part of this instruction. */
523 void clearSerializeBefore() { status.reset(SerializeBefore); }
524
525 /** Checks if this serializeBefore is only temporarily set. */
526 bool isTempSerializeBefore() { return status[SerializeBefore]; }
527
528 /** Temporarily sets this instruction as a serialize after instruction. */
529 void setSerializeAfter() { status.set(SerializeAfter); }
530
531 /** Clears the serializeAfter part of this instruction.*/
532 void clearSerializeAfter() { status.reset(SerializeAfter); }
533
534 /** Checks if this serializeAfter is only temporarily set. */
535 bool isTempSerializeAfter() { return status[SerializeAfter]; }
536
537 /** Sets the serialization part of this instruction as handled. */
538 void setSerializeHandled() { status.set(SerializeHandled); }
539
540 /** Checks if the serialization part of this instruction has been
541 * handled. This does not apply to the temporary serializing
542 * state; it only applies to this instruction's own permanent
543 * serializing state.
544 */
545 bool isSerializeHandled() { return status[SerializeHandled]; }
546
547 /** Returns the opclass of this instruction. */
548 OpClass opClass() const { return staticInst->opClass(); }
549
550 /** Returns the branch target address. */
551 TheISA::PCState branchTarget() const
552 { return staticInst->branchTarget(pc); }
553
554 /** Returns the number of source registers. */
555 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
556
557 /** Returns the number of destination registers. */
558 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
559
560 // the following are used to track physical register usage
561 // for machines with separate int & FP reg files
562 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
563 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
564
565 /** Returns the logical register index of the i'th destination register. */
566 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
567
568 /** Returns the logical register index of the i'th source register. */
569 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
570
571 /** Pops a result off the instResult queue */
572 template <class T>
573 void popResult(T& t)
574 {
575 if (!instResult.empty()) {
576 instResult.front().get(t);
577 instResult.pop();
578 }
579 }
580
581 /** Read the most recent result stored by this instruction */
582 template <class T>
583 void readResult(T& t)
584 {
585 instResult.back().get(t);
586 }
587
588 /** Pushes a result onto the instResult queue */
589 template <class T>
590 void setResult(T t)
591 {
592 if (recordResult) {
593 Result instRes;
594 instRes.set(t);
595 instResult.push(instRes);
596 }
597 }
598
599 /** Records an integer register being set to a value. */
600 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
601 {
602 setResult<uint64_t>(val);
603 }
604
605 /** Records an fp register being set to a value. */
606 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
607 int width)
608 {
609 if (width == 32 || width == 64) {
610 setResult<double>(val);
611 } else {
612 panic("Unsupported width!");
613 }
614 }
615
616 /** Records an fp register being set to a value. */
617 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
618 {
619 setResult<double>(val);
620 }
621
622 /** Records an fp register being set to an integer value. */
623 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
624 int width)
625 {
626 setResult<uint64_t>(val);
627 }
628
629 /** Records an fp register being set to an integer value. */
630 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
631 {
632 setResult<uint64_t>(val);
633 }
634
635 /** Records that one of the source registers is ready. */
636 void markSrcRegReady();
637
638 /** Marks a specific register as ready. */
639 void markSrcRegReady(RegIndex src_idx);
640
641 /** Returns if a source register is ready. */
642 bool isReadySrcRegIdx(int idx) const
643 {
644 return this->_readySrcRegIdx[idx];
645 }
646
647 /** Sets this instruction as completed. */
648 void setCompleted() { status.set(Completed); }
649
650 /** Returns whether or not this instruction is completed. */
651 bool isCompleted() const { return status[Completed]; }
652
653 /** Marks the result as ready. */
654 void setResultReady() { status.set(ResultReady); }
655
656 /** Returns whether or not the result is ready. */
657 bool isResultReady() const { return status[ResultReady]; }
658
659 /** Sets this instruction as ready to issue. */
660 void setCanIssue() { status.set(CanIssue); }
661
662 /** Returns whether or not this instruction is ready to issue. */
663 bool readyToIssue() const { return status[CanIssue]; }
664
665 /** Clears this instruction being able to issue. */
666 void clearCanIssue() { status.reset(CanIssue); }
667
668 /** Sets this instruction as issued from the IQ. */
669 void setIssued() { status.set(Issued); }
670
671 /** Returns whether or not this instruction has issued. */
672 bool isIssued() const { return status[Issued]; }
673
674 /** Clears this instruction as being issued. */
675 void clearIssued() { status.reset(Issued); }
676
677 /** Sets this instruction as executed. */
678 void setExecuted() { status.set(Executed); }
679
680 /** Returns whether or not this instruction has executed. */
681 bool isExecuted() const { return status[Executed]; }
682
683 /** Sets this instruction as ready to commit. */
684 void setCanCommit() { status.set(CanCommit); }
685
686 /** Clears this instruction as being ready to commit. */
687 void clearCanCommit() { status.reset(CanCommit); }
688
689 /** Returns whether or not this instruction is ready to commit. */
690 bool readyToCommit() const { return status[CanCommit]; }
691
692 void setAtCommit() { status.set(AtCommit); }
693
694 bool isAtCommit() { return status[AtCommit]; }
695
696 /** Sets this instruction as committed. */
697 void setCommitted() { status.set(Committed); }
698
699 /** Returns whether or not this instruction is committed. */
700 bool isCommitted() const { return status[Committed]; }
701
702 /** Sets this instruction as squashed. */
703 void setSquashed() { status.set(Squashed); }
704
705 /** Returns whether or not this instruction is squashed. */
706 bool isSquashed() const { return status[Squashed]; }
707
708 //Instruction Queue Entry
709 //-----------------------
710 /** Sets this instruction as a entry the IQ. */
711 void setInIQ() { status.set(IqEntry); }
712
713 /** Sets this instruction as a entry the IQ. */
714 void clearInIQ() { status.reset(IqEntry); }
715
716 /** Returns whether or not this instruction has issued. */
717 bool isInIQ() const { return status[IqEntry]; }
718
719 /** Sets this instruction as squashed in the IQ. */
720 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
721
722 /** Returns whether or not this instruction is squashed in the IQ. */
723 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
724
725
726 //Load / Store Queue Functions
727 //-----------------------
728 /** Sets this instruction as a entry the LSQ. */
729 void setInLSQ() { status.set(LsqEntry); }
730
731 /** Sets this instruction as a entry the LSQ. */
732 void removeInLSQ() { status.reset(LsqEntry); }
733
734 /** Returns whether or not this instruction is in the LSQ. */
735 bool isInLSQ() const { return status[LsqEntry]; }
736
737 /** Sets this instruction as squashed in the LSQ. */
738 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
739
740 /** Returns whether or not this instruction is squashed in the LSQ. */
741 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
742
743
744 //Reorder Buffer Functions
745 //-----------------------
746 /** Sets this instruction as a entry the ROB. */
747 void setInROB() { status.set(RobEntry); }
748
749 /** Sets this instruction as a entry the ROB. */
750 void clearInROB() { status.reset(RobEntry); }
751
752 /** Returns whether or not this instruction is in the ROB. */
753 bool isInROB() const { return status[RobEntry]; }
754
755 /** Sets this instruction as squashed in the ROB. */
756 void setSquashedInROB() { status.set(SquashedInROB); }
757
758 /** Returns whether or not this instruction is squashed in the ROB. */
759 bool isSquashedInROB() const { return status[SquashedInROB]; }
760
761 /** Read the PC state of this instruction. */
762 const TheISA::PCState pcState() const { return pc; }
763
764 /** Set the PC state of this instruction. */
765 const void pcState(const TheISA::PCState &val) { pc = val; }
766
767 /** Read the PC of this instruction. */
768 const Addr instAddr() const { return pc.instAddr(); }
769
770 /** Read the PC of the next instruction. */
771 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
772
773 /**Read the micro PC of this instruction. */
774 const Addr microPC() const { return pc.microPC(); }
775
776 bool readPredicate()
777 {
778 return predicate;
779 }
780
781 void setPredicate(bool val)
782 {
783 predicate = val;
784
785 if (traceData) {
786 traceData->setPredicate(val);
787 }
788 }
789
790 /** Sets the ASID. */
791 void setASID(short addr_space_id) { asid = addr_space_id; }
792
793 /** Sets the thread id. */
794 void setTid(ThreadID tid) { threadNumber = tid; }
795
796 /** Sets the pointer to the thread state. */
797 void setThreadState(ImplState *state) { thread = state; }
798
799 /** Returns the thread context. */
800 ThreadContext *tcBase() { return thread->getTC(); }
801
802 private:
803 /** Instruction effective address.
804 * @todo: Consider if this is necessary or not.
805 */
806 Addr instEffAddr;
807
808 /** Whether or not the effective address calculation is completed.
809 * @todo: Consider if this is necessary or not.
810 */
811 bool eaCalcDone;
812
813 /** Is this instruction's memory access uncacheable. */
814 bool isUncacheable;
815
816 /** Has this instruction generated a memory request. */
817 bool reqMade;
818
819 public:
820 /** Sets the effective address. */
821 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
822
823 /** Returns the effective address. */
824 const Addr &getEA() const { return instEffAddr; }
825
826 /** Returns whether or not the eff. addr. calculation has been completed. */
827 bool doneEACalc() { return eaCalcDone; }
828
829 /** Returns whether or not the eff. addr. source registers are ready. */
830 bool eaSrcsReady();
831
832 /** Whether or not the memory operation is done. */
833 bool memOpDone;
834
835 /** Is this instruction's memory access uncacheable. */
836 bool uncacheable() { return isUncacheable; }
837
838 /** Has this instruction generated a memory request. */
839 bool hasRequest() { return reqMade; }
840
841 public:
842 /** Load queue index. */
843 int16_t lqIdx;
844
845 /** Store queue index. */
846 int16_t sqIdx;
847
848 /** Iterator pointing to this BaseDynInst in the list of all insts. */
849 ListIt instListIt;
850
851 /** Returns iterator to this instruction in the list of all insts. */
852 ListIt &getInstListIt() { return instListIt; }
853
854 /** Sets iterator for this instruction in the list of all insts. */
855 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
856
857 public:
858 /** Returns the number of consecutive store conditional failures. */
859 unsigned readStCondFailures()
860 { return thread->storeCondFailures; }
861
862 /** Sets the number of consecutive store conditional failures. */
863 void setStCondFailures(unsigned sc_failures)
864 { thread->storeCondFailures = sc_failures; }
865};
866
867template<class Impl>
868Fault
869BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
870 unsigned size, unsigned flags)
871{
872 reqMade = true;
873 Request *req = NULL;
874 Request *sreqLow = NULL;
875 Request *sreqHigh = NULL;
876
877 if (reqMade && translationStarted) {
878 req = savedReq;
879 sreqLow = savedSreqLow;
880 sreqHigh = savedSreqHigh;
881 } else {
882 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
883 thread->contextId(), threadNumber);
884
885 // Only split the request if the ISA supports unaligned accesses.
886 if (TheISA::HasUnalignedMemAcc) {
887 splitRequest(req, sreqLow, sreqHigh);
888 }
889 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
890 }
891
892 if (translationCompleted) {
893 if (fault == NoFault) {
894 effAddr = req->getVaddr();
895 effSize = size;
896 effAddrValid = true;
897
898 if (cpu->checker) {
899 if (reqToVerify != NULL) {
900 delete reqToVerify;
901 }
902 reqToVerify = new Request(*req);
903 }
904 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
905 } else {
906 // Commit will have to clean up whatever happened. Set this
907 // instruction as executed.
908 this->setExecuted();
909 }
910
911 if (fault != NoFault) {
912 // Return a fixed value to keep simulation deterministic even
913 // along misspeculated paths.
914 if (data)
915 bzero(data, size);
916 }
917 }
918
919 if (traceData) {
920 traceData->setAddr(addr);
921 }
922
923 return fault;
924}
925
926template<class Impl>
927Fault
928BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
929 Addr addr, unsigned flags, uint64_t *res)
930{
931 if (traceData) {
932 traceData->setAddr(addr);
933 }
934
935 reqMade = true;
936 Request *req = NULL;
937 Request *sreqLow = NULL;
938 Request *sreqHigh = NULL;
939
940 if (reqMade && translationStarted) {
941 req = savedReq;
942 sreqLow = savedSreqLow;
943 sreqHigh = savedSreqHigh;
944 } else {
945 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
946 thread->contextId(), threadNumber);
947
948 // Only split the request if the ISA supports unaligned accesses.
949 if (TheISA::HasUnalignedMemAcc) {
950 splitRequest(req, sreqLow, sreqHigh);
951 }
952 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
953 }
954
955 if (fault == NoFault && translationCompleted) {
956 effAddr = req->getVaddr();
957 effSize = size;
958 effAddrValid = true;
959
960 if (cpu->checker) {
961 if (reqToVerify != NULL) {
962 delete reqToVerify;
963 }
964 reqToVerify = new Request(*req);
965 }
966 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
967 }
968
969 return fault;
970}
971
972template<class Impl>
973inline void
974BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
975 RequestPtr &sreqHigh)
976{
977 // Check to see if the request crosses the next level block boundary.
978 unsigned block_size = cpu->getDataPort().peerBlockSize();
979 Addr addr = req->getVaddr();
980 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
981 assert(split_addr <= addr || split_addr - addr < block_size);
982
983 // Spans two blocks.
984 if (split_addr > addr) {
985 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
986 }
987}
988
989template<class Impl>
990inline void
991BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
992 RequestPtr sreqHigh, uint64_t *res,
993 BaseTLB::Mode mode)
994{
995 translationStarted = true;
996
997 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
998 WholeTranslationState *state =
999 new WholeTranslationState(req, NULL, res, mode);
1000
1001 // One translation if the request isn't split.
1002 DataTranslation<BaseDynInstPtr> *trans =
1003 new DataTranslation<BaseDynInstPtr>(this, state);
1004 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1005 if (!translationCompleted) {
1006 // Save memory requests.
1007 savedReq = state->mainReq;
1008 savedSreqLow = state->sreqLow;
1009 savedSreqHigh = state->sreqHigh;
1010 }
1011 } else {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1014
1015 // Two translations when the request is split.
1016 DataTranslation<BaseDynInstPtr> *stransLow =
1017 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1018 DataTranslation<BaseDynInstPtr> *stransHigh =
1019 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1020
1021 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1022 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1023 if (!translationCompleted) {
1024 // Save memory requests.
1025 savedReq = state->mainReq;
1026 savedSreqLow = state->sreqLow;
1027 savedSreqHigh = state->sreqHigh;
1028 }
1029 }
1030}
1031
1032template<class Impl>
1033inline void
1034BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1035{
1036 fault = state->getFault();
1037
1038 if (state->isUncacheable())
1039 isUncacheable = true;
1040
1041 if (fault == NoFault) {
1042 physEffAddr = state->getPaddr();
1043 memReqFlags = state->getFlags();
1044
1045 if (state->mainReq->isCondSwap()) {
1046 assert(state->res);
1047 state->mainReq->setExtraData(*state->res);
1048 }
1049
1050 } else {
1051 state->deleteReqs();
1052 }
1053 delete state;
1054
1055 translationCompleted = true;
1056}
1057
1058#endif // __CPU_BASE_DYN_INST_HH__