1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 * Timothy M. Jones
31 */
32
33#ifndef __CPU_BASE_DYN_INST_HH__
34#define __CPU_BASE_DYN_INST_HH__
35
36#include <bitset>
37#include <list>
38#include <string>
39
40#include "arch/faults.hh"
41#include "base/fast_alloc.hh"
42#include "base/trace.hh"
43#include "config/full_system.hh"
44#include "config/the_isa.hh"
45#include "cpu/o3/comm.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/inst_seq.hh"
48#include "cpu/op_class.hh"
49#include "cpu/static_inst.hh"
50#include "cpu/translation.hh"
51#include "mem/packet.hh"
52#include "sim/system.hh"
53#include "sim/tlb.hh"
54
55/**
56 * @file
57 * Defines a dynamic instruction context.
58 */
59
60// Forward declaration.
61class StaticInstPtr;
62
63template <class Impl>
64class BaseDynInst : public FastAlloc, public RefCounted
65{
66 public:
67 // Typedef for the CPU.
68 typedef typename Impl::CPUType ImplCPU;
69 typedef typename ImplCPU::ImplState ImplState;
70
71 // Logical register index type.
72 typedef TheISA::RegIndex RegIndex;
73 // Integer register type.
74 typedef TheISA::IntReg IntReg;
75 // Floating point register type.
76 typedef TheISA::FloatReg FloatReg;
77
78 // The DynInstPtr type.
79 typedef typename Impl::DynInstPtr DynInstPtr;
80
81 // The list of instructions iterator type.
82 typedef typename std::list<DynInstPtr>::iterator ListIt;
83
84 enum {
85 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
86 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
87 };
88
89 /** The StaticInst used by this BaseDynInst. */
90 StaticInstPtr staticInst;
91
92 ////////////////////////////////////////////
93 //
94 // INSTRUCTION EXECUTION
95 //
96 ////////////////////////////////////////////
97 /** InstRecord that tracks this instructions. */
98 Trace::InstRecord *traceData;
99
100 void demapPage(Addr vaddr, uint64_t asn)
101 {
102 cpu->demapPage(vaddr, asn);
103 }
104 void demapInstPage(Addr vaddr, uint64_t asn)
105 {
106 cpu->demapPage(vaddr, asn);
107 }
108 void demapDataPage(Addr vaddr, uint64_t asn)
109 {
110 cpu->demapPage(vaddr, asn);
111 }
112
113 /**
114 * Does a read to a given address.
115 * @param addr The address to read.
116 * @param data The read's data is written into this parameter.
117 * @param flags The request's flags.
118 * @return Returns any fault due to the read.
119 */
120 template <class T>
121 Fault read(Addr addr, T &data, unsigned flags);
122
123 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
124
125 /**
126 * Does a write to a given address.
127 * @param data The data to be written.
128 * @param addr The address to write to.
129 * @param flags The request's flags.
130 * @param res The result of the write (for load locked/store conditionals).
131 * @return Returns any fault due to the write.
132 */
133 template <class T>
134 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
135
136 Fault writeBytes(uint8_t *data, unsigned size,
137 Addr addr, unsigned flags, uint64_t *res);
138
139 /** Splits a request in two if it crosses a dcache block. */
140 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
141 RequestPtr &sreqHigh);
142
143 /** Initiate a DTB address translation. */
144 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
145 RequestPtr sreqHigh, uint64_t *res,
146 BaseTLB::Mode mode);
147
148 /** Finish a DTB address translation. */
149 void finishTranslation(WholeTranslationState *state);
150
151 void prefetch(Addr addr, unsigned flags);
152 void writeHint(Addr addr, int size, unsigned flags);
153 Fault copySrcTranslate(Addr src);
154 Fault copy(Addr dest);
155
156 /** @todo: Consider making this private. */
157 public:
158 /** The sequence number of the instruction. */
159 InstSeqNum seqNum;
160
161 enum Status {
162 IqEntry, /// Instruction is in the IQ
163 RobEntry, /// Instruction is in the ROB
164 LsqEntry, /// Instruction is in the LSQ
165 Completed, /// Instruction has completed
166 ResultReady, /// Instruction has its result
167 CanIssue, /// Instruction can issue and execute
168 Issued, /// Instruction has issued
169 Executed, /// Instruction has executed
170 CanCommit, /// Instruction can commit
171 AtCommit, /// Instruction has reached commit
172 Committed, /// Instruction has committed
173 Squashed, /// Instruction is squashed
174 SquashedInIQ, /// Instruction is squashed in the IQ
175 SquashedInLSQ, /// Instruction is squashed in the LSQ
176 SquashedInROB, /// Instruction is squashed in the ROB
177 RecoverInst, /// Is a recover instruction
178 BlockingInst, /// Is a blocking instruction
179 ThreadsyncWait, /// Is a thread synchronization instruction
180 SerializeBefore, /// Needs to serialize on
181 /// instructions ahead of it
182 SerializeAfter, /// Needs to serialize instructions behind it
183 SerializeHandled, /// Serialization has been handled
184 NumStatus
185 };
186
187 /** The status of this BaseDynInst. Several bits can be set. */
188 std::bitset<NumStatus> status;
189
190 /** The thread this instruction is from. */
191 ThreadID threadNumber;
192
193 /** data address space ID, for loads & stores. */
194 short asid;
195
196 /** How many source registers are ready. */
197 unsigned readyRegs;
198
199 /** Pointer to the Impl's CPU object. */
200 ImplCPU *cpu;
201
202 /** Pointer to the thread state. */
203 ImplState *thread;
204
205 /** The kind of fault this instruction has generated. */
206 Fault fault;
207
208 /** Pointer to the data for the memory access. */
209 uint8_t *memData;
210
211 /** The effective virtual address (lds & stores only). */
212 Addr effAddr;
213
214 /** Is the effective virtual address valid. */
215 bool effAddrValid;
216
217 /** The effective physical address. */
218 Addr physEffAddr;
219
220 /** Effective virtual address for a copy source. */
221 Addr copySrcEffAddr;
222
223 /** Effective physical address for a copy source. */
224 Addr copySrcPhysEffAddr;
225
226 /** The memory request flags (from translation). */
227 unsigned memReqFlags;
228
229 union Result {
230 uint64_t integer;
231// float fp;
232 double dbl;
233 };
234
235 /** The result of the instruction; assumes for now that there's only one
236 * destination register.
237 */
238 Result instResult;
239
240 /** Records changes to result? */
241 bool recordResult;
242
243 /** PC of this instruction. */
244 Addr PC;
245
246 /** Micro PC of this instruction. */
247 Addr microPC;
248
249 /** Did this instruction execute, or is it predicated false */
250 bool predicate;
251
252 protected:
253 /** Next non-speculative PC. It is not filled in at fetch, but rather
254 * once the target of the branch is truly known (either decode or
255 * execute).
256 */
257 Addr nextPC;
258
259 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
260 Addr nextNPC;
261
262 /** Next non-speculative micro PC. */
263 Addr nextMicroPC;
264
265 /** Predicted next PC. */
266 Addr predPC;
267
268 /** Predicted next NPC. */
269 Addr predNPC;
270
271 /** Predicted next microPC */
272 Addr predMicroPC;
273
274 /** If this is a branch that was predicted taken */
275 bool predTaken;
276
277 public:
278
279#ifdef DEBUG
280 void dumpSNList();
281#endif
282
283 /** Whether or not the source register is ready.
284 * @todo: Not sure this should be here vs the derived class.
285 */
286 bool _readySrcRegIdx[MaxInstSrcRegs];
287
288 protected:
289 /** Flattened register index of the destination registers of this
290 * instruction.
291 */
292 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
293
294 /** Flattened register index of the source registers of this
295 * instruction.
296 */
297 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
298
299 /** Physical register index of the destination registers of this
300 * instruction.
301 */
302 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
303
304 /** Physical register index of the source registers of this
305 * instruction.
306 */
307 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
308
309 /** Physical register index of the previous producers of the
310 * architected destinations.
311 */
312 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
313
314 public:
315
316 /** Returns the physical register index of the i'th destination
317 * register.
318 */
319 PhysRegIndex renamedDestRegIdx(int idx) const
320 {
321 return _destRegIdx[idx];
322 }
323
324 /** Returns the physical register index of the i'th source register. */
325 PhysRegIndex renamedSrcRegIdx(int idx) const
326 {
327 return _srcRegIdx[idx];
328 }
329
330 /** Returns the flattened register index of the i'th destination
331 * register.
332 */
333 TheISA::RegIndex flattenedDestRegIdx(int idx) const
334 {
335 return _flatDestRegIdx[idx];
336 }
337
338 /** Returns the flattened register index of the i'th source register */
339 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
340 {
341 return _flatSrcRegIdx[idx];
342 }
343
344 /** Returns the physical register index of the previous physical register
345 * that remapped to the same logical register index.
346 */
347 PhysRegIndex prevDestRegIdx(int idx) const
348 {
349 return _prevDestRegIdx[idx];
350 }
351
352 /** Renames a destination register to a physical register. Also records
353 * the previous physical register that the logical register mapped to.
354 */
355 void renameDestReg(int idx,
356 PhysRegIndex renamed_dest,
357 PhysRegIndex previous_rename)
358 {
359 _destRegIdx[idx] = renamed_dest;
360 _prevDestRegIdx[idx] = previous_rename;
361 }
362
363 /** Renames a source logical register to the physical register which
364 * has/will produce that logical register's result.
365 * @todo: add in whether or not the source register is ready.
366 */
367 void renameSrcReg(int idx, PhysRegIndex renamed_src)
368 {
369 _srcRegIdx[idx] = renamed_src;
370 }
371
372 /** Flattens a source architectural register index into a logical index.
373 */
374 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
375 {
376 _flatSrcRegIdx[idx] = flattened_src;
377 }
378
379 /** Flattens a destination architectural register index into a logical
380 * index.
381 */
382 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
383 {
384 _flatDestRegIdx[idx] = flattened_dest;
385 }
386 /** BaseDynInst constructor given a binary instruction.
387 * @param staticInst A StaticInstPtr to the underlying instruction.
388 * @param PC The PC of the instruction.
389 * @param pred_PC The predicted next PC.
390 * @param pred_NPC The predicted next NPC.
391 * @param seq_num The sequence number of the instruction.
392 * @param cpu Pointer to the instruction's CPU.
393 */
394 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
395 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
396 InstSeqNum seq_num, ImplCPU *cpu);
397
398 /** BaseDynInst constructor given a binary instruction.
399 * @param inst The binary instruction.
400 * @param PC The PC of the instruction.
401 * @param pred_PC The predicted next PC.
402 * @param pred_NPC The predicted next NPC.
403 * @param seq_num The sequence number of the instruction.
404 * @param cpu Pointer to the instruction's CPU.
405 */
406 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
407 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
408 InstSeqNum seq_num, ImplCPU *cpu);
409
410 /** BaseDynInst constructor given a StaticInst pointer.
411 * @param _staticInst The StaticInst for this BaseDynInst.
412 */
413 BaseDynInst(StaticInstPtr &_staticInst);
414
415 /** BaseDynInst destructor. */
416 ~BaseDynInst();
417
418 private:
419 /** Function to initialize variables in the constructors. */
420 void initVars();
421
422 public:
423 /** Dumps out contents of this BaseDynInst. */
424 void dump();
425
426 /** Dumps out contents of this BaseDynInst into given string. */
427 void dump(std::string &outstring);
428
429 /** Read this CPU's ID. */
430 int cpuId() { return cpu->cpuId(); }
431
432 /** Read this context's system-wide ID **/
433 int contextId() { return thread->contextId(); }
434
435 /** Returns the fault type. */
436 Fault getFault() { return fault; }
437
438 /** Checks whether or not this instruction has had its branch target
439 * calculated yet. For now it is not utilized and is hacked to be
440 * always false.
441 * @todo: Actually use this instruction.
442 */
443 bool doneTargCalc() { return false; }
444
445 /** Returns the next PC. This could be the speculative next PC if it is
446 * called prior to the actual branch target being calculated.
447 */
448 Addr readNextPC() { return nextPC; }
449
450 /** Returns the next NPC. This could be the speculative next NPC if it is
451 * called prior to the actual branch target being calculated.
452 */
453 Addr readNextNPC()
454 {
455#if ISA_HAS_DELAY_SLOT
456 return nextNPC;
457#else
458 return nextPC + sizeof(TheISA::MachInst);
459#endif
460 }
461
462 Addr readNextMicroPC()
463 {
464 return nextMicroPC;
465 }
466
467 /** Set the predicted target of this current instruction. */
468 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
469 Addr predicted_MicroPC)
470 {
471 predPC = predicted_PC;
472 predNPC = predicted_NPC;
473 predMicroPC = predicted_MicroPC;
474 }
475
476 /** Returns the predicted PC immediately after the branch. */
477 Addr readPredPC() { return predPC; }
478
479 /** Returns the predicted PC two instructions after the branch */
480 Addr readPredNPC() { return predNPC; }
481
482 /** Returns the predicted micro PC after the branch */
483 Addr readPredMicroPC() { return predMicroPC; }
484
485 /** Returns whether the instruction was predicted taken or not. */
486 bool readPredTaken()
487 {
488 return predTaken;
489 }
490
491 void setPredTaken(bool predicted_taken)
492 {
493 predTaken = predicted_taken;
494 }
495
496 /** Returns whether the instruction mispredicted. */
497 bool mispredicted()
498 {
499 return readPredPC() != readNextPC() ||
500 readPredNPC() != readNextNPC() ||
501 readPredMicroPC() != readNextMicroPC();
502 }
503
504 //
505 // Instruction types. Forward checks to StaticInst object.
506 //
507 bool isNop() const { return staticInst->isNop(); }
508 bool isMemRef() const { return staticInst->isMemRef(); }
509 bool isLoad() const { return staticInst->isLoad(); }
510 bool isStore() const { return staticInst->isStore(); }
511 bool isStoreConditional() const
512 { return staticInst->isStoreConditional(); }
513 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
514 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
515 bool isCopy() const { return staticInst->isCopy(); }
516 bool isInteger() const { return staticInst->isInteger(); }
517 bool isFloating() const { return staticInst->isFloating(); }
518 bool isControl() const { return staticInst->isControl(); }
519 bool isCall() const { return staticInst->isCall(); }
520 bool isReturn() const { return staticInst->isReturn(); }
521 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
522 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
523 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
524 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
525 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
526 bool isThreadSync() const { return staticInst->isThreadSync(); }
527 bool isSerializing() const { return staticInst->isSerializing(); }
528 bool isSerializeBefore() const
529 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
530 bool isSerializeAfter() const
531 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
532 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
533 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
534 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
535 bool isQuiesce() const { return staticInst->isQuiesce(); }
536 bool isIprAccess() const { return staticInst->isIprAccess(); }
537 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
538 bool isSyscall() const { return staticInst->isSyscall(); }
539 bool isMacroop() const { return staticInst->isMacroop(); }
540 bool isMicroop() const { return staticInst->isMicroop(); }
541 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
542 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
543 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
544 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
545
546 /** Temporarily sets this instruction as a serialize before instruction. */
547 void setSerializeBefore() { status.set(SerializeBefore); }
548
549 /** Clears the serializeBefore part of this instruction. */
550 void clearSerializeBefore() { status.reset(SerializeBefore); }
551
552 /** Checks if this serializeBefore is only temporarily set. */
553 bool isTempSerializeBefore() { return status[SerializeBefore]; }
554
555 /** Temporarily sets this instruction as a serialize after instruction. */
556 void setSerializeAfter() { status.set(SerializeAfter); }
557
558 /** Clears the serializeAfter part of this instruction.*/
559 void clearSerializeAfter() { status.reset(SerializeAfter); }
560
561 /** Checks if this serializeAfter is only temporarily set. */
562 bool isTempSerializeAfter() { return status[SerializeAfter]; }
563
564 /** Sets the serialization part of this instruction as handled. */
565 void setSerializeHandled() { status.set(SerializeHandled); }
566
567 /** Checks if the serialization part of this instruction has been
568 * handled. This does not apply to the temporary serializing
569 * state; it only applies to this instruction's own permanent
570 * serializing state.
571 */
572 bool isSerializeHandled() { return status[SerializeHandled]; }
573
574 /** Returns the opclass of this instruction. */
575 OpClass opClass() const { return staticInst->opClass(); }
576
577 /** Returns the branch target address. */
578 Addr branchTarget() const { return staticInst->branchTarget(PC); }
579
580 /** Returns the number of source registers. */
581 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
582
583 /** Returns the number of destination registers. */
584 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
585
586 // the following are used to track physical register usage
587 // for machines with separate int & FP reg files
588 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
589 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
590
591 /** Returns the logical register index of the i'th destination register. */
592 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
593
594 /** Returns the logical register index of the i'th source register. */
595 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
596
597 /** Returns the result of an integer instruction. */
598 uint64_t readIntResult() { return instResult.integer; }
599
600 /** Returns the result of a floating point instruction. */
601 float readFloatResult() { return (float)instResult.dbl; }
602
603 /** Returns the result of a floating point (double) instruction. */
604 double readDoubleResult() { return instResult.dbl; }
605
606 /** Records an integer register being set to a value. */
607 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
608 {
609 if (recordResult)
610 instResult.integer = val;
611 }
612
613 /** Records an fp register being set to a value. */
614 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
615 int width)
616 {
617 if (recordResult) {
618 if (width == 32)
619 instResult.dbl = (double)val;
620 else if (width == 64)
621 instResult.dbl = val;
622 else
623 panic("Unsupported width!");
624 }
625 }
626
627 /** Records an fp register being set to a value. */
628 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
629 {
630 if (recordResult)
631 instResult.dbl = (double)val;
632 }
633
634 /** Records an fp register being set to an integer value. */
635 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
636 int width)
637 {
638 if (recordResult)
639 instResult.integer = val;
640 }
641
642 /** Records an fp register being set to an integer value. */
643 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
644 {
645 if (recordResult)
646 instResult.integer = val;
647 }
648
649 /** Records that one of the source registers is ready. */
650 void markSrcRegReady();
651
652 /** Marks a specific register as ready. */
653 void markSrcRegReady(RegIndex src_idx);
654
655 /** Returns if a source register is ready. */
656 bool isReadySrcRegIdx(int idx) const
657 {
658 return this->_readySrcRegIdx[idx];
659 }
660
661 /** Sets this instruction as completed. */
662 void setCompleted() { status.set(Completed); }
663
664 /** Returns whether or not this instruction is completed. */
665 bool isCompleted() const { return status[Completed]; }
666
667 /** Marks the result as ready. */
668 void setResultReady() { status.set(ResultReady); }
669
670 /** Returns whether or not the result is ready. */
671 bool isResultReady() const { return status[ResultReady]; }
672
673 /** Sets this instruction as ready to issue. */
674 void setCanIssue() { status.set(CanIssue); }
675
676 /** Returns whether or not this instruction is ready to issue. */
677 bool readyToIssue() const { return status[CanIssue]; }
678
679 /** Clears this instruction being able to issue. */
680 void clearCanIssue() { status.reset(CanIssue); }
681
682 /** Sets this instruction as issued from the IQ. */
683 void setIssued() { status.set(Issued); }
684
685 /** Returns whether or not this instruction has issued. */
686 bool isIssued() const { return status[Issued]; }
687
688 /** Clears this instruction as being issued. */
689 void clearIssued() { status.reset(Issued); }
690
691 /** Sets this instruction as executed. */
692 void setExecuted() { status.set(Executed); }
693
694 /** Returns whether or not this instruction has executed. */
695 bool isExecuted() const { return status[Executed]; }
696
697 /** Sets this instruction as ready to commit. */
698 void setCanCommit() { status.set(CanCommit); }
699
700 /** Clears this instruction as being ready to commit. */
701 void clearCanCommit() { status.reset(CanCommit); }
702
703 /** Returns whether or not this instruction is ready to commit. */
704 bool readyToCommit() const { return status[CanCommit]; }
705
706 void setAtCommit() { status.set(AtCommit); }
707
708 bool isAtCommit() { return status[AtCommit]; }
709
710 /** Sets this instruction as committed. */
711 void setCommitted() { status.set(Committed); }
712
713 /** Returns whether or not this instruction is committed. */
714 bool isCommitted() const { return status[Committed]; }
715
716 /** Sets this instruction as squashed. */
717 void setSquashed() { status.set(Squashed); }
718
719 /** Returns whether or not this instruction is squashed. */
720 bool isSquashed() const { return status[Squashed]; }
721
722 //Instruction Queue Entry
723 //-----------------------
724 /** Sets this instruction as a entry the IQ. */
725 void setInIQ() { status.set(IqEntry); }
726
727 /** Sets this instruction as a entry the IQ. */
728 void clearInIQ() { status.reset(IqEntry); }
729
730 /** Returns whether or not this instruction has issued. */
731 bool isInIQ() const { return status[IqEntry]; }
732
733 /** Sets this instruction as squashed in the IQ. */
734 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
735
736 /** Returns whether or not this instruction is squashed in the IQ. */
737 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
738
739
740 //Load / Store Queue Functions
741 //-----------------------
742 /** Sets this instruction as a entry the LSQ. */
743 void setInLSQ() { status.set(LsqEntry); }
744
745 /** Sets this instruction as a entry the LSQ. */
746 void removeInLSQ() { status.reset(LsqEntry); }
747
748 /** Returns whether or not this instruction is in the LSQ. */
749 bool isInLSQ() const { return status[LsqEntry]; }
750
751 /** Sets this instruction as squashed in the LSQ. */
752 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
753
754 /** Returns whether or not this instruction is squashed in the LSQ. */
755 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
756
757
758 //Reorder Buffer Functions
759 //-----------------------
760 /** Sets this instruction as a entry the ROB. */
761 void setInROB() { status.set(RobEntry); }
762
763 /** Sets this instruction as a entry the ROB. */
764 void clearInROB() { status.reset(RobEntry); }
765
766 /** Returns whether or not this instruction is in the ROB. */
767 bool isInROB() const { return status[RobEntry]; }
768
769 /** Sets this instruction as squashed in the ROB. */
770 void setSquashedInROB() { status.set(SquashedInROB); }
771
772 /** Returns whether or not this instruction is squashed in the ROB. */
773 bool isSquashedInROB() const { return status[SquashedInROB]; }
774
775 /** Read the PC of this instruction. */
776 const Addr readPC() const { return PC; }
777
778 /**Read the micro PC of this instruction. */
779 const Addr readMicroPC() const { return microPC; }
780
781 /** Set the next PC of this instruction (its actual target). */
782 void setNextPC(Addr val)
783 {
784 nextPC = val;
785 }
786
787 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
788 void setNextNPC(Addr val)
789 {
790#if ISA_HAS_DELAY_SLOT
791 nextNPC = val;
792#endif
793 }
794
795 void setNextMicroPC(Addr val)
796 {
797 nextMicroPC = val;
798 }
799
800 bool readPredicate()
801 {
802 return predicate;
803 }
804
805 void setPredicate(bool val)
806 {
807 predicate = val;
808
809 if (traceData) {
810 traceData->setPredicate(val);
811 }
812 }
813
814 /** Sets the ASID. */
815 void setASID(short addr_space_id) { asid = addr_space_id; }
816
817 /** Sets the thread id. */
818 void setTid(ThreadID tid) { threadNumber = tid; }
819
820 /** Sets the pointer to the thread state. */
821 void setThreadState(ImplState *state) { thread = state; }
822
823 /** Returns the thread context. */
824 ThreadContext *tcBase() { return thread->getTC(); }
825
826 private:
827 /** Instruction effective address.
828 * @todo: Consider if this is necessary or not.
829 */
830 Addr instEffAddr;
831
832 /** Whether or not the effective address calculation is completed.
833 * @todo: Consider if this is necessary or not.
834 */
835 bool eaCalcDone;
836
837 /** Is this instruction's memory access uncacheable. */
838 bool isUncacheable;
839
840 /** Has this instruction generated a memory request. */
841 bool reqMade;
842
843 public:
844 /** Sets the effective address. */
845 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
846
847 /** Returns the effective address. */
848 const Addr &getEA() const { return instEffAddr; }
849
850 /** Returns whether or not the eff. addr. calculation has been completed. */
851 bool doneEACalc() { return eaCalcDone; }
852
853 /** Returns whether or not the eff. addr. source registers are ready. */
854 bool eaSrcsReady();
855
856 /** Whether or not the memory operation is done. */
857 bool memOpDone;
858
859 /** Is this instruction's memory access uncacheable. */
860 bool uncacheable() { return isUncacheable; }
861
862 /** Has this instruction generated a memory request. */
863 bool hasRequest() { return reqMade; }
864
865 public:
866 /** Load queue index. */
867 int16_t lqIdx;
868
869 /** Store queue index. */
870 int16_t sqIdx;
871
872 /** Iterator pointing to this BaseDynInst in the list of all insts. */
873 ListIt instListIt;
874
875 /** Returns iterator to this instruction in the list of all insts. */
876 ListIt &getInstListIt() { return instListIt; }
877
878 /** Sets iterator for this instruction in the list of all insts. */
879 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
880
881 public:
882 /** Returns the number of consecutive store conditional failures. */
883 unsigned readStCondFailures()
884 { return thread->storeCondFailures; }
885
886 /** Sets the number of consecutive store conditional failures. */
887 void setStCondFailures(unsigned sc_failures)
888 { thread->storeCondFailures = sc_failures; }
889};
890
891template<class Impl>
892Fault
893BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
894 unsigned size, unsigned flags)
895{
896 reqMade = true;
897 Request *req = new Request(asid, addr, size, flags, this->PC,
898 thread->contextId(), threadNumber);
899
900 Request *sreqLow = NULL;
901 Request *sreqHigh = NULL;
902
903 // Only split the request if the ISA supports unaligned accesses.
904 if (TheISA::HasUnalignedMemAcc) {
905 splitRequest(req, sreqLow, sreqHigh);
906 }
907 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
908
909 if (fault == NoFault) {
910 effAddr = req->getVaddr();
911 effAddrValid = true;
912 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
913 } else {
914 // Commit will have to clean up whatever happened. Set this
915 // instruction as executed.
916 this->setExecuted();
917 }
918
919 if (fault != NoFault) {
920 // Return a fixed value to keep simulation deterministic even
921 // along misspeculated paths.
922 bzero(data, size);
923 }
924
925 if (traceData) {
926 traceData->setAddr(addr);
927 }
928
929 return fault;
930}
931
932template<class Impl>
933template<class T>
934inline Fault
935BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
936{
937 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
938
939 data = TheISA::gtoh(data);
940
941 if (traceData) {
942 traceData->setData(data);
943 }
944
945 return fault;
946}
947
948template<class Impl>
949Fault
950BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
951 Addr addr, unsigned flags, uint64_t *res)
952{
953 if (traceData) {
954 traceData->setAddr(addr);
955 }
956
957 reqMade = true;
958 Request *req = new Request(asid, addr, size, flags, this->PC,
959 thread->contextId(), threadNumber);
960
961 Request *sreqLow = NULL;
962 Request *sreqHigh = NULL;
963
964 // Only split the request if the ISA supports unaligned accesses.
965 if (TheISA::HasUnalignedMemAcc) {
966 splitRequest(req, sreqLow, sreqHigh);
967 }
968 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
969
970 if (fault == NoFault) {
971 effAddr = req->getVaddr();
972 effAddrValid = true;
973 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
974 }
975
976 return fault;
977}
978
979template<class Impl>
980template<class T>
981inline Fault
982BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
983{
984 if (traceData) {
985 traceData->setData(data);
986 }
987 data = TheISA::htog(data);
988 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
989}
990
991template<class Impl>
992inline void
993BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
994 RequestPtr &sreqHigh)
995{
996 // Check to see if the request crosses the next level block boundary.
997 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
998 Addr addr = req->getVaddr();
999 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
1000 assert(split_addr <= addr || split_addr - addr < block_size);
1001
1002 // Spans two blocks.
1003 if (split_addr > addr) {
1004 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1005 }
1006}
1007
1008template<class Impl>
1009inline void
1010BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1011 RequestPtr sreqHigh, uint64_t *res,
1012 BaseTLB::Mode mode)
1013{
1014 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1015 WholeTranslationState *state =
1016 new WholeTranslationState(req, NULL, res, mode);
1017
1018 // One translation if the request isn't split.
1019 DataTranslation<BaseDynInst<Impl> > *trans =
1020 new DataTranslation<BaseDynInst<Impl> >(this, state);
1021 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1022 } else {
1023 WholeTranslationState *state =
1024 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1025
1026 // Two translations when the request is split.
1027 DataTranslation<BaseDynInst<Impl> > *stransLow =
1028 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
1029 DataTranslation<BaseDynInst<Impl> > *stransHigh =
1030 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
1031
1032 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1033 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1034 }
1035}
1036
1037template<class Impl>
1038inline void
1039BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1040{
1041 fault = state->getFault();
1042
1043 if (state->isUncacheable())
1044 isUncacheable = true;
1045
1046 if (fault == NoFault) {
1047 physEffAddr = state->getPaddr();
1048 memReqFlags = state->getFlags();
1049
1050 if (state->mainReq->isCondSwap()) {
1051 assert(state->res);
1052 state->mainReq->setExtraData(*state->res);
1053 }
1054
1055 } else {
1056 state->deleteReqs();
1057 }
1058 delete state;
1059}
1060
1061#endif // __CPU_BASE_DYN_INST_HH__