1/*
2 * Copyright (c) 2011,2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * Copyright (c) 2009 The University of Edinburgh
17 * All rights reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are
21 * met: redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer;
23 * redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution;
26 * neither the name of the copyright holders nor the names of its
27 * contributors may be used to endorse or promote products derived from
28 * this software without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
35 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
36 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
37 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
38 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 * Authors: Kevin Lim
43 * Timothy M. Jones
44 */
45
46#ifndef __CPU_BASE_DYN_INST_HH__
47#define __CPU_BASE_DYN_INST_HH__
48
49#include <array>
50#include <bitset>
51#include <list>
52#include <string>
53#include <queue>
54
55#include "arch/generic/tlb.hh"
56#include "arch/utility.hh"
57#include "base/trace.hh"
58#include "config/the_isa.hh"
59#include "cpu/checker/cpu.hh"
60#include "cpu/o3/comm.hh"
61#include "cpu/exec_context.hh"
62#include "cpu/exetrace.hh"
63#include "cpu/inst_seq.hh"
64#include "cpu/op_class.hh"
65#include "cpu/static_inst.hh"
66#include "cpu/translation.hh"
67#include "mem/packet.hh"
68#include "mem/request.hh"
69#include "sim/byteswap.hh"
70#include "sim/system.hh"
71
72/**
73 * @file
74 * Defines a dynamic instruction context.
75 */
76
77template <class Impl>
78class BaseDynInst : public ExecContext, public RefCounted
79{
80 public:
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87
88 // The DynInstPtr type.
89 typedef typename Impl::DynInstPtr DynInstPtr;
90 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
91
92 // The list of instructions iterator type.
93 typedef typename std::list<DynInstPtr>::iterator ListIt;
94
95 enum {
96 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
97 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
98 };
99
100 union Result {
101 uint64_t integer;
102 double dbl;
103 void set(uint64_t i) { integer = i; }
104 void set(double d) { dbl = d; }
105 void get(uint64_t& i) { i = integer; }
106 void get(double& d) { d = dbl; }
107 };
108
109 protected:
110 enum Status {
111 IqEntry, /// Instruction is in the IQ
112 RobEntry, /// Instruction is in the ROB
113 LsqEntry, /// Instruction is in the LSQ
114 Completed, /// Instruction has completed
115 ResultReady, /// Instruction has its result
116 CanIssue, /// Instruction can issue and execute
117 Issued, /// Instruction has issued
118 Executed, /// Instruction has executed
119 CanCommit, /// Instruction can commit
120 AtCommit, /// Instruction has reached commit
121 Committed, /// Instruction has committed
122 Squashed, /// Instruction is squashed
123 SquashedInIQ, /// Instruction is squashed in the IQ
124 SquashedInLSQ, /// Instruction is squashed in the LSQ
125 SquashedInROB, /// Instruction is squashed in the ROB
126 RecoverInst, /// Is a recover instruction
127 BlockingInst, /// Is a blocking instruction
128 ThreadsyncWait, /// Is a thread synchronization instruction
129 SerializeBefore, /// Needs to serialize on
130 /// instructions ahead of it
131 SerializeAfter, /// Needs to serialize instructions behind it
132 SerializeHandled, /// Serialization has been handled
133 NumStatus
134 };
135
136 enum Flags {
137 TranslationStarted,
138 TranslationCompleted,
139 PossibleLoadViolation,
140 HitExternalSnoop,
141 EffAddrValid,
142 RecordResult,
143 Predicate,
144 PredTaken,
145 /** Whether or not the effective address calculation is completed.
146 * @todo: Consider if this is necessary or not.
147 */
148 EACalcDone,
149 IsStrictlyOrdered,
150 ReqMade,
151 MemOpDone,
152 MaxFlags
153 };
154
155 public:
156 /** The sequence number of the instruction. */
157 InstSeqNum seqNum;
158
159 /** The StaticInst used by this BaseDynInst. */
160 const StaticInstPtr staticInst;
161
162 /** Pointer to the Impl's CPU object. */
163 ImplCPU *cpu;
164
165 BaseCPU *getCpuPtr() { return cpu; }
166
167 /** Pointer to the thread state. */
168 ImplState *thread;
169
170 /** The kind of fault this instruction has generated. */
171 Fault fault;
172
173 /** InstRecord that tracks this instructions. */
174 Trace::InstRecord *traceData;
175
176 protected:
177 /** The result of the instruction; assumes an instruction can have many
178 * destination registers.
179 */
180 std::queue<Result> instResult;
181
182 /** PC state for this instruction. */
183 TheISA::PCState pc;
184
185 /* An amalgamation of a lot of boolean values into one */
186 std::bitset<MaxFlags> instFlags;
187
188 /** The status of this BaseDynInst. Several bits can be set. */
189 std::bitset<NumStatus> status;
190
191 /** Whether or not the source register is ready.
192 * @todo: Not sure this should be here vs the derived class.
193 */
194 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
195
196 public:
197 /** The thread this instruction is from. */
198 ThreadID threadNumber;
199
200 /** Iterator pointing to this BaseDynInst in the list of all insts. */
201 ListIt instListIt;
202
203 ////////////////////// Branch Data ///////////////
204 /** Predicted PC state after this instruction. */
205 TheISA::PCState predPC;
206
207 /** The Macroop if one exists */
208 const StaticInstPtr macroop;
209
210 /** How many source registers are ready. */
211 uint8_t readyRegs;
212
213 public:
214 /////////////////////// Load Store Data //////////////////////
215 /** The effective virtual address (lds & stores only). */
216 Addr effAddr;
217
218 /** The effective physical address. */
219 Addr physEffAddrLow;
220
221 /** The effective physical address
222 * of the second request for a split request
223 */
224 Addr physEffAddrHigh;
225
226 /** The memory request flags (from translation). */
227 unsigned memReqFlags;
228
229 /** data address space ID, for loads & stores. */
230 short asid;
231
232 /** The size of the request */
233 uint8_t effSize;
234
235 /** Pointer to the data for the memory access. */
236 uint8_t *memData;
237
238 /** Load queue index. */
239 int16_t lqIdx;
240
241 /** Store queue index. */
242 int16_t sqIdx;
243
244
245 /////////////////////// TLB Miss //////////////////////
246 /**
247 * Saved memory requests (needed when the DTB address translation is
248 * delayed due to a hw page table walk).
249 */
250 RequestPtr savedReq;
251 RequestPtr savedSreqLow;
252 RequestPtr savedSreqHigh;
253
254 /////////////////////// Checker //////////////////////
255 // Need a copy of main request pointer to verify on writes.
256 RequestPtr reqToVerify;
257
258 private:
259 /** Instruction effective address.
260 * @todo: Consider if this is necessary or not.
261 */
262 Addr instEffAddr;
263
264 protected:
265 /** Flattened register index of the destination registers of this
266 * instruction.
267 */
268 std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx;
269
270 /** Physical register index of the destination registers of this
271 * instruction.
272 */
273 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx;
274
275 /** Physical register index of the source registers of this
276 * instruction.
277 */
278 std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx;
279
280 /** Physical register index of the previous producers of the
281 * architected destinations.
282 */
283 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx;
284
285
286 public:
287 /** Records changes to result? */
288 void recordResult(bool f) { instFlags[RecordResult] = f; }
289
290 /** Is the effective virtual address valid. */
291 bool effAddrValid() const { return instFlags[EffAddrValid]; }
292
293 /** Whether or not the memory operation is done. */
294 bool memOpDone() const { return instFlags[MemOpDone]; }
295 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
296
297
298 ////////////////////////////////////////////
299 //
300 // INSTRUCTION EXECUTION
301 //
302 ////////////////////////////////////////////
303
304 void demapPage(Addr vaddr, uint64_t asn)
305 {
306 cpu->demapPage(vaddr, asn);
307 }
308 void demapInstPage(Addr vaddr, uint64_t asn)
309 {
310 cpu->demapPage(vaddr, asn);
311 }
312 void demapDataPage(Addr vaddr, uint64_t asn)
313 {
314 cpu->demapPage(vaddr, asn);
315 }
316
317 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
318
319 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
320 Request::Flags flags, uint64_t *res);
321
322 /** Splits a request in two if it crosses a dcache block. */
323 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
324 RequestPtr &sreqHigh);
325
326 /** Initiate a DTB address translation. */
327 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
328 RequestPtr sreqHigh, uint64_t *res,
329 BaseTLB::Mode mode);
330
331 /** Finish a DTB address translation. */
332 void finishTranslation(WholeTranslationState *state);
333
334 /** True if the DTB address translation has started. */
335 bool translationStarted() const { return instFlags[TranslationStarted]; }
336 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
337
338 /** True if the DTB address translation has completed. */
339 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
340 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
341
342 /** True if this address was found to match a previous load and they issued
343 * out of order. If that happend, then it's only a problem if an incoming
344 * snoop invalidate modifies the line, in which case we need to squash.
345 * If nothing modified the line the order doesn't matter.
346 */
347 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
348 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
349
350 /** True if the address hit a external snoop while sitting in the LSQ.
351 * If this is true and a older instruction sees it, this instruction must
352 * reexecute
353 */
354 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
355 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
356
357 /**
358 * Returns true if the DTB address translation is being delayed due to a hw
359 * page table walk.
360 */
361 bool isTranslationDelayed() const
362 {
363 return (translationStarted() && !translationCompleted());
364 }
365
366 public:
367#ifdef DEBUG
368 void dumpSNList();
369#endif
370
371 /** Returns the physical register index of the i'th destination
372 * register.
373 */
374 PhysRegIndex renamedDestRegIdx(int idx) const
375 {
376 return _destRegIdx[idx];
377 }
378
379 /** Returns the physical register index of the i'th source register. */
380 PhysRegIndex renamedSrcRegIdx(int idx) const
381 {
382 assert(TheISA::MaxInstSrcRegs > idx);
383 return _srcRegIdx[idx];
384 }
385
386 /** Returns the flattened register index of the i'th destination
387 * register.
388 */
389 TheISA::RegIndex flattenedDestRegIdx(int idx) const
390 {
391 return _flatDestRegIdx[idx];
392 }
393
394 /** Returns the physical register index of the previous physical register
395 * that remapped to the same logical register index.
396 */
397 PhysRegIndex prevDestRegIdx(int idx) const
398 {
399 return _prevDestRegIdx[idx];
400 }
401
402 /** Renames a destination register to a physical register. Also records
403 * the previous physical register that the logical register mapped to.
404 */
405 void renameDestReg(int idx,
406 PhysRegIndex renamed_dest,
407 PhysRegIndex previous_rename)
408 {
409 _destRegIdx[idx] = renamed_dest;
410 _prevDestRegIdx[idx] = previous_rename;
411 }
412
413 /** Renames a source logical register to the physical register which
414 * has/will produce that logical register's result.
415 * @todo: add in whether or not the source register is ready.
416 */
417 void renameSrcReg(int idx, PhysRegIndex renamed_src)
418 {
419 _srcRegIdx[idx] = renamed_src;
420 }
421
422 /** Flattens a destination architectural register index into a logical
423 * index.
424 */
425 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
426 {
427 _flatDestRegIdx[idx] = flattened_dest;
428 }
429 /** BaseDynInst constructor given a binary instruction.
430 * @param staticInst A StaticInstPtr to the underlying instruction.
431 * @param pc The PC state for the instruction.
432 * @param predPC The predicted next PC state for the instruction.
433 * @param seq_num The sequence number of the instruction.
434 * @param cpu Pointer to the instruction's CPU.
435 */
436 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
437 TheISA::PCState pc, TheISA::PCState predPC,
438 InstSeqNum seq_num, ImplCPU *cpu);
439
440 /** BaseDynInst constructor given a StaticInst pointer.
441 * @param _staticInst The StaticInst for this BaseDynInst.
442 */
443 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
444
445 /** BaseDynInst destructor. */
446 ~BaseDynInst();
447
448 private:
449 /** Function to initialize variables in the constructors. */
450 void initVars();
451
452 public:
453 /** Dumps out contents of this BaseDynInst. */
454 void dump();
455
456 /** Dumps out contents of this BaseDynInst into given string. */
457 void dump(std::string &outstring);
458
459 /** Read this CPU's ID. */
460 int cpuId() const { return cpu->cpuId(); }
461
462 /** Read this CPU's Socket ID. */
463 uint32_t socketId() const { return cpu->socketId(); }
464
465 /** Read this CPU's data requestor ID */
466 MasterID masterId() const { return cpu->dataMasterId(); }
467
468 /** Read this context's system-wide ID **/
469 ContextID contextId() const { return thread->contextId(); }
470
471 /** Returns the fault type. */
472 Fault getFault() const { return fault; }
473
474 /** Checks whether or not this instruction has had its branch target
475 * calculated yet. For now it is not utilized and is hacked to be
476 * always false.
477 * @todo: Actually use this instruction.
478 */
479 bool doneTargCalc() { return false; }
480
481 /** Set the predicted target of this current instruction. */
482 void setPredTarg(const TheISA::PCState &_predPC)
483 {
484 predPC = _predPC;
485 }
486
487 const TheISA::PCState &readPredTarg() { return predPC; }
488
489 /** Returns the predicted PC immediately after the branch. */
490 Addr predInstAddr() { return predPC.instAddr(); }
491
492 /** Returns the predicted PC two instructions after the branch */
493 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
494
495 /** Returns the predicted micro PC after the branch */
496 Addr predMicroPC() { return predPC.microPC(); }
497
498 /** Returns whether the instruction was predicted taken or not. */
499 bool readPredTaken()
500 {
501 return instFlags[PredTaken];
502 }
503
504 void setPredTaken(bool predicted_taken)
505 {
506 instFlags[PredTaken] = predicted_taken;
507 }
508
509 /** Returns whether the instruction mispredicted. */
510 bool mispredicted()
511 {
512 TheISA::PCState tempPC = pc;
513 TheISA::advancePC(tempPC, staticInst);
514 return !(tempPC == predPC);
515 }
516
517 //
518 // Instruction types. Forward checks to StaticInst object.
519 //
520 bool isNop() const { return staticInst->isNop(); }
521 bool isMemRef() const { return staticInst->isMemRef(); }
522 bool isLoad() const { return staticInst->isLoad(); }
523 bool isStore() const { return staticInst->isStore(); }
524 bool isStoreConditional() const
525 { return staticInst->isStoreConditional(); }
526 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
527 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
528 bool isInteger() const { return staticInst->isInteger(); }
529 bool isFloating() const { return staticInst->isFloating(); }
530 bool isControl() const { return staticInst->isControl(); }
531 bool isCall() const { return staticInst->isCall(); }
532 bool isReturn() const { return staticInst->isReturn(); }
533 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
534 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
535 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
536 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
537 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
538 bool isThreadSync() const { return staticInst->isThreadSync(); }
539 bool isSerializing() const { return staticInst->isSerializing(); }
540 bool isSerializeBefore() const
541 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
542 bool isSerializeAfter() const
543 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
544 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
545 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
546 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
547 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
548 bool isQuiesce() const { return staticInst->isQuiesce(); }
549 bool isIprAccess() const { return staticInst->isIprAccess(); }
550 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
551 bool isSyscall() const { return staticInst->isSyscall(); }
552 bool isMacroop() const { return staticInst->isMacroop(); }
553 bool isMicroop() const { return staticInst->isMicroop(); }
554 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
555 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
556 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
557 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
558
559 /** Temporarily sets this instruction as a serialize before instruction. */
560 void setSerializeBefore() { status.set(SerializeBefore); }
561
562 /** Clears the serializeBefore part of this instruction. */
563 void clearSerializeBefore() { status.reset(SerializeBefore); }
564
565 /** Checks if this serializeBefore is only temporarily set. */
566 bool isTempSerializeBefore() { return status[SerializeBefore]; }
567
568 /** Temporarily sets this instruction as a serialize after instruction. */
569 void setSerializeAfter() { status.set(SerializeAfter); }
570
571 /** Clears the serializeAfter part of this instruction.*/
572 void clearSerializeAfter() { status.reset(SerializeAfter); }
573
574 /** Checks if this serializeAfter is only temporarily set. */
575 bool isTempSerializeAfter() { return status[SerializeAfter]; }
576
577 /** Sets the serialization part of this instruction as handled. */
578 void setSerializeHandled() { status.set(SerializeHandled); }
579
580 /** Checks if the serialization part of this instruction has been
581 * handled. This does not apply to the temporary serializing
582 * state; it only applies to this instruction's own permanent
583 * serializing state.
584 */
585 bool isSerializeHandled() { return status[SerializeHandled]; }
586
587 /** Returns the opclass of this instruction. */
588 OpClass opClass() const { return staticInst->opClass(); }
589
590 /** Returns the branch target address. */
591 TheISA::PCState branchTarget() const
592 { return staticInst->branchTarget(pc); }
593
594 /** Returns the number of source registers. */
595 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
596
597 /** Returns the number of destination registers. */
598 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
599
600 // the following are used to track physical register usage
601 // for machines with separate int & FP reg files
602 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
603 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
604 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
605
606 /** Returns the logical register index of the i'th destination register. */
607 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
608
609 /** Returns the logical register index of the i'th source register. */
610 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
611
612 /** Pops a result off the instResult queue */
613 template <class T>
614 void popResult(T& t)
615 {
616 if (!instResult.empty()) {
617 instResult.front().get(t);
618 instResult.pop();
619 }
620 }
621
622 /** Read the most recent result stored by this instruction */
623 template <class T>
624 void readResult(T& t)
625 {
626 instResult.back().get(t);
627 }
628
629 /** Pushes a result onto the instResult queue */
630 template <class T>
631 void setResult(T t)
632 {
633 if (instFlags[RecordResult]) {
634 Result instRes;
635 instRes.set(t);
636 instResult.push(instRes);
637 }
638 }
639
640 /** Records an integer register being set to a value. */
641 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
642 {
643 setResult<uint64_t>(val);
644 }
645
646 /** Records a CC register being set to a value. */
647 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
648 {
649 setResult<uint64_t>(val);
650 }
651
652 /** Records an fp register being set to a value. */
653 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
654 {
655 setResult<double>(val);
656 }
657
658 /** Records an fp register being set to an integer value. */
659 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
660 {
661 setResult<uint64_t>(val);
662 }
663
664 /** Records that one of the source registers is ready. */
665 void markSrcRegReady();
666
667 /** Marks a specific register as ready. */
668 void markSrcRegReady(RegIndex src_idx);
669
670 /** Returns if a source register is ready. */
671 bool isReadySrcRegIdx(int idx) const
672 {
673 return this->_readySrcRegIdx[idx];
674 }
675
676 /** Sets this instruction as completed. */
677 void setCompleted() { status.set(Completed); }
678
679 /** Returns whether or not this instruction is completed. */
680 bool isCompleted() const { return status[Completed]; }
681
682 /** Marks the result as ready. */
683 void setResultReady() { status.set(ResultReady); }
684
685 /** Returns whether or not the result is ready. */
686 bool isResultReady() const { return status[ResultReady]; }
687
688 /** Sets this instruction as ready to issue. */
689 void setCanIssue() { status.set(CanIssue); }
690
691 /** Returns whether or not this instruction is ready to issue. */
692 bool readyToIssue() const { return status[CanIssue]; }
693
694 /** Clears this instruction being able to issue. */
695 void clearCanIssue() { status.reset(CanIssue); }
696
697 /** Sets this instruction as issued from the IQ. */
698 void setIssued() { status.set(Issued); }
699
700 /** Returns whether or not this instruction has issued. */
701 bool isIssued() const { return status[Issued]; }
702
703 /** Clears this instruction as being issued. */
704 void clearIssued() { status.reset(Issued); }
705
706 /** Sets this instruction as executed. */
707 void setExecuted() { status.set(Executed); }
708
709 /** Returns whether or not this instruction has executed. */
710 bool isExecuted() const { return status[Executed]; }
711
712 /** Sets this instruction as ready to commit. */
713 void setCanCommit() { status.set(CanCommit); }
714
715 /** Clears this instruction as being ready to commit. */
716 void clearCanCommit() { status.reset(CanCommit); }
717
718 /** Returns whether or not this instruction is ready to commit. */
719 bool readyToCommit() const { return status[CanCommit]; }
720
721 void setAtCommit() { status.set(AtCommit); }
722
723 bool isAtCommit() { return status[AtCommit]; }
724
725 /** Sets this instruction as committed. */
726 void setCommitted() { status.set(Committed); }
727
728 /** Returns whether or not this instruction is committed. */
729 bool isCommitted() const { return status[Committed]; }
730
731 /** Sets this instruction as squashed. */
732 void setSquashed() { status.set(Squashed); }
733
734 /** Returns whether or not this instruction is squashed. */
735 bool isSquashed() const { return status[Squashed]; }
736
737 //Instruction Queue Entry
738 //-----------------------
739 /** Sets this instruction as a entry the IQ. */
740 void setInIQ() { status.set(IqEntry); }
741
742 /** Sets this instruction as a entry the IQ. */
743 void clearInIQ() { status.reset(IqEntry); }
744
745 /** Returns whether or not this instruction has issued. */
746 bool isInIQ() const { return status[IqEntry]; }
747
748 /** Sets this instruction as squashed in the IQ. */
749 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
750
751 /** Returns whether or not this instruction is squashed in the IQ. */
752 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
753
754
755 //Load / Store Queue Functions
756 //-----------------------
757 /** Sets this instruction as a entry the LSQ. */
758 void setInLSQ() { status.set(LsqEntry); }
759
760 /** Sets this instruction as a entry the LSQ. */
761 void removeInLSQ() { status.reset(LsqEntry); }
762
763 /** Returns whether or not this instruction is in the LSQ. */
764 bool isInLSQ() const { return status[LsqEntry]; }
765
766 /** Sets this instruction as squashed in the LSQ. */
767 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
768
769 /** Returns whether or not this instruction is squashed in the LSQ. */
770 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
771
772
773 //Reorder Buffer Functions
774 //-----------------------
775 /** Sets this instruction as a entry the ROB. */
776 void setInROB() { status.set(RobEntry); }
777
778 /** Sets this instruction as a entry the ROB. */
779 void clearInROB() { status.reset(RobEntry); }
780
781 /** Returns whether or not this instruction is in the ROB. */
782 bool isInROB() const { return status[RobEntry]; }
783
784 /** Sets this instruction as squashed in the ROB. */
785 void setSquashedInROB() { status.set(SquashedInROB); }
786
787 /** Returns whether or not this instruction is squashed in the ROB. */
788 bool isSquashedInROB() const { return status[SquashedInROB]; }
789
790 /** Read the PC state of this instruction. */
791 TheISA::PCState pcState() const { return pc; }
792
793 /** Set the PC state of this instruction. */
794 void pcState(const TheISA::PCState &val) { pc = val; }
795
796 /** Read the PC of this instruction. */
797 Addr instAddr() const { return pc.instAddr(); }
798
799 /** Read the PC of the next instruction. */
800 Addr nextInstAddr() const { return pc.nextInstAddr(); }
801
802 /**Read the micro PC of this instruction. */
803 Addr microPC() const { return pc.microPC(); }
804
805 bool readPredicate()
806 {
807 return instFlags[Predicate];
808 }
809
810 void setPredicate(bool val)
811 {
812 instFlags[Predicate] = val;
813
814 if (traceData) {
815 traceData->setPredicate(val);
816 }
817 }
818
819 /** Sets the ASID. */
820 void setASID(short addr_space_id) { asid = addr_space_id; }
821
822 /** Sets the thread id. */
823 void setTid(ThreadID tid) { threadNumber = tid; }
824
825 /** Sets the pointer to the thread state. */
826 void setThreadState(ImplState *state) { thread = state; }
827
828 /** Returns the thread context. */
829 ThreadContext *tcBase() { return thread->getTC(); }
830
831 public:
832 /** Sets the effective address. */
833 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
834
835 /** Returns the effective address. */
836 Addr getEA() const { return instEffAddr; }
837
838 /** Returns whether or not the eff. addr. calculation has been completed. */
839 bool doneEACalc() { return instFlags[EACalcDone]; }
840
841 /** Returns whether or not the eff. addr. source registers are ready. */
842 bool eaSrcsReady();
843
844 /** Is this instruction's memory access strictly ordered? */
845 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
846
847 /** Has this instruction generated a memory request. */
848 bool hasRequest() { return instFlags[ReqMade]; }
849
850 /** Returns iterator to this instruction in the list of all insts. */
851 ListIt &getInstListIt() { return instListIt; }
852
853 /** Sets iterator for this instruction in the list of all insts. */
854 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
855
856 public:
857 /** Returns the number of consecutive store conditional failures. */
858 unsigned int readStCondFailures() const
859 { return thread->storeCondFailures; }
860
861 /** Sets the number of consecutive store conditional failures. */
862 void setStCondFailures(unsigned int sc_failures)
863 { thread->storeCondFailures = sc_failures; }
864
865 public:
866 // monitor/mwait funtions
867 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
868 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
869 void mwaitAtomic(ThreadContext *tc)
870 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
871 AddressMonitor *getAddrMonitor()
872 { return cpu->getCpuAddrMonitor(threadNumber); }
873};
874
875template<class Impl>
876Fault
877BaseDynInst::initiateMemRead(Addr addr, unsigned size,
878 Request::Flags flags)
879{
880 instFlags[ReqMade] = true;
881 Request *req = NULL;
882 Request *sreqLow = NULL;
883 Request *sreqHigh = NULL;
884
885 if (instFlags[ReqMade] && translationStarted()) {
886 req = savedReq;
887 sreqLow = savedSreqLow;
888 sreqHigh = savedSreqHigh;
889 } else {
890 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
891 thread->contextId());
892
893 req->taskId(cpu->taskId());
894
895 // Only split the request if the ISA supports unaligned accesses.
896 if (TheISA::HasUnalignedMemAcc) {
897 splitRequest(req, sreqLow, sreqHigh);
898 }
899 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
900 }
901
902 if (translationCompleted()) {
903 if (fault == NoFault) {
904 effAddr = req->getVaddr();
905 effSize = size;
906 instFlags[EffAddrValid] = true;
907
908 if (cpu->checker) {
909 if (reqToVerify != NULL) {
910 delete reqToVerify;
911 }
912 reqToVerify = new Request(*req);
913 }
914 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
915 } else {
916 // Commit will have to clean up whatever happened. Set this
917 // instruction as executed.
918 this->setExecuted();
919 }
920 }
921
922 if (traceData)
923 traceData->setMem(addr, size, flags);
924
925 return fault;
926}
927
928template<class Impl>
929Fault
930BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
931 Request::Flags flags, uint64_t *res)
932{
933 if (traceData)
934 traceData->setMem(addr, size, flags);
935
936 instFlags[ReqMade] = true;
937 Request *req = NULL;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
940
941 if (instFlags[ReqMade] && translationStarted()) {
942 req = savedReq;
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
945 } else {
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
947 thread->contextId());
948
949 req->taskId(cpu->taskId());
950
951 // Only split the request if the ISA supports unaligned accesses.
952 if (TheISA::HasUnalignedMemAcc) {
953 splitRequest(req, sreqLow, sreqHigh);
954 }
955 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
956 }
957
958 if (fault == NoFault && translationCompleted()) {
959 effAddr = req->getVaddr();
960 effSize = size;
961 instFlags[EffAddrValid] = true;
962
963 if (cpu->checker) {
964 if (reqToVerify != NULL) {
965 delete reqToVerify;
966 }
967 reqToVerify = new Request(*req);
968 }
969 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
970 }
971
972 return fault;
973}
974
975template<class Impl>
976inline void
977BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
978 RequestPtr &sreqHigh)
979{
980 // Check to see if the request crosses the next level block boundary.
981 unsigned block_size = cpu->cacheLineSize();
982 Addr addr = req->getVaddr();
983 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
984 assert(split_addr <= addr || split_addr - addr < block_size);
985
986 // Spans two blocks.
987 if (split_addr > addr) {
988 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
989 }
990}
991
992template<class Impl>
993inline void
994BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
995 RequestPtr sreqHigh, uint64_t *res,
996 BaseTLB::Mode mode)
997{
998 translationStarted(true);
999
1000 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1001 WholeTranslationState *state =
1002 new WholeTranslationState(req, NULL, res, mode);
1003
1004 // One translation if the request isn't split.
1005 DataTranslation<BaseDynInstPtr> *trans =
1006 new DataTranslation<BaseDynInstPtr>(this, state);
1007
1008 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1009
1010 if (!translationCompleted()) {
1011 // The translation isn't yet complete, so we can't possibly have a
1012 // fault. Overwrite any existing fault we might have from a previous
1013 // execution of this instruction (e.g. an uncachable load that
1014 // couldn't execute because it wasn't at the head of the ROB).
1015 fault = NoFault;
1016
1017 // Save memory requests.
1018 savedReq = state->mainReq;
1019 savedSreqLow = state->sreqLow;
1020 savedSreqHigh = state->sreqHigh;
1021 }
1022 } else {
1023 WholeTranslationState *state =
1024 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1025
1026 // Two translations when the request is split.
1027 DataTranslation<BaseDynInstPtr> *stransLow =
1028 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1029 DataTranslation<BaseDynInstPtr> *stransHigh =
1030 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1031
1032 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1033 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1034
1035 if (!translationCompleted()) {
1036 // The translation isn't yet complete, so we can't possibly have a
1037 // fault. Overwrite any existing fault we might have from a previous
1038 // execution of this instruction (e.g. an uncachable load that
1039 // couldn't execute because it wasn't at the head of the ROB).
1040 fault = NoFault;
1041
1042 // Save memory requests.
1043 savedReq = state->mainReq;
1044 savedSreqLow = state->sreqLow;
1045 savedSreqHigh = state->sreqHigh;
1046 }
1047 }
1048}
1049
1050template<class Impl>
1051inline void
1052BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1053{
1054 fault = state->getFault();
1055
1056 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1057
1058 if (fault == NoFault) {
1059 // save Paddr for a single req
1060 physEffAddrLow = state->getPaddr();
1061
1062 // case for the request that has been split
1063 if (state->isSplit) {
1064 physEffAddrLow = state->sreqLow->getPaddr();
1065 physEffAddrHigh = state->sreqHigh->getPaddr();
1066 }
1067
1068 memReqFlags = state->getFlags();
1069
1070 if (state->mainReq->isCondSwap()) {
1071 assert(state->res);
1072 state->mainReq->setExtraData(*state->res);
1073 }
1074
1075 } else {
1076 state->deleteReqs();
1077 }
1078 delete state;
1079
1080 translationCompleted(true);
1081}
1082
1083#endif // __CPU_BASE_DYN_INST_HH__