1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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852};
853
854template<class Impl>
855template<class T>
856inline Fault
857BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
858{
859 reqMade = true;
860 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
861 thread->contextId(), threadNumber);
862
863 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
864
865 if (req->isUncacheable())
866 isUncacheable = true;
867
868 if (fault == NoFault) {
869 effAddr = req->getVaddr();

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907BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
908{
909 if (traceData) {
910 traceData->setAddr(addr);
911 traceData->setData(data);
912 }
913
914 reqMade = true;
915 Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
916 thread->contextId(), threadNumber);
917
918 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
919
920 if (req->isUncacheable())
921 isUncacheable = true;
922
923 if (fault == NoFault) {
924 effAddr = req->getVaddr();

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