1/*
2 * Copyright (c) 2011,2013,2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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127 TranslationStarted,
128 TranslationCompleted,
129 PossibleLoadViolation,
130 HitExternalSnoop,
131 EffAddrValid,
132 RecordResult,
133 Predicate,
134 PredTaken,
135 IsStrictlyOrdered,
136 ReqMade,
137 MemOpDone,
138 MaxFlags
139 };
140
141 public:
142 /** The sequence number of the instruction. */

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236 RequestPtr savedReq;
237 RequestPtr savedSreqLow;
238 RequestPtr savedSreqHigh;
239
240 /////////////////////// Checker //////////////////////
241 // Need a copy of main request pointer to verify on writes.
242 RequestPtr reqToVerify;
243
244 protected:
245 /** Flattened register index of the destination registers of this
246 * instruction.
247 */
248 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
249
250 /** Physical register index of the destination registers of this
251 * instruction.

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844
845 /** Sets the pointer to the thread state. */
846 void setThreadState(ImplState *state) { thread = state; }
847
848 /** Returns the thread context. */
849 ThreadContext *tcBase() { return thread->getTC(); }
850
851 public:
852 /** Returns whether or not the eff. addr. source registers are ready. */
853 bool eaSrcsReady();
854
855 /** Is this instruction's memory access strictly ordered? */
856 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
857
858 /** Has this instruction generated a memory request. */
859 bool hasRequest() { return instFlags[ReqMade]; }

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