base.hh (9523:b8c8437f71d9) base.hh (9608:e2b6b86fda03)
1/*
1/*
2 * Copyright (c) 2011-2012 ARM Limited
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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112
113 /** The current OS process ID that is executing on this processor. This is
114 * used to generate a taskId */
115 uint32_t _pid;
116
117 /** Is the CPU switched out or active? */
118 bool _switchedOut;
119
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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112
113 /** The current OS process ID that is executing on this processor. This is
114 * used to generate a taskId */
115 uint32_t _pid;
116
117 /** Is the CPU switched out or active? */
118 bool _switchedOut;
119
120 /**
121 * Define a base class for the CPU ports (instruction and data)
122 * that is refined in the subclasses. This class handles the
123 * common cases, i.e. the functional accesses and the status
124 * changes and address range queries. The default behaviour for
125 * both atomic and timing access is to panic and the corresponding
126 * subclasses have to override these methods.
127 */
128 class CpuPort : public MasterPort
129 {
130 public:
131
132 /**
133 * Create a CPU port with a name and a structural owner.
134 *
135 * @param _name port name including the owner
136 * @param _name structural owner of this port
137 */
138 CpuPort(const std::string& _name, MemObject* _owner) :
139 MasterPort(_name, _owner)
140 { }
141
142 protected:
143
144 virtual bool recvTimingResp(PacketPtr pkt);
145
146 virtual void recvRetry();
147
148 virtual void recvFunctionalSnoop(PacketPtr pkt);
149
150 };
151
152 public:
153
154 /**
155 * Purely virtual method that returns a reference to the data
156 * port. All subclasses must implement this method.
157 *
158 * @return a reference to the data port
159 */
120 public:
121
122 /**
123 * Purely virtual method that returns a reference to the data
124 * port. All subclasses must implement this method.
125 *
126 * @return a reference to the data port
127 */
160 virtual CpuPort &getDataPort() = 0;
128 virtual MasterPort &getDataPort() = 0;
161
162 /**
163 * Purely virtual method that returns a reference to the instruction
164 * port. All subclasses must implement this method.
165 *
166 * @return a reference to the instruction port
167 */
129
130 /**
131 * Purely virtual method that returns a reference to the instruction
132 * port. All subclasses must implement this method.
133 *
134 * @return a reference to the instruction port
135 */
168 virtual CpuPort &getInstPort() = 0;
136 virtual MasterPort &getInstPort() = 0;
169
170 /** Reads this CPU's ID. */
171 int cpuId() { return _cpuId; }
172
173 /** Reads this CPU's unique data requestor ID */
174 MasterID dataMasterId() { return _dataMasterId; }
175 /** Reads this CPU's unique instruction requestor ID */
176 MasterID instMasterId() { return _instMasterId; }

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138 /** Reads this CPU's ID. */
139 int cpuId() { return _cpuId; }
140
141 /** Reads this CPU's unique data requestor ID */
142 MasterID dataMasterId() { return _dataMasterId; }
143 /** Reads this CPU's unique instruction requestor ID */
144 MasterID instMasterId() { return _instMasterId; }

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